JP6207190B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP6207190B2
JP6207190B2 JP2013061087A JP2013061087A JP6207190B2 JP 6207190 B2 JP6207190 B2 JP 6207190B2 JP 2013061087 A JP2013061087 A JP 2013061087A JP 2013061087 A JP2013061087 A JP 2013061087A JP 6207190 B2 JP6207190 B2 JP 6207190B2
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Japan
Prior art keywords
semiconductor chip
chip
alignment mark
semiconductor
logic chip
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Expired - Fee Related
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JP2013061087A
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English (en)
Japanese (ja)
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JP2014187184A (ja
JP2014187184A5 (https=
Inventor
木下　順弘
順弘 木下
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2013061087A priority Critical patent/JP6207190B2/ja
Priority to US14/194,890 priority patent/US9117826B2/en
Priority to TW103107287A priority patent/TWI596714B/zh
Priority to KR20140032580A priority patent/KR20140117285A/ko
Priority to CN201410106344.0A priority patent/CN104064479B/zh
Publication of JP2014187184A publication Critical patent/JP2014187184A/ja
Priority to HK14112039.2A priority patent/HK1198562B/xx
Priority to US14/803,486 priority patent/US20150325528A1/en
Publication of JP2014187184A5 publication Critical patent/JP2014187184A5/ja
Application granted granted Critical
Publication of JP6207190B2 publication Critical patent/JP6207190B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/101—Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/823—Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2013061087A 2013-03-22 2013-03-22 半導体装置の製造方法 Expired - Fee Related JP6207190B2 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2013061087A JP6207190B2 (ja) 2013-03-22 2013-03-22 半導体装置の製造方法
US14/194,890 US9117826B2 (en) 2013-03-22 2014-03-03 Method of manufacturing semiconductor device, and semiconductor device
TW103107287A TWI596714B (zh) 2013-03-22 2014-03-04 半導體裝置之製造方法
KR20140032580A KR20140117285A (ko) 2013-03-22 2014-03-20 반도체 장치의 제조 방법 및 반도체 장치
CN201410106344.0A CN104064479B (zh) 2013-03-22 2014-03-21 制造半导体装置的方法和半导体装置
HK14112039.2A HK1198562B (en) 2013-03-22 2014-11-28 Method of manufacturing semiconductor device, and semiconductor device
US14/803,486 US20150325528A1 (en) 2013-03-22 2015-07-20 Method of manufacturing semiconductor device, and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013061087A JP6207190B2 (ja) 2013-03-22 2013-03-22 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2014187184A JP2014187184A (ja) 2014-10-02
JP2014187184A5 JP2014187184A5 (https=) 2015-09-17
JP6207190B2 true JP6207190B2 (ja) 2017-10-04

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JP2013061087A Expired - Fee Related JP6207190B2 (ja) 2013-03-22 2013-03-22 半導体装置の製造方法

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US (2) US9117826B2 (https=)
JP (1) JP6207190B2 (https=)
KR (1) KR20140117285A (https=)
CN (1) CN104064479B (https=)
TW (1) TWI596714B (https=)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5876000B2 (ja) * 2012-06-11 2016-03-02 株式会社新川 ボンディング装置およびボンディング方法
KR102149150B1 (ko) * 2013-10-21 2020-08-28 삼성전자주식회사 전자 장치
JP6363854B2 (ja) * 2014-03-11 2018-07-25 キヤノン株式会社 形成方法、および物品の製造方法
TWI566305B (zh) * 2014-10-29 2017-01-11 巨擘科技股份有限公司 製造三維積體電路的方法
KR102012788B1 (ko) 2015-09-23 2019-08-21 주식회사 엘지화학 접착 필름, 반도체 장치의 제조 방법 및 반도체 장치
US9953963B2 (en) * 2015-11-06 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit process having alignment marks for underfill
KR102022267B1 (ko) * 2017-12-28 2019-09-18 삼성전자주식회사 팬-아웃 반도체 패키지
KR102164793B1 (ko) * 2018-08-16 2020-10-14 삼성전자주식회사 수동부품 내장기판
US10998247B2 (en) 2018-08-16 2021-05-04 Samsung Electronics Co., Ltd. Board with embedded passive component
DE102018133319A1 (de) * 2018-12-21 2020-06-25 Rittal Gmbh & Co. Kg Verfahren zur robotergestützten Verdrahtung von elektrischen Komponenten einer auf einer Montageplatte angeordneten elektrischen Schaltanlage
JP7120521B2 (ja) * 2018-12-25 2022-08-17 住友電工デバイス・イノベーション株式会社 電子部品の製造方法及び半導体装置の製造方法
US11430909B2 (en) 2019-07-31 2022-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. BSI chip with backside alignment mark
KR102728190B1 (ko) * 2019-09-10 2024-11-08 삼성전자주식회사 Pop 형태의 반도체 패키지
KR102739235B1 (ko) * 2019-09-24 2024-12-05 삼성전자주식회사 반도체 패키지
KR102766659B1 (ko) * 2020-05-20 2025-02-12 에스케이하이닉스 주식회사 코어 다이가 제어 다이에 스택된 스택 패키지
CN113889420B (zh) * 2020-07-03 2025-05-02 联华电子股份有限公司 半导体元件结构及接合二基板的方法
KR102914869B1 (ko) * 2020-12-16 2026-01-16 삼성전자 주식회사 자주형 ncf 시트 및 그를 포함하는 반도체 패키지
KR102822141B1 (ko) 2021-09-24 2025-06-18 삼성전자주식회사 정렬 검사용 광학 어셈블리, 이를 포함한 광학 장치, 다이 본딩 시스템 및 이를 이용한 다이 본딩 방법
KR20230083102A (ko) * 2021-12-02 2023-06-09 삼성전자주식회사 인쇄회로기판 및 이를 포함하는 반도체 패키지
TWI822230B (zh) * 2022-08-05 2023-11-11 友達光電股份有限公司 發光面板
CN118676109B (zh) * 2024-08-21 2024-11-19 芯爱科技(南京)有限公司 封装基板及其制法

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5434745A (en) * 1994-07-26 1995-07-18 White Microelectronics Div. Of Bowmar Instrument Corp. Stacked silicon die carrier assembly
JP3565319B2 (ja) * 1999-04-14 2004-09-15 シャープ株式会社 半導体装置及びその製造方法
JP2001217387A (ja) * 2000-02-03 2001-08-10 Rohm Co Ltd 半導体装置および半導体装置の製造方法
JP2002110742A (ja) * 2000-10-02 2002-04-12 Hitachi Ltd 半導体装置の製造方法および半導体製造装置
WO2002082540A1 (en) * 2001-03-30 2002-10-17 Fujitsu Limited Semiconductor device, method of manufacture thereof, and semiconductor substrate
KR100580635B1 (ko) * 2003-12-30 2006-05-16 삼성전자주식회사 전자소자 및 그 제조방법
JP4467318B2 (ja) * 2004-01-28 2010-05-26 Ｎｅｃエレクトロニクス株式会社 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法
JP2008109115A (ja) * 2006-09-26 2008-05-08 Sekisui Chem Co Ltd 半導体チップ積層体及びその製造方法
JP5049573B2 (ja) * 2006-12-12 2012-10-17 新光電気工業株式会社 半導体装置
JP2008177364A (ja) * 2007-01-18 2008-07-31 Denso Corp 半導体装置の製造方法及び半導体装置
US8723332B2 (en) * 2007-06-11 2014-05-13 Invensas Corporation Electrically interconnected stacked die assemblies
JP2010161102A (ja) * 2009-01-06 2010-07-22 Elpida Memory Inc 半導体装置
JP5185885B2 (ja) * 2009-05-21 2013-04-17 新光電気工業株式会社 配線基板および半導体装置
JP2011061004A (ja) * 2009-09-10 2011-03-24 Elpida Memory Inc 半導体装置及びその製造方法
US8796863B2 (en) * 2010-02-09 2014-08-05 Samsung Electronics Co., Ltd. Semiconductor memory devices and semiconductor packages
CN102169875B (zh) * 2010-02-26 2013-04-17 台湾积体电路制造股份有限公司 半导体装置及其制造方法
US8519537B2 (en) * 2010-02-26 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
JP2011187574A (ja) 2010-03-05 2011-09-22 Elpida Memory Inc 半導体装置及びその製造方法並びに電子装置
US8097490B1 (en) * 2010-08-27 2012-01-17 Stats Chippac, Ltd. Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die
JP5927756B2 (ja) * 2010-12-17 2016-06-01 ソニー株式会社 半導体装置及び半導体装置の製造方法
JP5664392B2 (ja) * 2011-03-23 2015-02-04 ソニー株式会社 半導体装置、半導体装置の製造方法、及び配線基板の製造方法
JP2012222161A (ja) * 2011-04-08 2012-11-12 Elpida Memory Inc 半導体装置
JP2013045945A (ja) * 2011-08-25 2013-03-04 Sumitomo Bakelite Co Ltd 半導体装置の製造方法
US20130069230A1 (en) * 2011-09-16 2013-03-21 Nagesh Vodrahalli Electronic assembly apparatus and associated methods
KR101906408B1 (ko) * 2011-10-04 2018-10-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9269646B2 (en) * 2011-11-14 2016-02-23 Micron Technology, Inc. Semiconductor die assemblies with enhanced thermal management and semiconductor devices including same
US8780600B2 (en) * 2011-12-07 2014-07-15 Apple Inc. Systems and methods for stacked semiconductor memory devices
JP2013197387A (ja) * 2012-03-21 2013-09-30 Elpida Memory Inc 半導体装置
JP5696076B2 (ja) * 2012-03-21 2015-04-08 株式会社東芝 半導体装置の検査装置及び半導体装置の検査方法
JP2013033999A (ja) * 2012-10-24 2013-02-14 Hitachi Ltd 半導体装置
JP2014187185A (ja) * 2013-03-22 2014-10-02 Renesas Electronics Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
JP2014187184A (ja) 2014-10-02
CN104064479B (zh) 2018-05-15
TW201445681A (zh) 2014-12-01
US20140284780A1 (en) 2014-09-25
KR20140117285A (ko) 2014-10-07
US20150325528A1 (en) 2015-11-12
TWI596714B (zh) 2017-08-21
CN104064479A (zh) 2014-09-24
US9117826B2 (en) 2015-08-25
HK1198562A1 (en) 2015-05-15

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