TWI596714B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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Publication number
TWI596714B
TWI596714B TW103107287A TW103107287A TWI596714B TW I596714 B TWI596714 B TW I596714B TW 103107287 A TW103107287 A TW 103107287A TW 103107287 A TW103107287 A TW 103107287A TW I596714 B TWI596714 B TW I596714B
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TW
Taiwan
Prior art keywords
semiconductor wafer
wafer
alignment mark
semiconductor
logic
Prior art date
Application number
TW103107287A
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English (en)
Chinese (zh)
Other versions
TW201445681A (zh
Inventor
木下順弘
Original Assignee
瑞薩電子股份有限公司
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Application filed by 瑞薩電子股份有限公司 filed Critical 瑞薩電子股份有限公司
Publication of TW201445681A publication Critical patent/TW201445681A/zh
Application granted granted Critical
Publication of TWI596714B publication Critical patent/TWI596714B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/101—Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/823—Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW103107287A 2013-03-22 2014-03-04 半導體裝置之製造方法 TWI596714B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013061087A JP6207190B2 (ja) 2013-03-22 2013-03-22 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW201445681A TW201445681A (zh) 2014-12-01
TWI596714B true TWI596714B (zh) 2017-08-21

Family

ID=51552137

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103107287A TWI596714B (zh) 2013-03-22 2014-03-04 半導體裝置之製造方法

Country Status (5)

Country Link
US (2) US9117826B2 (https=)
JP (1) JP6207190B2 (https=)
KR (1) KR20140117285A (https=)
CN (1) CN104064479B (https=)
TW (1) TWI596714B (https=)

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KR102149150B1 (ko) * 2013-10-21 2020-08-28 삼성전자주식회사 전자 장치
JP6363854B2 (ja) * 2014-03-11 2018-07-25 キヤノン株式会社 形成方法、および物品の製造方法
TWI566305B (zh) * 2014-10-29 2017-01-11 巨擘科技股份有限公司 製造三維積體電路的方法
KR102012788B1 (ko) 2015-09-23 2019-08-21 주식회사 엘지화학 접착 필름, 반도체 장치의 제조 방법 및 반도체 장치
US9953963B2 (en) * 2015-11-06 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit process having alignment marks for underfill
KR102022267B1 (ko) * 2017-12-28 2019-09-18 삼성전자주식회사 팬-아웃 반도체 패키지
KR102164793B1 (ko) * 2018-08-16 2020-10-14 삼성전자주식회사 수동부품 내장기판
US10998247B2 (en) 2018-08-16 2021-05-04 Samsung Electronics Co., Ltd. Board with embedded passive component
DE102018133319A1 (de) * 2018-12-21 2020-06-25 Rittal Gmbh & Co. Kg Verfahren zur robotergestützten Verdrahtung von elektrischen Komponenten einer auf einer Montageplatte angeordneten elektrischen Schaltanlage
JP7120521B2 (ja) * 2018-12-25 2022-08-17 住友電工デバイス・イノベーション株式会社 電子部品の製造方法及び半導体装置の製造方法
US11430909B2 (en) 2019-07-31 2022-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. BSI chip with backside alignment mark
KR102728190B1 (ko) * 2019-09-10 2024-11-08 삼성전자주식회사 Pop 형태의 반도체 패키지
KR102739235B1 (ko) * 2019-09-24 2024-12-05 삼성전자주식회사 반도체 패키지
KR102766659B1 (ko) * 2020-05-20 2025-02-12 에스케이하이닉스 주식회사 코어 다이가 제어 다이에 스택된 스택 패키지
CN113889420B (zh) * 2020-07-03 2025-05-02 联华电子股份有限公司 半导体元件结构及接合二基板的方法
KR102914869B1 (ko) * 2020-12-16 2026-01-16 삼성전자 주식회사 자주형 ncf 시트 및 그를 포함하는 반도체 패키지
KR102822141B1 (ko) 2021-09-24 2025-06-18 삼성전자주식회사 정렬 검사용 광학 어셈블리, 이를 포함한 광학 장치, 다이 본딩 시스템 및 이를 이용한 다이 본딩 방법
KR20230083102A (ko) * 2021-12-02 2023-06-09 삼성전자주식회사 인쇄회로기판 및 이를 포함하는 반도체 패키지
TWI822230B (zh) * 2022-08-05 2023-11-11 友達光電股份有限公司 發光面板
CN118676109B (zh) * 2024-08-21 2024-11-19 芯爱科技(南京)有限公司 封装基板及其制法

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Also Published As

Publication number Publication date
JP2014187184A (ja) 2014-10-02
JP6207190B2 (ja) 2017-10-04
CN104064479B (zh) 2018-05-15
TW201445681A (zh) 2014-12-01
US20140284780A1 (en) 2014-09-25
KR20140117285A (ko) 2014-10-07
US20150325528A1 (en) 2015-11-12
CN104064479A (zh) 2014-09-24
US9117826B2 (en) 2015-08-25
HK1198562A1 (en) 2015-05-15

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