CN104064479B - 制造半导体装置的方法和半导体装置 - Google Patents

制造半导体装置的方法和半导体装置 Download PDF

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Publication number
CN104064479B
CN104064479B CN201410106344.0A CN201410106344A CN104064479B CN 104064479 B CN104064479 B CN 104064479B CN 201410106344 A CN201410106344 A CN 201410106344A CN 104064479 B CN104064479 B CN 104064479B
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semiconductor chip
chip
alignment mark
semiconductor
wiring substrate
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CN104064479A (zh
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木下順弘
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00Marks applied to devices, e.g. for alignment or identification
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/20Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/0198Manufacture or treatment batch processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00Marks applied to devices, e.g. for alignment or identification
    • H10W46/101Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00Marks applied to devices, e.g. for alignment or identification
    • H10W46/301Marks applied to devices, e.g. for alignment or identification for alignment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00Marks applied to devices, e.g. for alignment or identification
    • H10W46/601Marks applied to devices, e.g. for alignment or identification for use after dicing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65Shapes or dispositions of interconnections
    • H10W70/654Top-view layouts
    • H10W70/655Fan-out layouts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/823Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/20Configurations of stacked chips
    • H10W90/291Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/20Configurations of stacked chips
    • H10W90/297Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN201410106344.0A 2013-03-22 2014-03-21 制造半导体装置的方法和半导体装置 Active CN104064479B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013061087A JP6207190B2 (ja) 2013-03-22 2013-03-22 半導体装置の製造方法
JP2013-061087 2013-03-22

Publications (2)

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CN104064479A CN104064479A (zh) 2014-09-24
CN104064479B true CN104064479B (zh) 2018-05-15

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US (2) US9117826B2 (https=)
JP (1) JP6207190B2 (https=)
KR (1) KR20140117285A (https=)
CN (1) CN104064479B (https=)
TW (1) TWI596714B (https=)

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JP7120521B2 (ja) * 2018-12-25 2022-08-17 住友電工デバイス・イノベーション株式会社 電子部品の製造方法及び半導体装置の製造方法
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KR102739235B1 (ko) * 2019-09-24 2024-12-05 삼성전자주식회사 반도체 패키지
KR102766659B1 (ko) * 2020-05-20 2025-02-12 에스케이하이닉스 주식회사 코어 다이가 제어 다이에 스택된 스택 패키지
CN113889420B (zh) * 2020-07-03 2025-05-02 联华电子股份有限公司 半导体元件结构及接合二基板的方法
KR102914869B1 (ko) * 2020-12-16 2026-01-16 삼성전자 주식회사 자주형 ncf 시트 및 그를 포함하는 반도체 패키지
KR102822141B1 (ko) 2021-09-24 2025-06-18 삼성전자주식회사 정렬 검사용 광학 어셈블리, 이를 포함한 광학 장치, 다이 본딩 시스템 및 이를 이용한 다이 본딩 방법
KR20230083102A (ko) * 2021-12-02 2023-06-09 삼성전자주식회사 인쇄회로기판 및 이를 포함하는 반도체 패키지
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CN118676109B (zh) * 2024-08-21 2024-11-19 芯爱科技(南京)有限公司 封装基板及其制法

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Also Published As

Publication number Publication date
JP2014187184A (ja) 2014-10-02
JP6207190B2 (ja) 2017-10-04
TW201445681A (zh) 2014-12-01
US20140284780A1 (en) 2014-09-25
KR20140117285A (ko) 2014-10-07
US20150325528A1 (en) 2015-11-12
TWI596714B (zh) 2017-08-21
CN104064479A (zh) 2014-09-24
US9117826B2 (en) 2015-08-25
HK1198562A1 (en) 2015-05-15

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