KR20120005383A - 배선 기판 및 배선 기판 제조 방법 - Google Patents

배선 기판 및 배선 기판 제조 방법 Download PDF

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Publication number
KR20120005383A
KR20120005383A KR1020110065762A KR20110065762A KR20120005383A KR 20120005383 A KR20120005383 A KR 20120005383A KR 1020110065762 A KR1020110065762 A KR 1020110065762A KR 20110065762 A KR20110065762 A KR 20110065762A KR 20120005383 A KR20120005383 A KR 20120005383A
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KR
South Korea
Prior art keywords
layer
electrode pad
insulating layer
support
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020110065762A
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English (en)
Korean (ko)
Inventor
겐타로 가네코
고타로 고다니
가즈히로 고바야시
준이치 나카무라
Original Assignee
신꼬오덴기 고교 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 신꼬오덴기 고교 가부시키가이샤 filed Critical 신꼬오덴기 고교 가부시키가이샤
Publication of KR20120005383A publication Critical patent/KR20120005383A/ko
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
KR1020110065762A 2010-07-08 2011-07-04 배선 기판 및 배선 기판 제조 방법 Withdrawn KR20120005383A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010155785A JP5502624B2 (ja) 2010-07-08 2010-07-08 配線基板の製造方法及び配線基板
JPJP-P-2010-155785 2010-07-08

Publications (1)

Publication Number Publication Date
KR20120005383A true KR20120005383A (ko) 2012-01-16

Family

ID=45429376

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110065762A Withdrawn KR20120005383A (ko) 2010-07-08 2011-07-04 배선 기판 및 배선 기판 제조 방법

Country Status (5)

Country Link
US (1) US20120006591A1 (enExample)
JP (1) JP5502624B2 (enExample)
KR (1) KR20120005383A (enExample)
CN (1) CN102316680A (enExample)
TW (1) TWI521618B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220077041A1 (en) * 2020-09-09 2022-03-10 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same

Families Citing this family (24)

* Cited by examiner, † Cited by third party
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JP5142967B2 (ja) * 2008-12-10 2013-02-13 ルネサスエレクトロニクス株式会社 半導体装置
JP6166879B2 (ja) * 2011-09-06 2017-07-19 株式会社 大昌電子 片面プリント配線板およびその製造方法
US20130168132A1 (en) * 2011-12-29 2013-07-04 Sumsung Electro-Mechanics Co., Ltd. Printed circuit board and method of manufacturing the same
JP6110084B2 (ja) * 2012-07-06 2017-04-05 株式会社 大昌電子 プリント配線板およびその製造方法
US9548282B2 (en) * 2012-11-08 2017-01-17 Nantong Fujitsu Microelectronics Co., Ltd. Metal contact for semiconductor device
WO2014071813A1 (zh) 2012-11-08 2014-05-15 南通富士通微电子股份有限公司 半导体器件的封装件和封装方法
CN102915986B (zh) 2012-11-08 2015-04-01 南通富士通微电子股份有限公司 芯片封装结构
KR101411813B1 (ko) 2012-11-09 2014-06-27 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
KR101516083B1 (ko) * 2013-10-14 2015-04-29 삼성전기주식회사 인쇄회로기판 및 인쇄회로기판 제조 방법
US9412686B2 (en) * 2014-08-26 2016-08-09 United Microelectronics Corp. Interposer structure and manufacturing method thereof
JP2016076534A (ja) * 2014-10-03 2016-05-12 イビデン株式会社 金属ポスト付きプリント配線板およびその製造方法
KR101896226B1 (ko) * 2015-05-15 2018-10-18 스템코 주식회사 연성 회로 기판 및 그 제조 방법
KR102040605B1 (ko) 2015-07-15 2019-12-05 엘지이노텍 주식회사 인쇄회로기판 및 그의 제조 방법
KR102326505B1 (ko) 2015-08-19 2021-11-16 엘지이노텍 주식회사 인쇄회로기판 및 그의 제조 방법
KR101742433B1 (ko) * 2016-04-21 2017-05-31 엘지이노텍 주식회사 인쇄회로기판 및 그의 제조 방법
TWI576033B (zh) * 2016-05-06 2017-03-21 旭德科技股份有限公司 線路基板及其製作方法
JP6615701B2 (ja) * 2016-06-24 2019-12-04 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
KR102119807B1 (ko) * 2018-02-13 2020-06-05 엘지이노텍 주식회사 인쇄회로기판 및 그의 제조 방법
WO2020158808A1 (ja) * 2019-01-30 2020-08-06 京セラ株式会社 電子部品実装用基体および電子装置
JP2021093417A (ja) * 2019-12-09 2021-06-17 イビデン株式会社 プリント配線板、及び、プリント配線板の製造方法
KR20220109642A (ko) * 2021-01-29 2022-08-05 엘지이노텍 주식회사 회로기판 및 이를 포함하는 패키지 기판
JP7711870B2 (ja) * 2021-10-19 2025-07-23 新光電気工業株式会社 配線基板及びその製造方法
JP7743265B2 (ja) * 2021-10-26 2025-09-24 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP2023125724A (ja) 2022-02-28 2023-09-07 新光電気工業株式会社 配線基板及びその製造方法

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JP2000165024A (ja) * 1998-11-25 2000-06-16 Kyocera Corp 配線基板および電子部品ならびにそれらの接続方法
US6586843B2 (en) * 2001-11-08 2003-07-01 Intel Corporation Integrated circuit device with covalently bonded connection structure
JP3990962B2 (ja) * 2002-09-17 2007-10-17 新光電気工業株式会社 配線基板の製造方法
JP4146864B2 (ja) * 2005-05-31 2008-09-10 新光電気工業株式会社 配線基板及びその製造方法、並びに半導体装置及び半導体装置の製造方法
TWI331494B (en) * 2007-03-07 2010-10-01 Unimicron Technology Corp Circuit board structure
JP5101169B2 (ja) * 2007-05-30 2012-12-19 新光電気工業株式会社 配線基板とその製造方法
JP4213191B1 (ja) * 2007-09-06 2009-01-21 新光電気工業株式会社 配線基板の製造方法
JP4783812B2 (ja) * 2008-05-12 2011-09-28 新光電気工業株式会社 配線基板の製造方法
JP5142967B2 (ja) * 2008-12-10 2013-02-13 ルネサスエレクトロニクス株式会社 半導体装置
KR101070022B1 (ko) * 2009-09-16 2011-10-04 삼성전기주식회사 다층 세라믹 회로 기판, 다층 세라믹 회로 기판 제조방법 및 이를 이용한 전자 디바이스 모듈

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220077041A1 (en) * 2020-09-09 2022-03-10 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same
KR20220033177A (ko) * 2020-09-09 2022-03-16 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US12300589B2 (en) * 2020-09-09 2025-05-13 Samsung Electronics Co., Ltd. Semiconductor package

Also Published As

Publication number Publication date
TW201209945A (en) 2012-03-01
US20120006591A1 (en) 2012-01-12
JP2012019080A (ja) 2012-01-26
TWI521618B (zh) 2016-02-11
JP5502624B2 (ja) 2014-05-28
CN102316680A (zh) 2012-01-11

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