KR102332346B1 - 3차원 반도체 메모리 장치 및 그의 제조 방법 - Google Patents

3차원 반도체 메모리 장치 및 그의 제조 방법 Download PDF

Info

Publication number
KR102332346B1
KR102332346B1 KR1020170046229A KR20170046229A KR102332346B1 KR 102332346 B1 KR102332346 B1 KR 102332346B1 KR 1020170046229 A KR1020170046229 A KR 1020170046229A KR 20170046229 A KR20170046229 A KR 20170046229A KR 102332346 B1 KR102332346 B1 KR 102332346B1
Authority
KR
South Korea
Prior art keywords
vertical
patterns
semiconductor pattern
semiconductor
horizontal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020170046229A
Other languages
English (en)
Korean (ko)
Other versions
KR20180114566A (ko
Inventor
이소현
심선일
이재덕
장재훈
한지훈
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020170046229A priority Critical patent/KR102332346B1/ko
Priority to US15/696,276 priority patent/US10396088B2/en
Priority to JP2018074160A priority patent/JP7207859B2/ja
Priority to CN201810311074.5A priority patent/CN108695339B/zh
Publication of KR20180114566A publication Critical patent/KR20180114566A/ko
Application granted granted Critical
Publication of KR102332346B1 publication Critical patent/KR102332346B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H01L27/11582—
    • H01L21/823425—
    • H01L27/11568—
    • H01L29/66833—
    • H01L29/7926—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/693—Vertical IGFETs having charge trapping gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H10D84/0133—Manufacturing common source or drain regions between multiple IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)
KR1020170046229A 2017-04-10 2017-04-10 3차원 반도체 메모리 장치 및 그의 제조 방법 Active KR102332346B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020170046229A KR102332346B1 (ko) 2017-04-10 2017-04-10 3차원 반도체 메모리 장치 및 그의 제조 방법
US15/696,276 US10396088B2 (en) 2017-04-10 2017-09-06 Three-dimensional semiconductor device
JP2018074160A JP7207859B2 (ja) 2017-04-10 2018-04-06 ３次元半導体メモリ装置及びその製造方法
CN201810311074.5A CN108695339B (zh) 2017-04-10 2018-04-09 三维半导体装置及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020170046229A KR102332346B1 (ko) 2017-04-10 2017-04-10 3차원 반도체 메모리 장치 및 그의 제조 방법

Publications (2)

Publication Number Publication Date
KR20180114566A KR20180114566A (ko) 2018-10-19
KR102332346B1 true KR102332346B1 (ko) 2021-12-01

Family

ID=63711243

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020170046229A Active KR102332346B1 (ko) 2017-04-10 2017-04-10 3차원 반도체 메모리 장치 및 그의 제조 방법

Country Status (4)

Country Link
US (1) US10396088B2 (https=)
JP (1) JP7207859B2 (https=)
KR (1) KR102332346B1 (https=)
CN (1) CN108695339B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210095390A (ko) * 2020-01-23 2021-08-02 삼성전자주식회사 폴리 실리콘과 메탈을 포함하는 워드 라인을 갖는 3차원 메모리 소자 및 이의 제조 방법

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020017572A (ja) * 2018-07-23 2020-01-30 キオクシア株式会社 半導体メモリ及び半導体メモリの製造方法
WO2020177049A1 (en) 2019-03-04 2020-09-10 Yangtze Memory Technologies Co., Ltd. Methods for forming three-dimensional memory devices
WO2020177048A1 (en) 2019-03-04 2020-09-10 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices
KR102778239B1 (ko) * 2019-04-25 2025-03-10 삼성전자주식회사 수직형 반도체 소자
EP4521880A3 (en) * 2019-06-27 2025-05-14 Yangtze Memory Technologies Co., Ltd. Novel 3d nand memory device and method of forming the same
KR102728797B1 (ko) * 2019-07-31 2024-11-11 삼성전자주식회사 반도체 장치 및 이의 동작 방법
KR102801211B1 (ko) * 2019-10-29 2025-04-29 삼성전자주식회사 돌출한 비아 라이너 층을 갖는 관통 비아 구조를 포함하는 3차원 반도체 소자 및 그 형성 방법
KR102744273B1 (ko) * 2020-01-03 2024-12-19 에스케이하이닉스 주식회사 반도체 장치 및 반도체 장치의 제조 방법
CN111223872B (zh) * 2020-01-17 2023-04-07 长江存储科技有限责任公司 一种3d nand存储器及其制造方法
CN111771281B (zh) 2020-01-17 2021-07-20 长江存储科技有限责任公司 三维存储器件及其制作方法
TWI743836B (zh) * 2020-04-30 2021-10-21 大陸商長江存儲科技有限責任公司 立體記憶體元件及其製作方法
KR102752667B1 (ko) 2020-05-07 2025-01-10 에스케이하이닉스 주식회사 반도체 장치 및 반도체 장치의 제조 방법
KR20210155266A (ko) * 2020-06-15 2021-12-22 에스케이하이닉스 주식회사 반도체 장치 및 반도체 장치의 제조 방법
CN111785730B (zh) * 2020-06-18 2021-06-08 长江存储科技有限责任公司 三维存储器及制备方法、电子设备
KR20230123355A (ko) * 2022-02-16 2023-08-23 삼성전자주식회사 웨이퍼 구조체 및 반도체 소자

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014057067A (ja) 2012-09-11 2014-03-27 Samsung Electronics Co Ltd ３次元半導体メモリ装置及びその製造方法
US20170084696A1 (en) 2015-09-18 2017-03-23 Changhyun LEE Three-dimensional semiconductor memory device

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010080685A (ja) 2008-09-26 2010-04-08 Toshiba Corp 不揮発性記憶装置及びその製造方法
JP5279560B2 (ja) 2009-03-11 2013-09-04 株式会社東芝 不揮発性半導体記憶装置
US8349681B2 (en) * 2010-06-30 2013-01-08 Sandisk Technologies Inc. Ultrahigh density monolithic, three dimensional vertical NAND memory device
KR101784695B1 (ko) * 2010-10-21 2017-10-13 삼성전자주식회사 수직형 메모리 장치 및 그 제조 방법
DE102011084603A1 (de) * 2010-10-25 2012-05-16 Samsung Electronics Co., Ltd. Dreidimensionales Halbleiterbauelement
KR20130066950A (ko) * 2011-12-13 2013-06-21 에스케이하이닉스 주식회사 3차원 불휘발성 메모리 소자와, 이를 포함하는 메모리 시스템과, 그 제조방법
US8847302B2 (en) * 2012-04-10 2014-09-30 Sandisk Technologies Inc. Vertical NAND device with low capacitance and silicided word lines
KR20140117212A (ko) * 2013-03-26 2014-10-07 에스케이하이닉스 주식회사 반도체 장치
JP2015028990A (ja) 2013-07-30 2015-02-12 株式会社東芝 不揮発性記憶装置
KR102139944B1 (ko) * 2013-11-26 2020-08-03 삼성전자주식회사 3차원 반도체 메모리 장치
JP2015149413A (ja) 2014-02-06 2015-08-20 株式会社東芝 半導体記憶装置及びその製造方法
KR102307487B1 (ko) * 2014-06-23 2021-10-05 삼성전자주식회사 3차원 반도체 메모리 장치 및 그 제조 방법
KR20160006866A (ko) 2014-07-09 2016-01-20 삼성전자주식회사 반도체 장치 및 그 제조방법
US9773803B2 (en) 2014-09-08 2017-09-26 Toshiba Memory Corporation Non-volatile memory device and method of manufacturing same
US9362298B2 (en) 2014-09-11 2016-06-07 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and manufacturing method thereof
KR102275543B1 (ko) * 2014-10-27 2021-07-13 삼성전자주식회사 3차원 반도체 메모리 장치
US20160260736A1 (en) 2015-03-03 2016-09-08 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20160268282A1 (en) 2015-03-13 2016-09-15 Kabushiki Kaisha Toshiba Semiconductor memory device and method for manufacturing same
KR102332359B1 (ko) * 2015-05-19 2021-11-29 삼성전자주식회사 수직형 메모리 장치
US9627399B2 (en) * 2015-07-24 2017-04-18 Sandisk Technologies Llc Three-dimensional memory device with metal and silicide control gates
KR102437779B1 (ko) * 2015-08-11 2022-08-30 삼성전자주식회사 3차원 반도체 메모리 장치
KR102437416B1 (ko) * 2015-08-28 2022-08-30 삼성전자주식회사 3차원 반도체 메모리 장치
KR20170027571A (ko) * 2015-09-02 2017-03-10 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법
KR102440221B1 (ko) * 2015-09-09 2022-09-05 삼성전자주식회사 반도체 소자 및 이의 제조 방법
KR102461150B1 (ko) * 2015-09-18 2022-11-01 삼성전자주식회사 3차원 반도체 메모리 장치
CN105355602B (zh) * 2015-10-19 2018-09-18 中国科学院微电子研究所 三维半导体器件及其制造方法
KR102565717B1 (ko) 2016-06-22 2023-08-14 삼성전자주식회사 메모리 장치

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014057067A (ja) 2012-09-11 2014-03-27 Samsung Electronics Co Ltd ３次元半導体メモリ装置及びその製造方法
US20170084696A1 (en) 2015-09-18 2017-03-23 Changhyun LEE Three-dimensional semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210095390A (ko) * 2020-01-23 2021-08-02 삼성전자주식회사 폴리 실리콘과 메탈을 포함하는 워드 라인을 갖는 3차원 메모리 소자 및 이의 제조 방법
KR102815720B1 (ko) 2020-01-23 2025-06-02 삼성전자주식회사 폴리 실리콘과 메탈을 포함하는 워드 라인을 갖는 3차원 메모리 소자 및 이의 제조 방법

Also Published As

Publication number Publication date
CN108695339A (zh) 2018-10-23
JP2018182320A (ja) 2018-11-15
US10396088B2 (en) 2019-08-27
JP7207859B2 (ja) 2023-01-18
KR20180114566A (ko) 2018-10-19
US20180294274A1 (en) 2018-10-11
CN108695339B (zh) 2023-09-05

Similar Documents

Publication Publication Date Title
KR102332346B1 (ko) 3차원 반도체 메모리 장치 및 그의 제조 방법
USRE50782E1 (en) Three-dimensional semiconductor memory devices including a first contact with a sidewall having a stepwise profile
US10964720B2 (en) Semiconductor memory device
US10886288B2 (en) Vertical semiconductor memory device structures including vertical channel structures and vertical dummy structures
CN107993996B (zh) 半导体器件及制造其的方法
KR102675911B1 (ko) 반도체 소자
US10546869B2 (en) Semiconductor device
KR102638740B1 (ko) 3차원 반도체 메모리 소자
US10777577B2 (en) 3-dimensional semiconductor memory device
KR102437273B1 (ko) 3차원 반도체 메모리 장치의 제조 방법
KR20190123050A (ko) 3차원 반도체 메모리 장치
KR20120078958A (ko) 3차원 반도체 장치의 제조 방법
KR20170130009A (ko) 3차원 반도체 장치
KR20200113124A (ko) 3차원 반도체 메모리 소자
KR102772394B1 (ko) 3차원 반도체 메모리 소자

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

D13-X000 Search requested

St.27 status event code: A-1-2-D10-D13-srh-X000

D14-X000 Search report completed

St.27 status event code: A-1-2-D10-D14-srh-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

U11 Full renewal or maintenance fee paid

Free format text: ST27 STATUS EVENT CODE: A-4-4-U10-U11-OTH-PR1001 (AS PROVIDED BY THE NATIONAL OFFICE)

Year of fee payment: 5