KR100970855B1 - 양면 전극 패키지 및 그 제조방법 - Google Patents
양면 전극 패키지 및 그 제조방법 Download PDFInfo
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- KR100970855B1 KR100970855B1 KR1020087011640A KR20087011640A KR100970855B1 KR 100970855 B1 KR100970855 B1 KR 100970855B1 KR 1020087011640 A KR1020087011640 A KR 1020087011640A KR 20087011640 A KR20087011640 A KR 20087011640A KR 100970855 B1 KR100970855 B1 KR 100970855B1
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- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229920005989 resin Polymers 0.000 claims abstract description 19
- 239000011347 resin Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000013467 fragmentation Methods 0.000 claims description 5
- 238000006062 fragmentation reaction Methods 0.000 claims description 5
- 238000007789 sealing Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 description 24
- 238000007650 screen-printing Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 239000010931 gold Substances 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000007641 inkjet printing Methods 0.000 description 2
- 230000005389 magnetism Effects 0.000 description 2
- 239000002923 metal particle Substances 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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Abstract
Description
Claims (4)
- LSI칩을 몰드수지에 의해 밀봉하는 동시에, 앞면측과 이면측의 양면에 외부 접속용 전극을 구비하는 양면 전극 패키지에 있어서,적어도 이면측에 아우터 리드부를 이면측 전극으로서 노출시킨 리드 프레임의 다이 패드상에 LSI칩을 접착하여, 상기 LSI칩과 리드 프레임의 복수의 이너 리드부의 사이에서 배선을 하고,상기 복수의 이너 리드부의 적어도 일부에는 또, 리드 프레임의 일부를 드로잉 가공(drawing)함으로써 앞면 전극을 일체로 형성하고, 그 앞면 전극의 두부면에 접속된 범프 전극을 다른 기판 또는 소자와 접속하기 위한 외부 접속용 전극으로서 구성하고,상기 범프 전극은 상기 몰드수지상에서 재배선함으로써 앞면 전극의 두부 노출위치와 다른 곳에 배치한 것을 특징으로 하는, 양면 전극 패키지.
- LSI칩을 몰드수지에 의해 밀봉하는 동시에, 앞면측과 이면측의 양면에 외부 접속용 전극을 구비하는 양면 전극 패키지에 있어서,적어도 이면측에 아우터 리드부를 이면측 전극으로서 노출시킨 리드 프레임의 다이 패드상에 LSI칩을 접착하여, 상기 LSI칩과 리드 프레임의 이너 리드부의 사이에서 배선을 하고,상기 이너 리드부에는 또, 스터드 범프를 접속하고, 그 스터드 범프 두부면에 접속된 범프 전극을 다른 기판 또는 소자와 접속하기 위한 앞면측 전극으로서 구성하고,상기 범프 전극은 상기 몰드수지상에서 재배선함으로써, 스터드 범프의 두부 노출위치와 다른 곳에 상기 범프전극을 배치한 것을 특징으로 하는, 양면 전극 패키지.
- LSI칩을 몰드수지에 의해 밀봉하는 동시에, 앞면측과 이면측의 양면에 외부 접속용 전극을 구비하는 양면 전극 패키지의 제조방법에 있어서,적어도 이면측에 아우터 리드부를 이면측 전극으로서 노출시킨 리드 프레임을 다수개 동시에 형성하고,상기 리드 프레임의 복수의 이너 리드부의 적어도 일부에는 리드 프레임의 일부를 드로잉 가공함으로써 앞면 전극을 일체로 형성하고,각각의 다이 패드상에 LSI칩을 접착하여, 상기 LSI칩과 리드 프레임의 복수의 이너부의 사이에서 배선을 하고,몰드수지에 의해 일괄 밀봉하고,앞면 전극의 두부면 또는 이것에 접속된 범프 전극을 몰드수지상에 노출시켜, 다른 기판 또는 소자와 접속하기 위한 외부 접속용 전극으로서 구성한 후, 개별 조각화를 위한 절단을 하는 것을 특징으로 하는, 양면 전극 패키지의 제조방법.
- LSI칩을 몰드수지에 의해 밀봉하는 동시에, 앞면측과 이면측의 양면에 외부 접속용 전극을 구비하는 양면 전극 패키지의 제조방법에 있어서,적어도 이면측에 아우터 리드부를 이면측 전극으로서 노출시킨 리드 프레임을 다수개 동시에 형성하고,각각의 다이 패드상에 LSI칩을 접착하여, 상기 LSI칩과 리드 프레임의 이너 리드부의 사이에서 배선을 하고,상기 이너 리드부에는 또, 스터드 범프를 접속하고,몰드수지에 의해 일괄 밀봉한 후, 개별 조각화를 위한 절단을 하고,스터드 범프 두부면에 접속된 범프 전극을 몰드수지상에 노출시켜, 다른 기판 또는 소자와 접속하기 위한 앞면측 전극으로서 구성한 것을 특징으로 하는, 양면 전극 패키지의 제조방법.
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Application Number | Priority Date | Filing Date | Title |
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JPJP-P-2005-00331156 | 2005-11-16 | ||
JP2005331156A JP3941877B2 (ja) | 2005-11-16 | 2005-11-16 | 両面電極パッケージ及びその製造方法 |
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KR20080058491A KR20080058491A (ko) | 2008-06-25 |
KR100970855B1 true KR100970855B1 (ko) | 2010-07-20 |
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US (2) | US8154110B2 (ko) |
JP (1) | JP3941877B2 (ko) |
KR (1) | KR100970855B1 (ko) |
CN (1) | CN101313402B (ko) |
WO (1) | WO2007058074A1 (ko) |
Cited By (1)
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US9585260B2 (en) | 2014-02-06 | 2017-02-28 | Samsung Electro-Mechanics Co., Ltd. | Electronic component module and manufacturing method thereof |
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JP5378643B2 (ja) * | 2006-09-29 | 2013-12-25 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びその製造方法 |
US20080217759A1 (en) * | 2007-03-06 | 2008-09-11 | Taiwan Solutions Systems Corp. | Chip package substrate and structure thereof |
JP5654109B2 (ja) * | 2007-09-18 | 2015-01-14 | オリンパス株式会社 | 積層実装構造体の製造方法 |
JP2009094118A (ja) | 2007-10-04 | 2009-04-30 | Panasonic Corp | リードフレーム、それを備える電子部品及びその製造方法 |
JP5149694B2 (ja) * | 2008-05-15 | 2013-02-20 | スパンション エルエルシー | 半導体装置及びその製造方法 |
JP5532570B2 (ja) * | 2008-09-29 | 2014-06-25 | 凸版印刷株式会社 | リードフレーム型基板とその製造方法ならびに半導体装置 |
EP2309535A1 (en) | 2009-10-09 | 2011-04-13 | Telefonaktiebolaget L M Ericsson (Publ) | Chip package with a chip embedded in a wiring body |
US8421210B2 (en) | 2010-05-24 | 2013-04-16 | Stats Chippac Ltd. | Integrated circuit packaging system with dual side connection and method of manufacture thereof |
US8482115B2 (en) | 2010-05-27 | 2013-07-09 | Stats Chippac Ltd. | Integrated circuit packaging system with dual side connection and method of manufacture thereof |
WO2013021647A1 (ja) * | 2011-08-10 | 2013-02-14 | 株式会社デンソー | 半導体モジュール、半導体モジュールを備えた半導体装置、および半導体モジュールの製造方法 |
JP5968827B2 (ja) * | 2013-04-25 | 2016-08-10 | アオイ電子株式会社 | 半導体パッケージおよびその製造方法 |
KR20150035251A (ko) | 2013-09-27 | 2015-04-06 | 삼성전기주식회사 | 외부접속단자부와 외부접속단자부를 갖는 반도체 패키지 및 그들의 제조방법 |
US9685351B2 (en) | 2014-07-18 | 2017-06-20 | Nxp Usa, Inc. | Wire bond mold lock method and structure |
CN104319270B (zh) * | 2014-10-31 | 2017-03-15 | 广东风华芯电科技股份有限公司 | 胎压感应器封装引线框架 |
KR101631558B1 (ko) * | 2014-12-05 | 2016-06-24 | 주식회사 에스에프에이반도체 | 라우터블 qfn 패키지 및 그 제조 방법 |
US20170287816A1 (en) * | 2016-04-01 | 2017-10-05 | Intel Corporation | Leadframe top-hat multi-chip solution |
JP6283131B1 (ja) * | 2017-01-31 | 2018-02-21 | 株式会社加藤電器製作所 | 電子デバイス及び電子デバイスの製造方法 |
CN108470725B (zh) * | 2018-05-02 | 2019-11-15 | 江苏感测通电子科技有限公司 | 一种高性能控制芯片封装结构 |
TWI736859B (zh) * | 2019-03-18 | 2021-08-21 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
CN110849482B (zh) * | 2019-11-20 | 2021-07-09 | 常熟市华通电子有限公司 | 一种具有引脚插件结构的传感器贴片封装工艺 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06252334A (ja) * | 1993-02-26 | 1994-09-09 | Hitachi Constr Mach Co Ltd | 半導体装置 |
JP2003174122A (ja) | 2001-12-04 | 2003-06-20 | Toshiba Corp | 半導体装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3461720B2 (ja) * | 1998-04-20 | 2003-10-27 | 松下電器産業株式会社 | 樹脂封止型半導体装置 |
JP2002026250A (ja) | 2000-07-12 | 2002-01-25 | Denso Corp | 積層回路モジュールの製造方法 |
JP2002158312A (ja) * | 2000-11-17 | 2002-05-31 | Oki Electric Ind Co Ltd | 3次元実装用半導体パッケージ、その製造方法、および半導体装置 |
US6707671B2 (en) * | 2001-05-31 | 2004-03-16 | Matsushita Electric Industrial Co., Ltd. | Power module and method of manufacturing the same |
JP4023159B2 (ja) * | 2001-07-31 | 2007-12-19 | ソニー株式会社 | 半導体装置の製造方法及び積層半導体装置の製造方法 |
TW523887B (en) * | 2001-11-15 | 2003-03-11 | Siliconware Precision Industries Co Ltd | Semiconductor packaged device and its manufacturing method |
JP2003249604A (ja) | 2002-02-25 | 2003-09-05 | Kato Denki Seisakusho:Kk | 樹脂封止半導体装置およびその製造方法、樹脂封止半導体装置に使用されるリードフレーム、ならびに半導体モジュール装置 |
JP3685185B2 (ja) | 2003-06-27 | 2005-08-17 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
-
2005
- 2005-11-16 JP JP2005331156A patent/JP3941877B2/ja active Active
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06252334A (ja) * | 1993-02-26 | 1994-09-09 | Hitachi Constr Mach Co Ltd | 半導体装置 |
JP2003174122A (ja) | 2001-12-04 | 2003-06-20 | Toshiba Corp | 半導体装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9585260B2 (en) | 2014-02-06 | 2017-02-28 | Samsung Electro-Mechanics Co., Ltd. | Electronic component module and manufacturing method thereof |
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CN101313402A (zh) | 2008-11-26 |
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US20090224381A1 (en) | 2009-09-10 |
US20120164790A1 (en) | 2012-06-28 |
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