KR100328536B1 - 향상된 층간 콘택을 가지는 반도체 디바이스 - Google Patents

향상된 층간 콘택을 가지는 반도체 디바이스 Download PDF

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Publication number
KR100328536B1
KR100328536B1 KR1019990005989A KR19990005989A KR100328536B1 KR 100328536 B1 KR100328536 B1 KR 100328536B1 KR 1019990005989 A KR1019990005989 A KR 1019990005989A KR 19990005989 A KR19990005989 A KR 19990005989A KR 100328536 B1 KR100328536 B1 KR 100328536B1
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KR
South Korea
Prior art keywords
insulating
film
contact hole
oxide film
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1019990005989A
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English (en)
Korean (ko)
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KR20000005599A (ko
Inventor
오까다마사까즈
히가시따니게이이찌
가와시마히로시
Original Assignee
다니구찌 이찌로오, 기타오카 다카시
미쓰비시덴키 가부시키가이샤
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Publication date
Application filed by 다니구찌 이찌로오, 기타오카 다카시, 미쓰비시덴키 가부시키가이샤 filed Critical 다니구찌 이찌로오, 기타오카 다카시
Publication of KR20000005599A publication Critical patent/KR20000005599A/ko
Application granted granted Critical
Publication of KR100328536B1 publication Critical patent/KR100328536B1/ko
Assigned to 르네사스 일렉트로닉스 가부시키가이샤 reassignment 르네사스 일렉트로닉스 가부시키가이샤 권리의 전부이전등록 Assignors: 미쓰비시덴키 가부시키가이샤
Assigned to 테세라 어드밴스드 테크놀로지스, 인크. reassignment 테세라 어드밴스드 테크놀로지스, 인크. 권리의 전부이전등록 Assignors: 르네사스 일렉트로닉스 가부시키가이샤
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
KR1019990005989A 1998-06-23 1999-02-23 향상된 층간 콘택을 가지는 반도체 디바이스 Expired - Lifetime KR100328536B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1998-176166 1998-06-23
JP10176166A JP2000012687A (ja) 1998-06-23 1998-06-23 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
KR20000005599A KR20000005599A (ko) 2000-01-25
KR100328536B1 true KR100328536B1 (ko) 2002-03-25

Family

ID=16008827

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990005989A Expired - Lifetime KR100328536B1 (ko) 1998-06-23 1999-02-23 향상된 층간 콘택을 가지는 반도체 디바이스

Country Status (4)

Country Link
US (1) US6531737B2 (https=)
JP (1) JP2000012687A (https=)
KR (1) KR100328536B1 (https=)
DE (1) DE19907070C2 (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6335249B1 (en) * 2000-02-07 2002-01-01 Taiwan Semiconductor Manufacturing Company Salicide field effect transistors with improved borderless contact structures and a method of fabrication
KR20020002007A (ko) * 2000-06-29 2002-01-09 박종섭 반도체 소자의 콘택홀 형성방법
JP4514006B2 (ja) * 2000-10-25 2010-07-28 ソニー株式会社 半導体装置
JP4733869B2 (ja) * 2001-07-25 2011-07-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7049667B2 (en) 2002-09-27 2006-05-23 Hrl Laboratories, Llc Conductive channel pseudo block process and circuit to inhibit reverse engineering
US6979606B2 (en) * 2002-11-22 2005-12-27 Hrl Laboratories, Llc Use of silicon block process step to camouflage a false transistor
WO2004055868A2 (en) * 2002-12-13 2004-07-01 Hrl Laboratories, Llc Integrated circuit modification using well implants
JP4343074B2 (ja) * 2004-03-19 2009-10-14 株式会社リコー 容器収納装置、該容器収納装置を備えた搬送装置及び画像形成装置
US7242063B1 (en) 2004-06-29 2007-07-10 Hrl Laboratories, Llc Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
KR100683852B1 (ko) * 2004-07-02 2007-02-15 삼성전자주식회사 반도체 소자의 마스크롬 소자 및 그 형성 방법
US8168487B2 (en) 2006-09-28 2012-05-01 Hrl Laboratories, Llc Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer
US8664050B2 (en) * 2012-03-20 2014-03-04 International Business Machines Corporation Structure and method to improve ETSOI MOSFETS with back gate
CN103594417A (zh) * 2012-08-13 2014-02-19 中芯国际集成电路制造(上海)有限公司 互连结构的制作方法
US9029940B2 (en) 2013-01-18 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical tunneling field-effect transistor cell
US9159826B2 (en) 2013-01-18 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical tunneling field-effect transistor cell and fabricating the same
US10534045B2 (en) * 2017-09-20 2020-01-14 Texas Instruments Incorporated Vertical hall-effect sensor for detecting two-dimensional in-plane magnetic fields

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08227938A (ja) * 1995-02-21 1996-09-03 Nec Corp 半導体装置及びその製造方法

Family Cites Families (16)

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Publication number Priority date Publication date Assignee Title
US4566914A (en) 1983-05-13 1986-01-28 Micro Power Systems, Inc. Method of forming localized epitaxy and devices formed therein
SE8603126L (sv) 1985-08-05 1987-02-06 Rca Corp Cmos-integrerad krets och metod att tillverka en sadan
JPS62190847A (ja) 1986-02-18 1987-08-21 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
DE4337355C2 (de) 1993-11-02 1997-08-21 Siemens Ag Verfahren zur Herstellung eines Kontaktlochs zu einem dotierten Bereich
US5492858A (en) * 1994-04-20 1996-02-20 Digital Equipment Corporation Shallow trench isolation process for high aspect ratio trenches
KR0126640B1 (ko) 1994-05-07 1998-04-02 김주용 반도체소자 및 그 제조방법
WO1996024160A2 (en) 1995-01-30 1996-08-08 Philips Electronics N.V. Method of manufacturing a semiconductor device with a semiconductor body with field insulation regions provided with recessed connection conductors
US5652176A (en) * 1995-02-24 1997-07-29 Motorola, Inc. Method for providing trench isolation and borderless contact
JPH08277938A (ja) 1995-04-06 1996-10-22 Daihatsu Motor Co Ltd オイルフィラーキャップのシール構造
US5976769A (en) * 1995-07-14 1999-11-02 Texas Instruments Incorporated Intermediate layer lithography
DE19629736C2 (de) 1996-01-26 2000-12-14 Mitsubishi Electric Corp Halbleitereinrichtung mit selbstjustierendem Kontakt und Herstellungsverfahren dafür
US5703391A (en) 1996-06-27 1997-12-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having element isolating insulating film in contact hole
JP2924814B2 (ja) * 1996-09-26 1999-07-26 日本電気株式会社 半導体装置の製造方法
JPH10106973A (ja) 1996-09-27 1998-04-24 Nec Corp 半導体装置およびその製造方法
US6018180A (en) * 1997-12-23 2000-01-25 Advanced Micro Devices, Inc. Transistor formation with LI overetch immunity
US6018184A (en) * 1998-01-22 2000-01-25 Micron Technology, Inc. Semiconductor structure useful in a self-aligned contact having multiple insulation layers of non-uniform thickness

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08227938A (ja) * 1995-02-21 1996-09-03 Nec Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
JP2000012687A (ja) 2000-01-14
US20010042892A1 (en) 2001-11-22
US6531737B2 (en) 2003-03-11
DE19907070C2 (de) 2003-08-21
DE19907070A1 (de) 2000-01-13
KR20000005599A (ko) 2000-01-25

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