WO1996024160A2 - Method of manufacturing a semiconductor device with a semiconductor body with field insulation regions provided with recessed connection conductors - Google Patents
Method of manufacturing a semiconductor device with a semiconductor body with field insulation regions provided with recessed connection conductors Download PDFInfo
- Publication number
- WO1996024160A2 WO1996024160A2 PCT/IB1996/000037 IB9600037W WO9624160A2 WO 1996024160 A2 WO1996024160 A2 WO 1996024160A2 IB 9600037 W IB9600037 W IB 9600037W WO 9624160 A2 WO9624160 A2 WO 9624160A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- field insulation
- region
- insulation region
- semiconductor
- active
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
Definitions
- the invention relates to a method of manufacturing a semiconductor device with a semiconductor body provided with a field insulation region which adjoins a surface of the semiconductor body and which encloses an active monocrystalline semiconductor region, the field insulation region being provided with a strip of conductive material which adjoins the surface, which is recessed in the field insulation region, and which makes contact with the active region.
- connection conductors capable of being contacted via the strip of conductive material recessed in the field insulation region can be formed in the active semiconductor region.
- parasitic capacitances between said connection conductors and the semiconductor body are very small in that case because they are separated from semiconductor material by a comparatively thick layer of insulating material.
- US 4,566,914 discloses a method of the kind mentioned in the opening paragraph whereby a layer of insulating material is provided on a semiconductor slice, in which material a window and a groove adjoining the window are provided. Semiconductor material is subsequently deposited in monocrystalline form within the window and in non- monocrystalline form outside the window. Then a polishing treatment is carried out until the layer of insulating material has been exposed again. A semiconductor body with a plane surface is formed in this way. The active region, the field insulation region enclosing the active region, and the strip of conductive material recessed in the field insulation region and contacting the active region adjoin this surface.
- the active region is formed by the monocrystalline semiconductor material, the field insulation region by the layer of insulating material, and the strip of conductive material by the non-crystalline semiconductor material present in the groove.
- a deposition process is used whereby monocrystalline material is grown on monocrystalline material and non- monocrystalline material is grown on non-monocrystalline material. During the deposition it is not only monocrystalline material which grows within the window.
- the window has an edge of non-monocrystalline insulating material which is directed transverse to the semiconductor wafer. Monocrystalline material is grown on the monocrystalline semiconductor wafer within the window, but non-monocrystalline material on the edge of the window.
- the useful monocrystalline active region accordingly becomes smaller than the window and the contacts to semiconductor zones formed in the active region pass through non-crystalline material deposited within the window.
- the invention has for its object inter alia to counteract said disadvantage.
- the method is for this purpose characterized in that first the field insulation region is provided in the semiconductor body so as to adjoin the surface thereof, after which a groove adjoining the active region is formed in the field insulation region, in which groove subsequently the strip of conductive material which lies recessed in the field insulation region is provided.
- this field insulation region directly adjoins die monocrystalline active region.
- the active region may thus be made so small in this method that the desired semiconductor zones can just be provided therein. The advantages of a small active region wid connection conductors recessed in the field insulation region as described above are then fully utilized.
- the field insulation region may be provided in the semiconductor body in various manners, for example, through local oxidation of this body.
- the insulation region is provided in the semiconductor body in that a depression is formed therein at the region of the field insulation region, in that subsequently a layer of insulating material is deposited which fills the depression and covers the active region, and in that finally the semiconductor body is subjected to a chemical mechanical polishing treatment until the active region has been exposed again.
- a field insulation region is formed here which exhibits a sharp boundary with the active region transverse to the surface.
- the conductive strip is accordingly insulated from the subjacent semiconductor material over the entire surface of this strip by a comparatively thick layer of insulating material of the field insulation region. This is not the case when the field insulation region is formed through local oxidation.
- a field insulation region formed in this latter manner has a thickness near the active region which gradually decreases, seen in a direction towards the active region.
- the conductive strip is provided in the groove formed in the field insulation region through deposition of a layer of conductive material after the formation of the groove, filling the groove and covering the active region and the field insulation region, after which the semiconductor body is subjected to a chemical mechanical polishing treatment until the active region and the field insulation region have been exposed again.
- the strip then exhibits a sharp boundary with the active region transverse to the surface again.
- the active region is not made smaller by this method of providing the strip.
- the field insulation region is formed from silicon oxide and the strip of conductive material from non-crystalline silicon in a silicon semiconductor body.
- the groove in the field insulation region may then be selectively etched relative to silicon and silicon oxide and may subsequently be simply filled with polycrystalline silicon.
- the removal of polycrystalline silicon by the chemical mechanical polishing treatment then stops automatically the moment the silicon oxide of the field insulation region is reached.
- Figs. 1 to 7 diagrammatically and in cross-section show a few stages in the manufacture of a semiconductor device by the method according to the invention.
- Figs. 1 to 7 diagrammatically and in cross-section show a few stages in the manufacture of a semiconductor device with a semiconductor body 1 provided with a field insulation region 2 which adjoins a surface 3 of the semiconductor body 1 and which encloses active monocrystalline semiconductor regions 4 and 5, the field insulation region 2 being provided with strips 6, 7, 8 of conductive material which adjoin the surface 3, which are recessed in the field insulation region 2, and which make contact with the active regions 4 and 5.
- the drawing two active regions 4 and 5 are shown, but in practice a semiconductor device may comprise only a single but also very many such regions.
- the method starts with a semiconductor body 1 , in this case a wafer of n- type doped monocrystalline silicon.
- the field insulation region 2 is first provided therein so as to adjoin the surface 3.
- a usual photoresist mask 9 is provided on the surface 3 at the areas of the active regions 4 and 5 to be formed.
- Depressions 10 are subsequently etched into the semiconductor body 1 by a reactive ion plasma etching process in usual manner. These depressions 10 have comparatively straight walls 11 which extend transverse to the surface 3.
- a layer of insulating material 12 is deposited in usual manner, filling the depressions 10 and covering the surface 3.
- the insulating material in this example is silicon oxide, but alternative insulating materials such as, for example, silicon nitride or silicon oxynitride are also possible.
- the depressions 10 may also be filled through deposition of layers of different compositions such as, for example, a layer of silicon oxide followed by a layer of silicon oxynitride.
- the semiconductor body 1 is subjected to a usual chemical mechanical polishing treatment whereby silicon oxide is removed. This polishing treatment is stopped the moment the surface 3 is reached.
- the field insulation region 2 has now been formed, enclosing the active regions 4 and 5.
- the structure 1, 2, 4, 5 thus obtained is bounded by the plane surface 3.
- grooves 13, 14, 15 adjoining the active regions 4 and 5 are formed in the field insulation region 2.
- a photoresist mask 16 is provided on the surface 3 after the formation of the field insulation region 2. This photoresist mask 16 leaves exposed not only portions 17 of the field insulation region 2, but also portions 18 of the active region 4 and 5.
- the grooves 13, 14, 15 are subsequently etched in a usual reactive ion plasma etching process whereby silicon oxide can be selectively removed relative to silicon.
- the grooves 13, 14, 15 directly adjoin the active regions 4 and 5.
- the strips 6, 7, 8 of conductive material are provided therein.
- a layer 19 of conductive material or of a material which can be rendered conductive subsequently through the introduction of dopants is deposited, in the present example non-doped polycrystalline silicon. This layer 19 fills the grooves 13, 14, 15 and covers the field insulation region 2 and the active regions 4 and 5.
- a chemical mechanical polishing treatment is carried out whereby material is removed from the layer 19, which treatment is stopped the moment the active regions 4 and 5 and the field insulation region 2 have become exposed.
- the structure 1, 2, 4, 5, 6, 7, 8 thus obtained is bounded by the plane surface 3.
- a structure is thus obtained with a semiconductor 1 provided with a field insulation region 2 which adjoins a surface 3 of the semiconductor body 1 and which encloses active monocrystalline semiconductor regions 4 and 5, the field insulation region 2 being provided with strips 6, 7, 8 of conductive material which adjoin the surface 3, which are recessed in the field insulation region 2, and which make contact with the active regions 4 and 5.
- Semiconductor elements may be formed in the active regions 4 and contacted through the strips 6, 7, 8 of conductive material recessed in the field insulation region 2. No space need be reserved for such contacts on the active regions then, so that the active regions can be very small.
- parasitic capacitances between the contacts and the semiconductor body 1 are very small then because said contacts are separated from the subjacent semiconductor material by comparatively thick field insulation material.
- the strips 6, 7, 8 exhibit sharp boundaries with the active regions 4 and 5 transverse to the surface. The active region is not made smaller when the strips 6, 7, 8 are provided in this manner.
- an MOS transistor 20 is formed in the one active region 4 and a bipolar transistor 21 in the other region 5.
- p-type doped semiconductor zones 22 and 23 are first formed in the active regions 4 and 5, and the surface 3 is provided with a thin layer of gate oxide 24 at the area of the active region 4.
- a conductor track 25 of n-type polycrystalline silicon is formed on the active region 4 so as to serve as a gate electrode for the MOS transistor 20, and a conductor track 26 of n-type polycrystalline silicon is formed on the active region 5 serving as a connection conductor for the emitter zone 27 of the bipolar transistor 21 and as a diffusion source from which this emitter zone 27 is formed.
- n-type source and drain zones 28 and 29 of the MOS transistor are formed by a usual ion implantation.
- the conductor tracks 25 and 26 are provided with side wall insulations 30 in usual manner. Finally, the strips 6 and 7 are provided with an n-type dopant and the strip 8 with a p-type dopant. The strips 6, 7, 8 and the conductor tracks 25 and 26 are finally also provided with a titanium suicide top layer in usual manner.
- a field insulation region 2 is formed by the method according to the invention which exhibits a sharp boundary transverse to the surface with the active regions 4 and 5, which boundary is formed by the wall 11 of the depression 10 etched into the semiconductor body 1.
- the conductive strips 6, 7, 8 are thus insulated from the subjacent semiconductor material over their entire surface areas by a comparatively thick layer of insulating material of the field insulation region 2. This is not the case, for example, when the field insulation region is provided through local oxidation; in that case the field insulation region has a thickness near the active region which gradually decreases, seen in the direction of the active region.
Abstract
A method of manufacturing a semiconductor device with a semiconductor body (1) provided with a field insulation region (2) which adjoins a surface (3) of the semiconductor body (1) and which encloses an active monocrystalline semiconductor region (4, 5). The field insulation region (2) is provided with a strip of conductive material (6, 7, 8) which adjoins the surface (3), which is recessed in the field insulation region (2), and which makes contact with the active region (4, 5). The field insulation region (2) is first provided in the semiconductor body (1), after which a groove (13, 14, 15) is formed adjoining the active region (4, 5) in the field insulation region (2), in which groove subsequently the strip (6, 7, 8) of conductive material is provided. Semiconductor elements (20, 21) may be formed in the active semiconductor region (4, 5) and connected via the strips (6, 7, 8) recessed in the field insulation region (2). The relevant connection conductors lie outside the active regions (4, 5), which may accordingly be small. In addition, parasitic capacitances between the connection conductors and the semiconductor body are small.
Description
Method of manufacturing a semiconductor device with a semiconductor body with field insulation regions provided with recessed connection conductors.
The invention relates to a method of manufacturing a semiconductor device with a semiconductor body provided with a field insulation region which adjoins a surface of the semiconductor body and which encloses an active monocrystalline semiconductor region, the field insulation region being provided with a strip of conductive material which adjoins the surface, which is recessed in the field insulation region, and which makes contact with the active region.
Semiconductor elements capable of being contacted via the strip of conductive material recessed in the field insulation region can be formed in the active semiconductor region. The source and drain of a MOS transistor or the base and emitter of a bipolar transistor, for example, may be contacted through such a recessed connection conductor. No space need be reserved for such connection conductors on the active region then, so that the active region can be made very small. In addition, parasitic capacitances between said connection conductors and the semiconductor body are very small in that case because they are separated from semiconductor material by a comparatively thick layer of insulating material.
US 4,566,914 discloses a method of the kind mentioned in the opening paragraph whereby a layer of insulating material is provided on a semiconductor slice, in which material a window and a groove adjoining the window are provided. Semiconductor material is subsequently deposited in monocrystalline form within the window and in non- monocrystalline form outside the window. Then a polishing treatment is carried out until the layer of insulating material has been exposed again. A semiconductor body with a plane surface is formed in this way. The active region, the field insulation region enclosing the active region, and the strip of conductive material recessed in the field insulation region and contacting the active region adjoin this surface. The active region is formed by the monocrystalline semiconductor material, the field insulation region by the layer of insulating material, and the strip of conductive material by the non-crystalline semiconductor material present in the groove.
To form the active region and the conductive strip, a deposition process is used whereby monocrystalline material is grown on monocrystalline material and non- monocrystalline material is grown on non-monocrystalline material. During the deposition it is not only monocrystalline material which grows within the window. The window has an edge of non-monocrystalline insulating material which is directed transverse to the semiconductor wafer. Monocrystalline material is grown on the monocrystalline semiconductor wafer within the window, but non-monocrystalline material on the edge of the window. The useful monocrystalline active region accordingly becomes smaller than the window and the contacts to semiconductor zones formed in the active region pass through non-crystalline material deposited within the window. This has the disadvantage that the advantages of a small active region with connection conductors recessed in the field insulation region as described above are at least partly cancelled out.
The invention has for its object inter alia to counteract said disadvantage.
According to the invention, the method is for this purpose characterized in that first the field insulation region is provided in the semiconductor body so as to adjoin the surface thereof, after which a groove adjoining the active region is formed in the field insulation region, in which groove subsequently the strip of conductive material which lies recessed in the field insulation region is provided.
Since in this method first the field insulation region adjoining the surface of the semiconductor body is provided in this body, this field insulation region directly adjoins die monocrystalline active region. The same holds for the groove provided in the field insulation region and for the conductive strip provided therein. The active region may thus be made so small in this method that the desired semiconductor zones can just be provided therein. The advantages of a small active region wid connection conductors recessed in the field insulation region as described above are then fully utilized.
The field insulation region may be provided in the semiconductor body in various manners, for example, through local oxidation of this body. Preferably, however, the insulation region is provided in the semiconductor body in that a depression is formed therein at the region of the field insulation region, in that subsequently a layer of insulating material is deposited which fills the depression and covers the active region, and in that finally the semiconductor body is subjected to a chemical mechanical polishing treatment until the active region has been exposed again. A field insulation region is formed here which exhibits a
sharp boundary with the active region transverse to the surface. The conductive strip is accordingly insulated from the subjacent semiconductor material over the entire surface of this strip by a comparatively thick layer of insulating material of the field insulation region. This is not the case when the field insulation region is formed through local oxidation. A field insulation region formed in this latter manner has a thickness near the active region which gradually decreases, seen in a direction towards the active region.
Preferably, the conductive strip is provided in the groove formed in the field insulation region through deposition of a layer of conductive material after the formation of the groove, filling the groove and covering the active region and the field insulation region, after which the semiconductor body is subjected to a chemical mechanical polishing treatment until the active region and the field insulation region have been exposed again. The strip then exhibits a sharp boundary with the active region transverse to the surface again. The active region is not made smaller by this method of providing the strip.
Preferably, the field insulation region is formed from silicon oxide and the strip of conductive material from non-crystalline silicon in a silicon semiconductor body. The groove in the field insulation region may then be selectively etched relative to silicon and silicon oxide and may subsequently be simply filled with polycrystalline silicon. The removal of polycrystalline silicon by the chemical mechanical polishing treatment then stops automatically the moment the silicon oxide of the field insulation region is reached.
The invention will be explained in more detail below by way of example with reference to a drawing in which:
Figs. 1 to 7 diagrammatically and in cross-section show a few stages in the manufacture of a semiconductor device by the method according to the invention.
Figs. 1 to 7 diagrammatically and in cross-section show a few stages in the manufacture of a semiconductor device with a semiconductor body 1 provided with a field insulation region 2 which adjoins a surface 3 of the semiconductor body 1 and which encloses active monocrystalline semiconductor regions 4 and 5, the field insulation region 2 being provided with strips 6, 7, 8 of conductive material which adjoin the surface 3, which are recessed in the field insulation region 2, and which make contact with the active regions 4 and 5. In the drawing, two active regions 4 and 5 are shown, but in practice a
semiconductor device may comprise only a single but also very many such regions.
The method starts with a semiconductor body 1 , in this case a wafer of n- type doped monocrystalline silicon. The field insulation region 2 is first provided therein so as to adjoin the surface 3. For this purpose, a usual photoresist mask 9 is provided on the surface 3 at the areas of the active regions 4 and 5 to be formed. Depressions 10 are subsequently etched into the semiconductor body 1 by a reactive ion plasma etching process in usual manner. These depressions 10 have comparatively straight walls 11 which extend transverse to the surface 3. After the depressions 10 have been provided, a layer of insulating material 12 is deposited in usual manner, filling the depressions 10 and covering the surface 3. The insulating material in this example is silicon oxide, but alternative insulating materials such as, for example, silicon nitride or silicon oxynitride are also possible. The depressions 10 may also be filled through deposition of layers of different compositions such as, for example, a layer of silicon oxide followed by a layer of silicon oxynitride. After the deposition of the layer of insulating material 12 the semiconductor body 1 is subjected to a usual chemical mechanical polishing treatment whereby silicon oxide is removed. This polishing treatment is stopped the moment the surface 3 is reached. The field insulation region 2 has now been formed, enclosing the active regions 4 and 5. The structure 1, 2, 4, 5 thus obtained is bounded by the plane surface 3. After the field insulation region 2 has been formed, grooves 13, 14, 15 adjoining the active regions 4 and 5 are formed in the field insulation region 2. For this purpose, a photoresist mask 16 is provided on the surface 3 after the formation of the field insulation region 2. This photoresist mask 16 leaves exposed not only portions 17 of the field insulation region 2, but also portions 18 of the active region 4 and 5. The grooves 13, 14, 15 are subsequently etched in a usual reactive ion plasma etching process whereby silicon oxide can be selectively removed relative to silicon. The grooves 13, 14, 15 directly adjoin the active regions 4 and 5.
After the grooves 13, 14, 15 have been etched, the strips 6, 7, 8 of conductive material are provided therein. For this purpose, a layer 19 of conductive material or of a material which can be rendered conductive subsequently through the introduction of dopants is deposited, in the present example non-doped polycrystalline silicon. This layer 19 fills the grooves 13, 14, 15 and covers the field insulation region 2 and the active regions 4 and 5. Then a chemical mechanical polishing treatment is carried out whereby material is removed from the layer 19, which treatment is stopped the moment the active regions 4 and
5 and the field insulation region 2 have become exposed. The structure 1, 2, 4, 5, 6, 7, 8 thus obtained is bounded by the plane surface 3.
A structure is thus obtained with a semiconductor 1 provided with a field insulation region 2 which adjoins a surface 3 of the semiconductor body 1 and which encloses active monocrystalline semiconductor regions 4 and 5, the field insulation region 2 being provided with strips 6, 7, 8 of conductive material which adjoin the surface 3, which are recessed in the field insulation region 2, and which make contact with the active regions 4 and 5. Semiconductor elements may be formed in the active regions 4 and contacted through the strips 6, 7, 8 of conductive material recessed in the field insulation region 2. No space need be reserved for such contacts on the active regions then, so that the active regions can be very small. In addition, parasitic capacitances between the contacts and the semiconductor body 1 are very small then because said contacts are separated from the subjacent semiconductor material by comparatively thick field insulation material. The strips 6, 7, 8 exhibit sharp boundaries with the active regions 4 and 5 transverse to the surface. The active region is not made smaller when the strips 6, 7, 8 are provided in this manner.
In this example, an MOS transistor 20 is formed in the one active region 4 and a bipolar transistor 21 in the other region 5. To achieve this, p-type doped semiconductor zones 22 and 23 are first formed in the active regions 4 and 5, and the surface 3 is provided with a thin layer of gate oxide 24 at the area of the active region 4. Then a conductor track 25 of n-type polycrystalline silicon is formed on the active region 4 so as to serve as a gate electrode for the MOS transistor 20, and a conductor track 26 of n-type polycrystalline silicon is formed on the active region 5 serving as a connection conductor for the emitter zone 27 of the bipolar transistor 21 and as a diffusion source from which this emitter zone 27 is formed. Then n-type source and drain zones 28 and 29 of the MOS transistor are formed by a usual ion implantation.
After the semiconductor zones 27, 28, 29 have been formed, the conductor tracks 25 and 26 are provided with side wall insulations 30 in usual manner. Finally, the strips 6 and 7 are provided with an n-type dopant and the strip 8 with a p-type dopant. The strips 6, 7, 8 and the conductor tracks 25 and 26 are finally also provided with a titanium suicide top layer in usual manner.
A field insulation region 2 is formed by the method according to the invention which exhibits a sharp boundary transverse to the surface with the active regions 4 and 5, which boundary is formed by the wall 11 of the depression 10 etched into the semiconductor body 1. The conductive strips 6, 7, 8 are thus insulated from the subjacent
semiconductor material over their entire surface areas by a comparatively thick layer of insulating material of the field insulation region 2. This is not the case, for example, when the field insulation region is provided through local oxidation; in that case the field insulation region has a thickness near the active region which gradually decreases, seen in the direction of the active region.
Claims
1. A method of manufacturing a semiconductor device with a semiconductor body provided with a field insulation region which adjoins a surface of the semiconductor body and which encloses an active monocrystalline semiconductor region, the field insulation region being provided with a strip of conductive material which adjoins the surface, which is recessed in the field insulation region, and which makes contact with the active region, characterized in that first the field insulation region is provided in the semiconductor body so as to adjoin the surface thereof, after which a groove adjoining the active region is formed in the field insulation region, in which groove subsequently the strip of conductive material which lies recessed in the field insulation region is provided.
2. A method as claimed in Claim 1, characterized in that the insulation region is provided in the semiconductor body in tiiat a depression is formed therein at the region of the field insulation region, in that subsequently a layer of insulating material is deposited which fills the depression and covers the active region, and in that finally the seriiiconductor body is subjected to a chemical mechanical polishing treatment until the active region has been exposed again.
3. A method as claimed in Claim 1 or 2, characterized in that the conductive strip is provided in the groove formed in the field insulation region through deposition of a layer of conductive material after the formation of the groove, filling the groove and covering the active region and the field insulation region, after which the semiconductor body is subjected to a chemical mechanical polishing treatment until the active region and the field insulation region have been exposed again.
4. A method as claimed in Claim 1 , 2 or 3, characterized in that the field insulation region is formed from silicon oxide and the strip of conductive material from non- crystalline silicon in a silicon semiconductor body.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP95200214 | 1995-01-30 | ||
| EP95200214.5 | 1995-01-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO1996024160A2 true WO1996024160A2 (en) | 1996-08-08 |
| WO1996024160A3 WO1996024160A3 (en) | 1996-10-17 |
Family
ID=8219976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/IB1996/000037 WO1996024160A2 (en) | 1995-01-30 | 1996-01-17 | Method of manufacturing a semiconductor device with a semiconductor body with field insulation regions provided with recessed connection conductors |
Country Status (1)
| Country | Link |
|---|---|
| WO (1) | WO1996024160A2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6531737B2 (en) | 1998-06-23 | 2003-03-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having an improved interlayer contact and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4160991A (en) * | 1977-10-25 | 1979-07-10 | International Business Machines Corporation | High performance bipolar device and method for making same |
| US4309812A (en) * | 1980-03-03 | 1982-01-12 | International Business Machines Corporation | Process for fabricating improved bipolar transistor utilizing selective etching |
| US4319932A (en) * | 1980-03-24 | 1982-03-16 | International Business Machines Corporation | Method of making high performance bipolar transistor with polysilicon base contacts |
| US4378630A (en) * | 1980-05-05 | 1983-04-05 | International Business Machines Corporation | Process for fabricating a high performance PNP and NPN structure |
| US4566914A (en) * | 1983-05-13 | 1986-01-28 | Micro Power Systems, Inc. | Method of forming localized epitaxy and devices formed therein |
-
1996
- 1996-01-17 WO PCT/IB1996/000037 patent/WO1996024160A2/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4160991A (en) * | 1977-10-25 | 1979-07-10 | International Business Machines Corporation | High performance bipolar device and method for making same |
| US4309812A (en) * | 1980-03-03 | 1982-01-12 | International Business Machines Corporation | Process for fabricating improved bipolar transistor utilizing selective etching |
| US4319932A (en) * | 1980-03-24 | 1982-03-16 | International Business Machines Corporation | Method of making high performance bipolar transistor with polysilicon base contacts |
| US4378630A (en) * | 1980-05-05 | 1983-04-05 | International Business Machines Corporation | Process for fabricating a high performance PNP and NPN structure |
| US4566914A (en) * | 1983-05-13 | 1986-01-28 | Micro Power Systems, Inc. | Method of forming localized epitaxy and devices formed therein |
Non-Patent Citations (1)
| Title |
|---|
| IBM TECHNICAL DISCLOSURE BULLETIN, Volume 21, No. 12, May 1979, I. ANTIPOV, "Method for Forming Shallow Junction Semiconductor Devices", pages 4868-4870. * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6531737B2 (en) | 1998-06-23 | 2003-03-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having an improved interlayer contact and manufacturing method thereof |
| DE19907070C2 (en) * | 1998-06-23 | 2003-08-21 | Mitsubishi Electric Corp | Semiconductor contact and associated manufacturing process |
Also Published As
| Publication number | Publication date |
|---|---|
| WO1996024160A3 (en) | 1996-10-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5933748A (en) | Shallow trench isolation process | |
| US5920108A (en) | Late process method and apparatus for trench isolation | |
| US4763177A (en) | Read only memory with improved channel length isolation and method of forming | |
| KR910002831B1 (en) | Process for manufacturing semiconductor devices | |
| US5811283A (en) | Silicon on insulator (SOI) dram cell structure and process | |
| US6756257B2 (en) | Patterned SOI regions on semiconductor chips | |
| US6069058A (en) | Shallow trench isolation for semiconductor devices | |
| JP2901444B2 (en) | Semiconductor device and manufacturing method thereof | |
| US8691660B2 (en) | Semiconductor component with trench isolation and corresponding production method | |
| US5872044A (en) | Late process method for trench isolation | |
| CN1237601C (en) | Semiconductor devices | |
| US6297109B1 (en) | Method to form shallow junction transistors while eliminating shorts due to junction spiking | |
| US6143624A (en) | Shallow trench isolation formation with spacer-assisted ion implantation | |
| EP0162774B1 (en) | Improvements in integrated circuit chip processing techniques and integrated circuit chip produced thereby | |
| US5932913A (en) | MOS transistor with controlled shallow source/drain junction, source/drain strap portions, and source/drain electrodes on field insulation layers | |
| US6514809B1 (en) | SOI field effect transistors with body contacts formed by selective etch and fill | |
| US5438015A (en) | Silicon-on-insulator technique with buried gap | |
| US6326272B1 (en) | Method for forming self-aligned elevated transistor | |
| US6599810B1 (en) | Shallow trench isolation formation with ion implantation | |
| US5525533A (en) | Method of making a low voltage coefficient capacitor | |
| KR0140715B1 (en) | Method for forming a transistor base region under thick oxide | |
| US6521942B2 (en) | Electrically programmable memory cell | |
| EP0939974B1 (en) | Manufacture of a semiconductor device with a mos transistor having an ldd structure | |
| US6538284B1 (en) | SOI device with body recombination region, and method | |
| RU1830156C (en) | Method of producing semiconducting device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AK | Designated states |
Kind code of ref document: A2 Designated state(s): CN JP KR |
|
| AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 1996900059 Country of ref document: EP |
|
| WWW | Wipo information: withdrawn in national office |
Ref document number: 1996900059 Country of ref document: EP |
|
| AK | Designated states |
Kind code of ref document: A3 Designated state(s): CN JP KR |
|
| AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE |
|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
| 122 | Ep: pct application non-entry in european phase |