DE19907070C2 - Halbleiterkontakt und zugehöriges Herstellungsverfahren - Google Patents

Halbleiterkontakt und zugehöriges Herstellungsverfahren

Info

Publication number
DE19907070C2
DE19907070C2 DE19907070A DE19907070A DE19907070C2 DE 19907070 C2 DE19907070 C2 DE 19907070C2 DE 19907070 A DE19907070 A DE 19907070A DE 19907070 A DE19907070 A DE 19907070A DE 19907070 C2 DE19907070 C2 DE 19907070C2
Authority
DE
Germany
Prior art keywords
layer
region
silicon
semiconductor substrate
dopant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19907070A
Other languages
German (de)
English (en)
Other versions
DE19907070A1 (de
Inventor
Masakazu Okada
Keiichi Higashitani
Hiroshi Kawashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE19907070A1 publication Critical patent/DE19907070A1/de
Application granted granted Critical
Publication of DE19907070C2 publication Critical patent/DE19907070C2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
DE19907070A 1998-06-23 1999-02-19 Halbleiterkontakt und zugehöriges Herstellungsverfahren Expired - Fee Related DE19907070C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10176166A JP2000012687A (ja) 1998-06-23 1998-06-23 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
DE19907070A1 DE19907070A1 (de) 2000-01-13
DE19907070C2 true DE19907070C2 (de) 2003-08-21

Family

ID=16008827

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19907070A Expired - Fee Related DE19907070C2 (de) 1998-06-23 1999-02-19 Halbleiterkontakt und zugehöriges Herstellungsverfahren

Country Status (4)

Country Link
US (1) US6531737B2 (https=)
JP (1) JP2000012687A (https=)
KR (1) KR100328536B1 (https=)
DE (1) DE19907070C2 (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6335249B1 (en) * 2000-02-07 2002-01-01 Taiwan Semiconductor Manufacturing Company Salicide field effect transistors with improved borderless contact structures and a method of fabrication
KR20020002007A (ko) * 2000-06-29 2002-01-09 박종섭 반도체 소자의 콘택홀 형성방법
JP4514006B2 (ja) * 2000-10-25 2010-07-28 ソニー株式会社 半導体装置
JP4733869B2 (ja) * 2001-07-25 2011-07-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7049667B2 (en) 2002-09-27 2006-05-23 Hrl Laboratories, Llc Conductive channel pseudo block process and circuit to inhibit reverse engineering
US6979606B2 (en) * 2002-11-22 2005-12-27 Hrl Laboratories, Llc Use of silicon block process step to camouflage a false transistor
WO2004055868A2 (en) * 2002-12-13 2004-07-01 Hrl Laboratories, Llc Integrated circuit modification using well implants
JP4343074B2 (ja) * 2004-03-19 2009-10-14 株式会社リコー 容器収納装置、該容器収納装置を備えた搬送装置及び画像形成装置
US7242063B1 (en) 2004-06-29 2007-07-10 Hrl Laboratories, Llc Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
KR100683852B1 (ko) * 2004-07-02 2007-02-15 삼성전자주식회사 반도체 소자의 마스크롬 소자 및 그 형성 방법
US8168487B2 (en) 2006-09-28 2012-05-01 Hrl Laboratories, Llc Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer
US8664050B2 (en) * 2012-03-20 2014-03-04 International Business Machines Corporation Structure and method to improve ETSOI MOSFETS with back gate
CN103594417A (zh) * 2012-08-13 2014-02-19 中芯国际集成电路制造(上海)有限公司 互连结构的制作方法
US9029940B2 (en) 2013-01-18 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical tunneling field-effect transistor cell
US9159826B2 (en) 2013-01-18 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical tunneling field-effect transistor cell and fabricating the same
US10534045B2 (en) * 2017-09-20 2020-01-14 Texas Instruments Incorporated Vertical hall-effect sensor for detecting two-dimensional in-plane magnetic fields

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4566914A (en) * 1983-05-13 1986-01-28 Micro Power Systems, Inc. Method of forming localized epitaxy and devices formed therein
JPS62190847A (ja) * 1986-02-18 1987-08-21 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
DE3625742C2 (de) * 1985-08-05 1995-06-29 Rca Corp Integrierte CMOS-Schaltung
GB2289984A (en) * 1994-05-07 1995-12-06 Hyundai Electronics Ind Dram storage electrode fabrication
WO1996024160A2 (en) * 1995-01-30 1996-08-08 Philips Electronics N.V. Method of manufacturing a semiconductor device with a semiconductor body with field insulation regions provided with recessed connection conductors
DE4337355C2 (de) * 1993-11-02 1997-08-21 Siemens Ag Verfahren zur Herstellung eines Kontaktlochs zu einem dotierten Bereich
EP0838862A1 (en) * 1996-09-27 1998-04-29 Nec Corporation Semiconductor device and method of producing the same
DE19629736C2 (de) * 1996-01-26 2000-12-14 Mitsubishi Electric Corp Halbleitereinrichtung mit selbstjustierendem Kontakt und Herstellungsverfahren dafür

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5492858A (en) * 1994-04-20 1996-02-20 Digital Equipment Corporation Shallow trench isolation process for high aspect ratio trenches
JP3022744B2 (ja) * 1995-02-21 2000-03-21 日本電気株式会社 半導体装置及びその製造方法
US5652176A (en) * 1995-02-24 1997-07-29 Motorola, Inc. Method for providing trench isolation and borderless contact
JPH08277938A (ja) 1995-04-06 1996-10-22 Daihatsu Motor Co Ltd オイルフィラーキャップのシール構造
US5976769A (en) * 1995-07-14 1999-11-02 Texas Instruments Incorporated Intermediate layer lithography
US5703391A (en) 1996-06-27 1997-12-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having element isolating insulating film in contact hole
JP2924814B2 (ja) * 1996-09-26 1999-07-26 日本電気株式会社 半導体装置の製造方法
US6018180A (en) * 1997-12-23 2000-01-25 Advanced Micro Devices, Inc. Transistor formation with LI overetch immunity
US6018184A (en) * 1998-01-22 2000-01-25 Micron Technology, Inc. Semiconductor structure useful in a self-aligned contact having multiple insulation layers of non-uniform thickness

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4566914A (en) * 1983-05-13 1986-01-28 Micro Power Systems, Inc. Method of forming localized epitaxy and devices formed therein
DE3625742C2 (de) * 1985-08-05 1995-06-29 Rca Corp Integrierte CMOS-Schaltung
JPS62190847A (ja) * 1986-02-18 1987-08-21 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
DE4337355C2 (de) * 1993-11-02 1997-08-21 Siemens Ag Verfahren zur Herstellung eines Kontaktlochs zu einem dotierten Bereich
GB2289984A (en) * 1994-05-07 1995-12-06 Hyundai Electronics Ind Dram storage electrode fabrication
WO1996024160A2 (en) * 1995-01-30 1996-08-08 Philips Electronics N.V. Method of manufacturing a semiconductor device with a semiconductor body with field insulation regions provided with recessed connection conductors
DE19629736C2 (de) * 1996-01-26 2000-12-14 Mitsubishi Electric Corp Halbleitereinrichtung mit selbstjustierendem Kontakt und Herstellungsverfahren dafür
EP0838862A1 (en) * 1996-09-27 1998-04-29 Nec Corporation Semiconductor device and method of producing the same

Also Published As

Publication number Publication date
JP2000012687A (ja) 2000-01-14
US20010042892A1 (en) 2001-11-22
US6531737B2 (en) 2003-03-11
KR100328536B1 (ko) 2002-03-25
DE19907070A1 (de) 2000-01-13
KR20000005599A (ko) 2000-01-25

Similar Documents

Publication Publication Date Title
DE4220497B4 (de) Halbleiterspeicherbauelement und Verfahren zu dessen Herstellung
DE19907070C2 (de) Halbleiterkontakt und zugehöriges Herstellungsverfahren
DE10235986B4 (de) Nichtflüchtige Speichervorrichtung mit einer schwebenden Trap-Speicherzelle und Verfahren zur Herstellung derselben
DE4127967C2 (de) MOS-Transistor mit Gate-Drain-Elektrodenüberlapp und Verfahren zu seiner Herstellung
DE4028488C2 (de) Verfahren zur Herstellung einer Halbleiterspeichervorrichtung
DE4445345C2 (de) Verfahren zur Herstellung eines Bipolartransistors
DE10259745A1 (de) Halbleitervorrichtung und Verfahren zur Herstellung derselben
DE10059620A1 (de) Halbleitervorrichtung,Verfahren zum Herstellen derselben und Verfahren zum Anordnen eines Dummybereiches
EP0993049A1 (de) Vertikaler Feldeffekttransistor mit ringförmigem Graben-Gate und Verfahren zu dessen Herstellung
DE10236682A1 (de) Halbleitervorrichtung
DE3834241A1 (de) Halbleitereinrichtung
DE69526486T2 (de) Verfahren zum Herstellen einer Kontaktfläche in einer integrierten Schaltung
DE4007582C2 (de) Verfahren zum Herstellen von mindestens zwei Kontakten in einem Halbleiterbauelement
DE10128718B4 (de) Grabenkondensator einer DRAM-Speicherzelle mit metallischem Collarbereich und nicht-metallischer Leitungsbrücke zum Auswahltransistor
DE19750918A1 (de) Halbleitereinrichtung und zugehöriges Herstellungsverfahren
DE10120053A1 (de) Stressreduziertes Schichtsystem
DE10330070A1 (de) Halbleitervorrichtung und Verfahren zur Herstellung derselben
DE19615692C2 (de) Halbleitervorrichtung und Herstellungsverfahren einer Halbleitereinrichtung
DE4113962C2 (de) Halbleitereinrichtung mit selbstausgerichteter Kontaktstruktur für Feldeffekttransistoren und Herstellungsverfahren für diese
DE10162905B4 (de) Neuartiges Konsolidierungsverfahren für die Übergangskontaktätzung für DT-basierte DRAM-Bauelemente mit weniger als 150 NM
DE10109564A1 (de) Grabenkondensator und Verfahren zu seiner Herstellung
DE102005025951B4 (de) Verfahren zum Herstellen einer Mehrschicht-Gatestapelstruktur mit einer Metallschicht und Gatestapelstruktur für eine FET-Vorrichtung
DE19542606C2 (de) MIS-Transistor mit einem Dreischicht-Einrichtungsisolationsfilm und Herstellungsverfahren
DE4120592C2 (de) Halbleitereinrichtung und Verfahren zu deren Herstellung
DE3923619C2 (https=)

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8125 Change of the main classification

Ipc: H01L 21/283

8304 Grant after examination procedure
8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Effective date: 20130903