KR100261646B1 - 반도체 장치의 제조 방법 - Google Patents

반도체 장치의 제조 방법 Download PDF

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Publication number
KR100261646B1
KR100261646B1 KR1019970071900A KR19970071900A KR100261646B1 KR 100261646 B1 KR100261646 B1 KR 100261646B1 KR 1019970071900 A KR1019970071900 A KR 1019970071900A KR 19970071900 A KR19970071900 A KR 19970071900A KR 100261646 B1 KR100261646 B1 KR 100261646B1
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KR
South Korea
Prior art keywords
oxide film
film
silicide
semiconductor substrate
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019970071900A
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English (en)
Korean (ko)
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KR19990022665A (ko
Inventor
시게노부 마에다
Original Assignee
다니구찌 이찌로오, 기타오카 다카시
미쓰비시덴키 가부시키가이샤
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Publication date
Application filed by 다니구찌 이찌로오, 기타오카 다카시, 미쓰비시덴키 가부시키가이샤 filed Critical 다니구찌 이찌로오, 기타오카 다카시
Publication of KR19990022665A publication Critical patent/KR19990022665A/ko
Application granted granted Critical
Publication of KR100261646B1 publication Critical patent/KR100261646B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/50—Alloying conductive materials with semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment

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  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
KR1019970071900A 1997-08-22 1997-12-22 반도체 장치의 제조 방법 Expired - Fee Related KR100261646B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP97-226289 1997-08-22
JP9226289A JPH1168103A (ja) 1997-08-22 1997-08-22 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
KR19990022665A KR19990022665A (ko) 1999-03-25
KR100261646B1 true KR100261646B1 (ko) 2000-08-01

Family

ID=16842888

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970071900A Expired - Fee Related KR100261646B1 (ko) 1997-08-22 1997-12-22 반도체 장치의 제조 방법

Country Status (6)

Country Link
US (1) US6008077A (https=)
JP (1) JPH1168103A (https=)
KR (1) KR100261646B1 (https=)
DE (1) DE19819438C2 (https=)
FR (1) FR2767603B1 (https=)
TW (1) TW371789B (https=)

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JPH11317527A (ja) * 1998-05-06 1999-11-16 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6555455B1 (en) * 1998-09-03 2003-04-29 Micron Technology, Inc. Methods of passivating an oxide surface subjected to a conductive material anneal
TW405164B (en) * 1999-01-04 2000-09-11 United Microelectronics Corp Method for manufacturing self-aligned silicide
US6121091A (en) * 1999-01-19 2000-09-19 Taiwan Semiconductor Manufacturing Company Reduction of a hot carrier effect phenomena via use of transient enhanced diffusion processes
EP1049167A3 (en) 1999-04-30 2007-10-24 Sel Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US6180462B1 (en) * 1999-06-07 2001-01-30 United Microelectronics Corp. Method of fabricating an analog integrated circuit with ESD protection
US6433388B2 (en) * 1999-06-29 2002-08-13 Oki Electric Industry Co., Ltd Semiconductor device with self-aligned areas formed using a supplemental silicon overlayer
KR100322886B1 (ko) * 1999-07-01 2002-02-09 박종섭 반도체장치의 금속 콘택 형성 방법
JP2001077209A (ja) 1999-07-08 2001-03-23 Mitsubishi Electric Corp 半導体装置の製造方法
US6204129B1 (en) * 1999-10-22 2001-03-20 United Microelectronics Corp Method for producing a high-voltage and low-voltage MOS transistor with salicide structure
JP2001196549A (ja) 2000-01-11 2001-07-19 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
US6277683B1 (en) * 2000-02-28 2001-08-21 Chartered Semiconductor Manufacturing Ltd. Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layer
US6441434B1 (en) 2000-03-31 2002-08-27 Advanced Micro Devices, Inc. Semiconductor-on-insulator body-source contact and method
US6525381B1 (en) 2000-03-31 2003-02-25 Advanced Micro Devices, Inc. Semiconductor-on-insulator body-source contact using shallow-doped source, and method
JP4676069B2 (ja) * 2001-02-07 2011-04-27 パナソニック株式会社 半導体装置の製造方法
US6410371B1 (en) * 2001-02-26 2002-06-25 Advanced Micro Devices, Inc. Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer
US6670263B2 (en) * 2001-03-10 2003-12-30 International Business Machines Corporation Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size
KR20030052814A (ko) * 2001-12-21 2003-06-27 동부전자 주식회사 반도체소자의 제조방법
DE10208904B4 (de) 2002-02-28 2007-03-01 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung unterschiedlicher Silicidbereiche auf verschiedenen Silicium enthaltenden Gebieten in einem Halbleiterelement
DE10208728B4 (de) 2002-02-28 2009-05-07 Advanced Micro Devices, Inc., Sunnyvale Ein Verfahren zur Herstellung eines Halbleiterelements mit unterschiedlichen Metallsilizidbereichen
DE10209059B4 (de) 2002-03-01 2007-04-05 Advanced Micro Devices, Inc., Sunnyvale Ein Halbleiterelement mit unterschiedlichen Metall-Halbleiterbereichen, die auf einem Halbleitergebiet gebildet sind, und Verfahren zur Herstellung des Halbleiterelements
DE10234931A1 (de) 2002-07-31 2004-02-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Metallsilizidgates in einer standardmässigen MOS-Prozesssequenz
US6815235B1 (en) 2002-11-25 2004-11-09 Advanced Micro Devices, Inc. Methods of controlling formation of metal silicide regions, and system for performing same
KR100588653B1 (ko) * 2002-12-30 2006-06-12 동부일렉트로닉스 주식회사 반도체 소자의 제조방법
KR100559572B1 (ko) * 2003-09-01 2006-03-10 동부아남반도체 주식회사 살리사이드를 갖는 반도체 소자 제조 방법
US7227234B2 (en) * 2004-12-14 2007-06-05 Tower Semiconductor Ltd. Embedded non-volatile memory cell with charge-trapping sidewall spacers
DE102009010883B4 (de) * 2009-02-27 2011-05-26 Amd Fab 36 Limited Liability Company & Co. Kg Einstellen eines nicht-Siliziumanteils in einer Halbleiterlegierung während der FET-Transistorherstellung mittels eines Zwischenoxidationsprozesses
JP2012222023A (ja) * 2011-04-05 2012-11-12 Renesas Electronics Corp 半導体装置の製造方法
US8883598B2 (en) * 2012-03-05 2014-11-11 Taiwan Semiconductor Manufacturing Co., Ltd. Thin capped channel layers of semiconductor devices and methods of forming the same
US10840333B2 (en) * 2018-10-31 2020-11-17 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement and method of manufacture

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Publication number Priority date Publication date Assignee Title
US4874713A (en) * 1989-05-01 1989-10-17 Ncr Corporation Method of making asymmetrically optimized CMOS field effect transistors
US5262344A (en) * 1990-04-27 1993-11-16 Digital Equipment Corporation N-channel clamp for ESD protection in self-aligned silicided CMOS process
US5021853A (en) * 1990-04-27 1991-06-04 Digital Equipment Corporation N-channel clamp for ESD protection in self-aligned silicided CMOS process
JP2940880B2 (ja) * 1990-10-09 1999-08-25 三菱電機株式会社 半導体装置およびその製造方法
JP3181695B2 (ja) * 1992-07-08 2001-07-03 ローム株式会社 Ｓｏｉ基板を用いた半導体装置の製造方法
US5589423A (en) * 1994-10-03 1996-12-31 Motorola Inc. Process for fabricating a non-silicided region in an integrated circuit
DE19510777C1 (de) * 1995-03-24 1996-06-05 Itt Ind Gmbh Deutsche Verfahren zum Herstellen einer CMOS-Struktur mit ESD-Schutz
US5672527A (en) * 1996-03-08 1997-09-30 United Microelectronics Corp. Method for fabricating an electrostatic discharge protection circuit
US5585299A (en) * 1996-03-19 1996-12-17 United Microelectronics Corporation Process for fabricating a semiconductor electrostatic discharge (ESD) protective device
US5814537A (en) * 1996-12-18 1998-09-29 Sharp Microelectronics Technology,Inc. Method of forming transistor electrodes from directionally deposited silicide

Also Published As

Publication number Publication date
DE19819438C2 (de) 2002-01-24
FR2767603A1 (fr) 1999-02-26
US6008077A (en) 1999-12-28
KR19990022665A (ko) 1999-03-25
FR2767603B1 (fr) 2003-07-04
TW371789B (en) 1999-10-11
DE19819438A1 (de) 1999-03-04
JPH1168103A (ja) 1999-03-09

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