JPS6396947A - 半導体装置用リ−ドフレ−ム - Google Patents

半導体装置用リ−ドフレ−ム

Info

Publication number
JPS6396947A
JPS6396947A JP61243612A JP24361286A JPS6396947A JP S6396947 A JPS6396947 A JP S6396947A JP 61243612 A JP61243612 A JP 61243612A JP 24361286 A JP24361286 A JP 24361286A JP S6396947 A JPS6396947 A JP S6396947A
Authority
JP
Japan
Prior art keywords
lead
resin
lead frame
layer
plated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61243612A
Other languages
English (en)
Inventor
Toshiaki Shinohara
利彰 篠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61243612A priority Critical patent/JPS6396947A/ja
Priority to KR1019870008766A priority patent/KR900007230B1/ko
Priority to GB8724006A priority patent/GB2195826B/en
Priority to US07/108,907 priority patent/US4942455A/en
Publication of JPS6396947A publication Critical patent/JPS6396947A/ja
Priority to US07/315,054 priority patent/US5026669A/en
Priority to SG52991A priority patent/SG52991G/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/48639—Silver (Ag) as principal constituent
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    • H01L2224/491—Disposition
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、樹脂封止型半導体装置の組立工程に使用さ
れるリードフレームに関するものである。
〔従来の技術〕
第４ｇは従来の１ｓ積回路の組立工程に使用されるリー
ドフレームを示すものであり、薄い金属条からエツチン
グ処理又は金型による抜きにより所定のパターンが形成
される。図において、１はアウターリード２間を接続す
るタイバー、３は封止後、樹脂中に入るインナーリード
、４はチップをのせるダイスパッドである。なお図中ハ
ツチング部はチップの接合及びチップの電極とインナー
リード３間をＡｕｇ等で接続を容易にするためのＡｇ又
はＡｕのメッキ部である。
次に第５図はダイスパッド４にチップ５が接合され、チ
ップ５の電極とインナーリード３との間の電気的接続を
得るためのＡｕ１ｉ等の細線６で接続された工程を示す
。その後、第６図に示すように、リードフレーム１１を
モールド金型の上型９と下型１０の間にはさみ込み、エ
ギキシ樹脂等の熱硬化型樹脂を低圧トランスファー成形
法等によりキャビティ中に注入し、樹脂８が成形される
。この成形後のフレームを第７図に示す。なお図中１２
はモールド金型とフレームとの隙間に樹脂が流入して成
形された薄膜（以下パリという）を示す。このパリは、
金型の平面精度、リードフレームの板厚のバラツキ及び
金型を締めるプレスの均一加圧性、封止’１４ＨＮの流
動性、フレーム加工によるダレ等により発生し、このま
までは後の工程のアウターリードのメッキが着かないと
いう不具合があるので、モールド成形後、乾式ホーニン
グや湿式ホーニング等によりパリを除去していた。又電
解パリ取り後、高水圧によるパリ除去方法等も採用され
ていた。
〔発明が解決しようとするａｔｅ点〕
従来のリードフレームは以上のようにして構成されるが
、この際上記の様なパリ取り作業は本来不要な工程であ
り、ホーニングを使った場合、パリと同時にパッケージ
も同時に損傷を受け、リードフレームも表面粗れ、細り
を起こし、メッキ針状析出を発生させたり、リード強度
を弱くするという不具合があった。また電解と高水圧に
よりパリ取り方法は、厚いパリが発生した場合には完全
に除去されないという不具合があった。また以上のよう
なパリ取り設備及び作業により製品のコストを引上げろ
要因となっていた。
この発明は上記のような問題点を解消するためになされ
たもので、ＩＩｓ脂封止工程におけるパリの発生を最小
限に抑え、特別なパリ取り設備及び工程を不要にし、ｔ
！Ｒ脂、リードに損傷を与えないことを目的とする。
〔問題点を解決するための手段〕
この発明に係るリードフレームは、封止樹脂の外側のア
ウターリード及びタイバー部に鉛などの薄膜金属層を施
したものである。
〔作用〕
この発明における薄膜金属層は、チップの接合時、チッ
プの電極とインナーリードを電気的に接続するための細
線接続時、及び樹脂封止工程における温度によっても溶
融せず、しかもモールド工程において金型でリードフレ
ームを締めるとき、硬度が低いため変形して金型とリー
ドフレームとの隙間をなくシ、パリの発生を防ぐ。
〔実施例〕
以下この発明の一実ｔ１１例を図について説明する。
第１図は本発明のリードフレームを示すもので、１３は
鉛メツキ部分であり、パッケージ（樹ｆｉｌ）の外側か
らタイバー２を少し越えるところまでリードフレームの
表裏及び側面に施されている。この範囲は通常最終製品
に加工されたとき残る場所で、パリの出る範囲が設定さ
れる。なおこのメッキ厚は、金型、リードフレームの寸
法精度、プレスの型締圧力等にもよるが、通常５μ〜１
０μの範囲に付着される。この鉛メッキは、ダイスパッ
ド部４及びインナーリード３の先端につけられるＡｇ又
はＡｕメッキの工程で同時処理により容易に得られる。
このリードフレームを用いてダイスパッド４上にチップ
の接合を行い、チップの電極とインナーリード間を細線
により接続する。チップの接合温度は、Ｕ接合を行う場
合、約２００℃、又細線の接合温度は２５０℃付近であ
る。又樹脂封止時の金型温度は約１８０℃である。なお
鉛メッキの融点は３２７℃であり、組立工程中に溶融す
ることはない。
次に第２図は樹脂封止工程を示すもので、１３は鉛メッ
キの暦を示し、リードフレーム１１と、上型９、下型１
０の隙間を鉛メッキがプレスの型締圧による変形により
埋めてしまうため、パリになる樹脂の流出を防止できる
。又仮に鉛メッキと金型間に樹脂が流出しても、パリは
鉛メツキ上に付着する。樹脂封止後、アウターリード上
にリードの半田付性を向上させるため、通常半田メッキ
が施されるが、この工程中に鉛メッキの剥離槽（溶液と
して硝酸１５％溶ｗＲ）を設けることにより、鉛メッキ
は容易に除去されると共に、鉛メツキ上に付着したパリ
は完全に除去される。第３図ａはモールド工程後の斜視
図であり、剥離工程を通ることにより、ｂのようにリー
ド上のパリは完全に除去される。
なお上記実施例では、メッキ材に鉛を使用したが、鉛以
外の金属（例えばＡｇ、　Ｓｎ等）でも溶融しなくて、
容易に変形するものであれば適用可能である。又リード
フレームへの鉛をつける方法としてメッキを採用したが
、薄膜の圧接、溶射等の方法も応用可能である。
〔発明の効果〕
以上のようにこの発明によれば、半導体装置の組立工程
中の＊脂封止時、ｊｆ！！脂の流出部分のリードフレー
ム上に鉛などの軟かい薄膜金属層を施すことにより、封
止工程のパリ発生を防止できると共に、多少流出しても
メッキ工程中の剥離工程で完全に除去でき、又従来のホ
ーニング等のパリ取り工程及び設備を省略できるなどの
効果がある。
【図面の簡単な説明】
第１図〜第３図はこの発明の一実施例を示すもので、第
１図はリードフレームの斜視図、第２図は要部の断面図
、第３図ａ、ｂは樹脂封止工程を示す説明図、第４図〜
第７図はこの種の従来のリードフレームを示すもので、
第４図は斜視図、第５図〜第７図は組立工程を示す説明
図である。 図中、１はタイバー、２はアウターリード、３はインナ
ーリード、４はダイスパッド、８は樹脂、１３は鉛メッ
キ層である。 尚、図中同一符号は同−又は相当部分を示す。

Claims (3)

    【特許請求の範囲】
  1. （１）樹脂封止型半導体装置の組立工程に使用されるリ
    ードフレームにおいて、封止樹脂より外部のアウターリ
    ード及びタイバー部に、難溶融性で変形し易い薄膜金属
    層を施したことを特徴とする半導体装置用リードフレー
    ム。
  2. （２）薄膜金属層は鉛メッキにより形成されている特許
    請求の範囲第１項記載の半導体装置用リードフレーム。
  3. （３）薄膜金属層の厚さは１μ〜２０μである特許請求
    の範囲第１項または第２項記載の半導体装置用リードフ
    レーム。
JP61243612A 1986-10-13 1986-10-13 半導体装置用リ−ドフレ−ム Pending JPS6396947A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP61243612A JPS6396947A (ja) 1986-10-13 1986-10-13 半導体装置用リ−ドフレ−ム
KR1019870008766A KR900007230B1 (ko) 1986-10-13 1987-08-10 반도체 장치용 리드프레임
GB8724006A GB2195826B (en) 1986-10-13 1987-10-13 A lead frame for a semiconductor device and a method for manufacturing a semiconductor device using the lead frame
US07/108,907 US4942455A (en) 1986-10-13 1987-10-13 Lead frame for a semiconductor device and a method for manufacturing a semiconductor device using the lead frame
US07/315,054 US5026669A (en) 1986-10-13 1989-02-24 Method of eliminating burrs on a lead frame with a thin metal coating
SG52991A SG52991G (en) 1986-10-13 1991-07-09 A lead frame for a semiconductor device and a method for manufacturing a semiconductor device using the lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61243612A JPS6396947A (ja) 1986-10-13 1986-10-13 半導体装置用リ−ドフレ−ム

Publications (1)

Publication Number Publication Date
JPS6396947A true JPS6396947A (ja) 1988-04-27

Family

ID=17106405

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61243612A Pending JPS6396947A (ja) 1986-10-13 1986-10-13 半導体装置用リ−ドフレ−ム

Country Status (5)

Country Link
US (2) US4942455A (ja)
JP (1) JPS6396947A (ja)
KR (1) KR900007230B1 (ja)
GB (1) GB2195826B (ja)
SG (1) SG52991G (ja)

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EP0620590A1 (en) * 1993-03-30 1994-10-19 AT&T Corp. Leadframe processing for molded package arrangements
EP0620589A1 (en) * 1993-03-30 1994-10-19 AT&T Corp. Leadframe structure for molded package arrangements
US6303983B1 (en) 1998-05-01 2001-10-16 Nec Corporation Apparatus for manufacturing resin-encapsulated semiconductor devices
JP2008112961A (ja) * 2006-10-04 2008-05-15 Rohm Co Ltd 半導体装置の製造方法および半導体装置
JP2014029995A (ja) * 2012-06-27 2014-02-13 Dainippon Printing Co Ltd リードフレームおよびその製造方法、樹脂付リードフレームおよびその製造方法、ならびにｌｅｄパッケージおよびその製造方法
CN103985644A (zh) * 2013-02-13 2014-08-13 精工电子有限公司 树脂密封型半导体装置的制造方法以及引脚架

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JPH0760839B2 (ja) * 1990-03-15 1995-06-28 株式会社東芝 半導体装置
JP2585830B2 (ja) * 1990-03-28 1997-02-26 株式会社東芝 樹脂封止型半導体装置及びその製造方法
JPH0595079A (ja) * 1991-10-02 1993-04-16 Ibiden Co Ltd リードフレーム、半導体集積回路搭載用基板及び半導体装置並びにそれらの製造方法
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CN1134839C (zh) * 1997-12-26 2004-01-14 三星航空产业株式会社 引线框架及涂敷引线框架的方法
US5930604A (en) * 1998-02-02 1999-07-27 Delco Electronics Corporation Encapsulation method for fine-pitch chip-on-board
DE19921867C2 (de) 1999-05-11 2001-08-30 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleiterbauelements mit mindestens einem verkapselten Chip auf einem Substrat
JP3878781B2 (ja) * 1999-12-27 2007-02-07 株式会社ルネサステクノロジ 半導体装置の製造方法
US6396129B1 (en) * 2001-03-05 2002-05-28 Siliconware Precision Industries Co., Ltd. Leadframe with dot array of silver-plated regions on die pad for use in exposed-pad semiconductor package
JP4626919B2 (ja) * 2001-03-27 2011-02-09 ルネサスエレクトロニクス株式会社 半導体装置
KR100464752B1 (ko) * 2002-11-29 2005-01-05 한국섬유개발연구원 의마섬유 및 그 제조방법
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US7192809B2 (en) * 2005-02-18 2007-03-20 Texas Instruments Incorporated Low cost method to produce high volume lead frames
KR100789419B1 (ko) 2006-11-27 2007-12-28 (주)원일사 리드프레임 모재 가공방법
JP5252819B2 (ja) * 2007-03-26 2013-07-31 三菱電機株式会社 半導体装置およびその製造方法
JP2010056372A (ja) 2008-08-29 2010-03-11 Sanyo Electric Co Ltd 樹脂封止型半導体装置とその製造方法
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CN104795377B (zh) * 2014-01-17 2019-02-19 恩智浦美国有限公司 具有引线网的半导体器件

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EP0620590A1 (en) * 1993-03-30 1994-10-19 AT&T Corp. Leadframe processing for molded package arrangements
EP0620589A1 (en) * 1993-03-30 1994-10-19 AT&T Corp. Leadframe structure for molded package arrangements
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JP2008112961A (ja) * 2006-10-04 2008-05-15 Rohm Co Ltd 半導体装置の製造方法および半導体装置
JP2014029995A (ja) * 2012-06-27 2014-02-13 Dainippon Printing Co Ltd リードフレームおよびその製造方法、樹脂付リードフレームおよびその製造方法、ならびにｌｅｄパッケージおよびその製造方法
CN103985644A (zh) * 2013-02-13 2014-08-13 精工电子有限公司 树脂密封型半导体装置的制造方法以及引脚架
JP2014154848A (ja) * 2013-02-13 2014-08-25 Seiko Instruments Inc 樹脂封止型半導体装置の製造方法およびリードフレーム

Also Published As

Publication number Publication date
GB2195826B (en) 1990-01-10
KR880005678A (ko) 1988-06-30
US5026669A (en) 1991-06-25
GB2195826A (en) 1988-04-13
SG52991G (en) 1991-08-23
GB8724006D0 (en) 1987-11-18
KR900007230B1 (ko) 1990-10-05
US4942455A (en) 1990-07-17

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