JPS57202766A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPS57202766A
JPS57202766A JP8659481A JP8659481A JPS57202766A JP S57202766 A JPS57202766 A JP S57202766A JP 8659481 A JP8659481 A JP 8659481A JP 8659481 A JP8659481 A JP 8659481A JP S57202766 A JPS57202766 A JP S57202766A
Authority
JP
Japan
Prior art keywords
resin
plating
lead
bar
plating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8659481A
Other languages
Japanese (ja)
Inventor
Nobutaka Nagamine
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KIYUUSHIYUU NIPPON DENKI KK
NEC Kyushu Ltd
Original Assignee
KIYUUSHIYUU NIPPON DENKI KK
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KIYUUSHIYUU NIPPON DENKI KK, NEC Kyushu Ltd filed Critical KIYUUSHIYUU NIPPON DENKI KK
Priority to JP8659481A priority Critical patent/JPS57202766A/en
Publication of JPS57202766A publication Critical patent/JPS57202766A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent adhesion of plating on the surface of resin when plating is to be performed on a lead frame for a resin package having the semiconductor element fixing part and the plural number of inside lead parts and outside lead parts by a method wherein the step difference formed by half etching or coating is provided on a part of dam for prevention of flowing out of resin. CONSTITUTION:Resin 4'' for tie bars of plural number of pieces are formed on the outside circumference of the package 1, and the tie bar 2' to be used as the dam for prevention of flowing out of resin and having the outside lead 10' at one end is fixed thereto. Then a plating layer 3' is adhered from the surface of the bar 2' to the surface of the lead 10' by plating, but the plating layer 3' gets on the surface of resin 4'' when the condition remains as it is. Accordingly half etching or coating is applied to the tip part of the tie bar 2' coming in contact with resin 4'' to make the step difference to be generated between resin 4'' and the bar 2', and the plating layer 3' is stopped thereat.
JP8659481A 1981-06-05 1981-06-05 Lead frame for semiconductor device Pending JPS57202766A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8659481A JPS57202766A (en) 1981-06-05 1981-06-05 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8659481A JPS57202766A (en) 1981-06-05 1981-06-05 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPS57202766A true JPS57202766A (en) 1982-12-11

Family

ID=13891321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8659481A Pending JPS57202766A (en) 1981-06-05 1981-06-05 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPS57202766A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943560A (en) * 1982-09-02 1984-03-10 Mitsubishi Electric Corp Lead frame for semiconductor device
US4942455A (en) * 1986-10-13 1990-07-17 Mitsubishi Denki Kabushiki Kaisha Lead frame for a semiconductor device and a method for manufacturing a semiconductor device using the lead frame
KR100531422B1 (en) * 2000-10-11 2005-11-28 앰코 테크놀로지 코리아 주식회사 structure of lead frame for fabricating semiconductor package

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943560A (en) * 1982-09-02 1984-03-10 Mitsubishi Electric Corp Lead frame for semiconductor device
US4942455A (en) * 1986-10-13 1990-07-17 Mitsubishi Denki Kabushiki Kaisha Lead frame for a semiconductor device and a method for manufacturing a semiconductor device using the lead frame
US5026669A (en) * 1986-10-13 1991-06-25 Mitsubishi Denki Kabushiki Kaisha Method of eliminating burrs on a lead frame with a thin metal coating
KR100531422B1 (en) * 2000-10-11 2005-11-28 앰코 테크놀로지 코리아 주식회사 structure of lead frame for fabricating semiconductor package

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