JPS57202745A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57202745A
JPS57202745A JP8659281A JP8659281A JPS57202745A JP S57202745 A JPS57202745 A JP S57202745A JP 8659281 A JP8659281 A JP 8659281A JP 8659281 A JP8659281 A JP 8659281A JP S57202745 A JPS57202745 A JP S57202745A
Authority
JP
Japan
Prior art keywords
tie bar
resin
mold
lead frame
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8659281A
Other languages
Japanese (ja)
Inventor
Shinichi Takeda
Kouichi Sohara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP8659281A priority Critical patent/JPS57202745A/en
Publication of JPS57202745A publication Critical patent/JPS57202745A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent a resin thin film from overflowing at resin sealing, by using a mold which does not press an outer tie bar of a lead frame. CONSTITUTION:An Si element 7 is brazed to a lead frame, wired 8, and put into a mold. The mold 3' contacts a unit pattern at a tie bar of lead frame, and has hollows at the element 7 and the outer tie bar 6. When resin is pressed and injected into the element hollow, a resin overflow 5' stops at the tie bar 6 and does not go out.
JP8659281A 1981-06-05 1981-06-05 Manufacture of semiconductor device Pending JPS57202745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8659281A JPS57202745A (en) 1981-06-05 1981-06-05 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8659281A JPS57202745A (en) 1981-06-05 1981-06-05 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57202745A true JPS57202745A (en) 1982-12-11

Family

ID=13891268

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8659281A Pending JPS57202745A (en) 1981-06-05 1981-06-05 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57202745A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4857483A (en) * 1986-04-30 1989-08-15 Sgs-Thomson Microelectronics S.A. Method for the encapsulation of integrated circuits
US5395800A (en) * 1992-01-30 1995-03-07 Fuji Electric Co., Ltd. Method for assembling semiconductor devices with lead frame containing common lead arrangement
KR100600171B1 (en) * 2000-12-26 2006-07-12 앰코 테크놀로지 코리아 주식회사 Circuit board for preventing flash

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS501662A (en) * 1973-05-07 1975-01-09
JPS5147369A (en) * 1974-10-21 1976-04-22 Hitachi Ltd Jushifushi nyoru handotaisochino seizoho
JPS5326671A (en) * 1976-08-25 1978-03-11 Hitachi Ltd Resin molding device for el ectronic parts
JPS53104171A (en) * 1977-02-23 1978-09-11 Hitachi Ltd Mold for semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS501662A (en) * 1973-05-07 1975-01-09
JPS5147369A (en) * 1974-10-21 1976-04-22 Hitachi Ltd Jushifushi nyoru handotaisochino seizoho
JPS5326671A (en) * 1976-08-25 1978-03-11 Hitachi Ltd Resin molding device for el ectronic parts
JPS53104171A (en) * 1977-02-23 1978-09-11 Hitachi Ltd Mold for semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4857483A (en) * 1986-04-30 1989-08-15 Sgs-Thomson Microelectronics S.A. Method for the encapsulation of integrated circuits
US5395800A (en) * 1992-01-30 1995-03-07 Fuji Electric Co., Ltd. Method for assembling semiconductor devices with lead frame containing common lead arrangement
KR100600171B1 (en) * 2000-12-26 2006-07-12 앰코 테크놀로지 코리아 주식회사 Circuit board for preventing flash

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