JPS62216352A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JPS62216352A
JPS62216352A JP61059744A JP5974486A JPS62216352A JP S62216352 A JPS62216352 A JP S62216352A JP 61059744 A JP61059744 A JP 61059744A JP 5974486 A JP5974486 A JP 5974486A JP S62216352 A JPS62216352 A JP S62216352A
Authority
JP
Japan
Prior art keywords
substrate
bonding
film
melting point
adhesion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61059744A
Other languages
English (en)
Other versions
JP2559700B2 (ja
Inventor
Masaaki Muto
正明 武藤
Takashi Kato
隆 加藤
Takashi Ito
隆司 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61059744A priority Critical patent/JP2559700B2/ja
Priority to KR1019870002404A priority patent/KR900003830B1/ko
Priority to US07/027,317 priority patent/US4826787A/en
Priority to EP87103983A priority patent/EP0238066B1/en
Publication of JPS62216352A publication Critical patent/JPS62216352A/ja
Application granted granted Critical
Publication of JP2559700B2 publication Critical patent/JP2559700B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Recrystallisation Techniques (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔概要〕 Ｓｉ或いはＳｉＯ□の基板をジルコニウム（Ｚｒ）等の
高融点金属のシリサイドを用いて、相互に接着する。
〔産業上の利用分野〕
本発明はＳｉ或いはＳｉＯ２の基板の接着の方法に関す
る。
これまでＬＳＩの集積度向上のためにはデバイス寸法を
縮小する方法が主であったが、今後は導電層、絶縁層を
幾層にも積み重ね、３次元化することにより更に集積度
を向上させる方法が注目されている。
この方法に必要な技術にＳｉ基板とＳｉ基板の接着があ
る。これの既存の技術としてはポリイミド等の有機物を
用いた接着法、Ｐ　Ｓ　Ｇ　（ＰｈｏｓｐｈｏｒｕｓＳ
ｉｌｉｃａｔｅ　Ｇｌａｓｓ）を用いた接着法がある。
しかし、前者は熱に弱く、接着後高温での熱処理が行え
ないこと、又炭素による汚染の問題がある。後者は接着
後の耐熱性は略良好であるが、接着する際１０００℃以
上の高温を必要とするので問題である。
Ｓｉ基板相互の接着に関して、接着温度は低く、接着後
は耐熱性のある、汚染も少ない接着法は、いままで満足
すべきものがなく、これの解決が望まれている。
〔従来の技術〕
第２図（ａ）　、（ｂ）は従来例における基板の接着工
程を説明するための断面図である。
第２図（ａ）において、１はＳｉ基板で、この表面にＣ
ＶＤ法で厚さ約５００ｎｍのＰＳＧ被膜５を被着形成す
る。
第２図（ｂ）において、ＰＳＧ被膜５形成のＳｉ基板１
の」二にＳｉ基板３を密着して載置し、Ｎ２雰囲気で約
１０００℃に熱処理し両Ｓｉ基板１．３を接着する。
この方法での接着は、接着後の耐熱性は比較的価れてい
るが、接着に１０００℃以上の熱処理を要するため、素
子形成済みのＳｉ基板に適用しづらい欠点がある。
〔発明が解決しようとする問題点〕
Ｓｉ基板相互の接着において、接着温度は低く、接着し
た後は耐熱性があり、且つ汚染も少ない接着法を提供し
ようとするものである。
〔問題点を解決するための手段〕
上記問題点の解決は、Ｓｉ基板、ＳｉＯ□被膜を表面に
形成したＳｉ基板またはＳｉＯ２基板よりなる第１の基
板の表面に高融点金属被膜を形成し、前記第１の基板の
上に、Ｓｉ基板、ＳｉＯ□被膜を表面に形成したＳｉ基
板または５ｉｎ２基板よりなる第２の基板の表面を下に
して密着載置し、熱処理して前記高融点金属被膜をシリ
ナイド化して、前記第１の基板と第２の基板を接着する
本発明による半導体装置の製造方法により達成される。
特に前記高融点金属被膜をジルコニウム、チタンまたは
ハフニウムとすることにより本発明は容易に実施するこ
とが出来る。
〔作用〕
Ｚｒ等の高融点金属は反応性にとみ還元力が優れている
ので、Ｓｉ基板の表面に薄い酸化層があっても、又Ｓｉ
ｎ、基板であってもシリサイド化して接着を可能とする
。
〔実施例〕
第１図（ａ）　、（ｂ）は本発明における基板の接着工
程を説明するための断面図である。
第１図（ａ）において、第１の基板たるＳｉ基板１の表
面上に、ＤＣマグネトロンスパッタリング法によりＺｒ
被膜２を１３０ｎｍ堆積被着する。
第１図（ｂ）において、厚さ約３００ｎｍのＳｉＯ□被
膜をその表面に形成したＳｉ基板３を、その表面を下に
してＳｉ基板１の上に密着載置して、４χＴｏ＋＾ｒ中
で６５０℃で熱処理する。するとＺｒは下のＳｉ基板１
のＳｉ１上の第２の基板３の５ｉ（ｈ被膜のＳｉと反応
してシリサイド化しＺｒ５ｉｚ　　４となる。これによ
り、上下の両基板１．３は接着される。
接着後、Ｎ２中或いは０２中でｌ０００℃、１時間熱処
理を行ったが、剥れ、割れ、変形などの変化は観察され
ず、極めて耐熱性に優れた密着性のよい、強い接着が得
られた。
以上はＳｉ基板とＳｉＯ□被膜のついたＳｉ基板の接着
に関するものであるが、Ｓｉ基板とＳｉ基板、ＳｉＯ□
基板とＳｉＯ□基板、Ｓｉｎｇ被膜付きＳｉ基板同士の
接着も可能で良好な結果を得ることが出来る。
６００〜８００℃の範囲のシリサイド化温度で強い接着
が得られた。
特に、Ｓｉ基板同士の接着は、Ｓｉ基板表面の自然酸化
膜の影響を受けることなく反応が速やかに進行するため
、強固な良好な接着が得られる。
Ｚｒの替わりにチタン（Ｔｉ）、ハフニウム（）Ｉｆ）
を使用したものでも略同様な良好な結果を得ることが出
来る。
〔発明の効果〕
Ｚｒ等の高融点金属のシリサイド化反応を用いることに
より、Ｓｉ基板やＳｉＯ□基板の良好な接着が可能であ
る。接着は６００〜８００℃の比較的低温で行うごとが
出来、又素子特性に悪影啓を及ぼすような汚染がない。
更に接着後の耐熱性、耐薬品性も優れている。
【図面の簡単な説明】
第１図（ａ）　、（ｂ）は本発明における基板の接着工
程を説明するための断面図、 第２図（ａ）　、（ｂ）は従来例における基板の接着工
程を説明するための断面図である。 これら図において、 １は第１の基板、 ２は高融点金属被膜、 ３は第２の基板、

Claims (1)

  1. 【特許請求の範囲】 〔１〕Ｓｉ基板、ＳｉＯ＿２被膜を表面に形成したＳｉ
    基板またはＳｉＯ＿２基板よりなる第１の基板（１）の
    表面に高融点金属被膜（２）を形成し、前記第１の基板
    （１）の上に、Ｓｉ基板、ＳｉＯ＿２被膜を表面に形成
    したＳｉ基板またはＳｉＯ＿２基板よりなる第２の基板
    （３）の表面を下にして密着載置し、熱処理して前記高
    融点金属被膜（２）をシリサイド（４）化して、前記第
    １の基板（１）と第２の基板（３）を接着する ことを特徴とする半導体装置の製造方法。 〔２〕前記高融点金属被膜（２）がジルコニウム、チタ
    ンまたはハフニウムであることを特徴とする特許請求の
    範囲第１項記載の半導体装置の製造方法。
JP61059744A 1986-03-18 1986-03-18 半導体装置の製造方法 Expired - Fee Related JP2559700B2 (ja)

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JP61059744A JP2559700B2 (ja) 1986-03-18 1986-03-18 半導体装置の製造方法
KR1019870002404A KR900003830B1 (ko) 1986-03-18 1987-03-17 실리콘판 또는 이산화실리콘판의 접착방법
US07/027,317 US4826787A (en) 1986-03-18 1987-03-18 Method for adhesion of silicon or silicon dioxide plate
EP87103983A EP0238066B1 (en) 1986-03-18 1987-03-18 A method for effecting adhesion of silicon or silicon dioxide plates

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JP61059744A JP2559700B2 (ja) 1986-03-18 1986-03-18 半導体装置の製造方法

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JPS62216352A true JPS62216352A (ja) 1987-09-22
JP2559700B2 JP2559700B2 (ja) 1996-12-04

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JP2004512683A (ja) * 2000-10-19 2004-04-22 インターナショナル・ビジネス・マシーンズ・コーポレーション エッチ・バック法を用いた低欠陥ＳｉＧｅの層移動
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EP0238066A3 (en) 1990-03-28
KR900003830B1 (ko) 1990-06-02
KR870009463A (ko) 1987-10-26
EP0238066A2 (en) 1987-09-23
US4826787A (en) 1989-05-02
JP2559700B2 (ja) 1996-12-04
EP0238066B1 (en) 1994-05-25

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