JPS60126850A - 集積回路パツケ−ジ - Google Patents

集積回路パツケ−ジ

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Publication number
JPS60126850A
JPS60126850A JP59155643A JP15564384A JPS60126850A JP S60126850 A JPS60126850 A JP S60126850A JP 59155643 A JP59155643 A JP 59155643A JP 15564384 A JP15564384 A JP 15564384A JP S60126850 A JPS60126850 A JP S60126850A
Authority
JP
Japan
Prior art keywords
frame
lead
cavity
assembly
lead wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59155643A
Other languages
English (en)
Other versions
JPS6229908B2 (ja
Inventor
デイミイトリ・ジー・グラツベ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TE Connectivity Corp
Original Assignee
AMP Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AMP Inc filed Critical AMP Inc
Publication of JPS60126850A publication Critical patent/JPS60126850A/ja
Publication of JPS6229908B2 publication Critical patent/JPS6229908B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
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    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
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    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

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  • Physics & Mathematics (AREA)
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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Dispersion Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Casings For Electric Apparatus (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は集積回路パッケージｌこ関する。
集積回路は現在例えば時計、計算器等に広く使用されて
おり、このような回路をいわゆ゛るチップの形で容易に
かつ全自動的に実装可能な方法が必要とされている。回
路の寿命を延ばすためには製品としてのパッケージは気
体や湿気が侵入しないように密封すべきである。
本発明によれば、第１端部及び第２端部を持つ複数本の
枠状導電性リード線と、空所を画定する可塑性絶縁材料
の枠体にして、前記リード線の一部を、該リード線の第
１端部が前記空所に突入しかつ該リード線の第２端部が
当該枠体から外出するように、封入した枠体と、第１端
部及び第２端部を持つ放射状リード線を宮み、前記空所
内部で前記放射状リード線の第１端部に回路要素が装架
され、前記放射性リード緋の第２端部が前記枠状導電性
リード線の前記第１端部に固定されたスパイダ一部材と
を包言するリード枠組立体と、前記空所を両側から閉鎖
する第１及び第２の閉鎖部材とから成り、該第１及び第
２の閉鎖部材間の空間が前記回路要素を密封する絶縁性
のゲル状封止材料で充填されて水蒸気の通過を阻止する
ようになっている回路パッケージが与えられる。
本発明の実施例を以下図面を参照して説明する。
第１図を参照して、導電性リード線を枠状ｌこ形成した
もの（例えば第１１図および第１２図に（１つで示すよ
うなもの）をその供給源（ｉ）から取出して成形部門（
２）へ送り、この成形部門（２）において電気絶縁物か
らなる枠体（例えば第１１図および第１２図に＋１６）
で示すようなもの）をそｎぞｎの上ｌこ形成する。スパ
イダ一部材（例えば第３図に示すようなもの）をその供
給源（３）から取出して集積回路チップ供給源（４）か
ら取出した集積回路チップａ■とおもに装着部門（５）
へ送り、ここでチップを各スパイダ一部材上に取付けて
第４図に示すような構造をつる。ついでこのスパイダ一
部材とチップからなる組立体を装着部門（６）へ送り、
ここでこの組立体を成形部門（２）力）ら送られたリー
ド線と枠体との組立体内にそれぞｎ取付けて第６図およ
び第７図に示すような組立体をつる。ついで、このリー
ド線と、枠体と、スパイダ一部材と、研ツブと、からな
る組立体を第１の封止部門（７）へ送り、ここで閉鎖部
材０樽を（第８図Ａこ示すように）枠体（１６）にプレ
ススばめしてこ−の枠体の一側部を閉鎖する。その後、
前記組立体を第２の封止部門（８）へ送り、ここで枠体
ｕ６）内の空所α泪こ（第９図に示すように）シリコー
ンゲルのようなゲル状封止材料μ匂を充填する。
最後に組立体を第３の封止部門（９）へ送り、ここで（
第９図に示すように）第２の閉鎖部材（１８１を枠体α
ωにプレスばめしてその開放部を閉鎖すると同時にゲル
状封止材料を圧縮することによって製品としてのパッケ
ージが信頼できる密封性を有するようにする。
本発明による上述の方法の利点は、この方法が全自動的
に容易に行えることであり、別の利点は閉鎖部材を枠体
に単にプレスばめして摩僚係合させることによって枠体
内に固定することができる点である。すなわち、第１と
第３の封止部門（７）、（９）において適当な自動装置
の一動作によって閉鎖部材をはめこむことができる点で
ある。以下本発明の工程を順を追って説明する。
第２図に示すように複数個の集積回路チップ（ｌＯ）は
その周辺にそれぞれ複数個の接点バッド（１１）を有す
る。このようなチップを製造するには多くの方法がある
が公知であるのでこｎに関しては詳述しない。
第３図は′電気絶縁物のシート状体［３１によって担持
された複数個の放射状に延びるリード線αりからなるス
パイダ一部材を示す。このシート状体◇３）は窓Ｉを有
し、各リード線（１２の一端部は窓□ａ内に延び他端部
はシート状体α３）の周縁部を越えて延びている。
第４図は第３図のスパイダ一部材の窓α唱こ第２図に示
すようなチップ（１０）の１つを取付けたものを示す。
チップ（１ｏ）の接点パッド（ｌ］）はリード線（１渇
の内端部に例えば加熱または超音波のエネルギーを用い
て接続する。このような組立体は第１図の装着部門（５
）においてえられる。
第５図は複数本のリード線α０からなる枠状部材と枠体
との組立体の一部を示すもので、第１１図に示すような
完成体の一部をなすものである。すなわち、電気絶縁物
からなる枠体（１６）をリード線（１５）からなる枠状
部材上に公知の方法で成形したものでリード線（１５１
は枠体σ０の内部からこれを貫いて外方へ延びている。
リード線からなる枠状部材の余計な部分はあとで公知の
方法で除去してリード線（１句を互いに電気的に隔離し
、ついでリード線ｔｔＳを枠体←ｅによってその位置に
保持する。第５図に示すリード線と枠体とからなる組立
体は第１図の成形部門（２）ｌこおいてえられる。
第６図は第５図の組立体上に第４図に示すようなスパイ
ダ一部材とチップとの組立体を取付けたものを示す。ス
パイダ一部材のり一ドＨＮＬ”！ｒＱ＞外端部はリード
線（１５）の内端部に接続されており、チップｕ（ｌＩ
ｌは枠体α０によって画定さｎた空所（１７）内に受入
ｎられている。リードＲｕり、１１５１間の接続は熱間
圧接のような公知の方法で行なうことができる。こｎら
のリード線には金や銀のような貴金属を被着させるのが
好適である０ 第７図は第１図の装着部門（６）においてえられる第６
図に示す組立体の裏側を示す。
第８図は第７図の■−■線での断面図で第１図の部門（
７）において行われる工程を示すもＱ〕である。
電気絶縁物からなる閉鎖部材−を枠体α６）の空所αη
内にプレスばめして摩擦係合によって空所αＤ内に保持
させており、この閉鎖部材ａ町ま空所αηの一側部のみ
を閉鎖している。
第９図は閉鎖部材ｕ樟を取付けた組立体を示す。
第１図の部門（８）において空所面はシリコーンゲルの
ような分子の架橋結合度の低いゲル状封止材料ＣＰ９に
よって実質的に充填される。その後、第２の閉鎖部材ａ
８をプレスばめして空所αηの開放部を閉鎖する。この
工程は第１図の部門（９）において行われる。第２の閉
鎖部材−のプレスばめの際、封止材料（１つは圧縮され
流動して空所ａη内の全ての残っている空間に充満する
とともに両開鎖部材ａ槌の縁部と枠体１１ｅの間にも充
満してこのようにしてえられるパッケージを効果的に密
封する。
第１０図は本発明に従ってえられたパッケージ完成品を
示す。
第１１図は第１図の部門（６）において行われる工程を
示す。第１１図に示すチップｆ１０１を取付けたスパイ
ダ一部材はリード線と枠体との組立体の空所面内への挿
入に先立って帯状片ｖｅから打抜いて形成したものであ
る。
第１２図および第１３図に示すように、空所俣η内には
導電性の接地板（２１）があり、この＋にチップ（１０
）が着座している。この接地板はリード線（１５１の中
の・１本によって枠体けｅの外部に接続されている。
さらに第１３図に示すよ□うに、リード線（１５）は枠
体ｕｅ）の囲りに屈曲され、完成品である密封されたパ
ッケージ９）接続に適する接片として作用する。
上述の方法においてはただ１個のチップ（ｌＯ）を空所
面内に取付けているが、必要なら２１固０）スノくイダ
ー／チップ組立体を第１図の部門（６）で取付けこｎら
組立体のリード線ａ鴎をリード線／枠体組立体の両１１
１１１４こ接続できることはもちろんである。この場合
も空所（１７）は前述のようにして閉鎖し密封する。
そのようなパッケージを第１４図に示す。第１４図では
接地板（２１）は両チップ（１０）の間にあるものとし
て図示されている。
閉鎖部材（１８）は絶縁物としたが導電性のものでもよ
い。この導電性閉鎖部材は第１３図に示す組立体の下側
の閉鎖部材（１８）として用いた場合特に有利である。
【図面の簡単な説明】
第１図は本発明の方法を例示するブロック図、第２図は
集積回路チップからなるシート状体の平面図、第３図は
チップを取付けるのに用Ｇ）るスパイダ一部材の平面図
５、第４図は第３図のスパイダ一部材上ζこチップを取
付けたものを示す図、第５図は絶縁物からなる枠体をそ
の上に成形した複数本の導電性リード線の平面図、第６
図は第５図の枠体上に第４図のスパイダー／チップ組立
体を取付けたものを示す図、゛第７図は第６図の反対側
を示す図、第８図、第９図および第１０図は第７図の■
−■線での断面図で本発明の方法の工程を示す、第１１
図は第５図のリード線／枠体組立体とその上ｌこ取付け
るスパイダー／チップ組立体の斜視図、第１２図は第１
１図の組立構造体を一部切欠して示す斜視図、第１３図
は本発明によって製造さｎた第１のパッケージの断面図
、第１４図は本発明によって製造さｎた第２のパッケー
ジの断面図である。 １０・・・集積回路チップ １２・・・放射状リード線（スパイダ一部材）１３・・
・電気絶縁物のシート状体 １５・・・導電性リード線 １６・・・電気絶縁物の枠体 １７・・・空所 １８・・・閉鎖部材 １９・・・封止材料

Claims (1)

  1. 【特許請求の範囲】 第１端部及び第２端部を持つ複数本の枠状導電性リード
    線と、 空所を画定する可塑性絶縁材料の枠体にして、前記リー
    ド線の一部を、該リード線の第１端部が前記空所に突入
    しかつ該リード線の第２端部が当該枠体から外出するよ
    うに、封入した枠体と、第１端部及び第２端部を持つ放
    射状リード＃！を含み、前記空所内部で前記放射状リー
    ド縁の第１端部に回路要素が装架され、前記放射性リー
    ド線の第２端部が前記枠状導電性リード線の前記第１端
    部に固定されたスパイダ一部材と を包含するリード枠組立体と、 前記空所を両側から閉鎖する第１及び第２の閉鎖部材と
    から成り、該第１及び第２の閉鎖部材間の空間が前記回
    路要素を密封する絶縁性のゲル状封止材料で充填さｎた
    水蒸気の通過を阻止するようになっている回路パッケー
    ジ。
JP59155643A 1976-07-30 1984-07-27 集積回路パツケ−ジ Granted JPS60126850A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/710,043 US4079511A (en) 1976-07-30 1976-07-30 Method for packaging hermetically sealed integrated circuit chips on lead frames
US710043 1985-03-11

Publications (2)

Publication Number Publication Date
JPS60126850A true JPS60126850A (ja) 1985-07-06
JPS6229908B2 JPS6229908B2 (ja) 1987-06-29

Family

ID=24852388

Family Applications (2)

Application Number Title Priority Date Filing Date
JP8989177A Granted JPS5317276A (en) 1976-07-30 1977-07-28 Integrated circuit package and method of manufacture thereof
JP59155643A Granted JPS60126850A (ja) 1976-07-30 1984-07-27 集積回路パツケ−ジ

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP8989177A Granted JPS5317276A (en) 1976-07-30 1977-07-28 Integrated circuit package and method of manufacture thereof

Country Status (12)

Country Link
US (1) US4079511A (ja)
JP (2) JPS5317276A (ja)
BE (1) BE857125A (ja)
BR (1) BR7704965A (ja)
CA (1) CA1069220A (ja)
DE (1) DE2734439A1 (ja)
ES (2) ES461133A1 (ja)
FR (1) FR2360174A1 (ja)
GB (1) GB1524776A (ja)
IT (1) IT1080619B (ja)
NL (1) NL7707424A (ja)
SE (1) SE423846B (ja)

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Also Published As

Publication number Publication date
SE7708156L (sv) 1978-01-31
SE423846B (sv) 1982-06-07
FR2360174B1 (ja) 1983-01-21
BE857125A (fr) 1978-01-25
US4079511A (en) 1978-03-21
JPS6229908B2 (ja) 1987-06-29
DE2734439A1 (de) 1978-02-02
ES461133A1 (es) 1978-06-01
ES462978A1 (es) 1978-06-01
CA1069220A (en) 1980-01-01
JPS5317276A (en) 1978-02-17
NL7707424A (nl) 1978-02-01
IT1080619B (it) 1985-05-16
BR7704965A (pt) 1978-04-25
JPS6143851B2 (ja) 1986-09-30
DE2734439C2 (ja) 1988-08-25
GB1524776A (en) 1978-09-13
FR2360174A1 (fr) 1978-02-24

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