KR960000706B1 - 전력소자용 플라스틱 패키지 구조 및 그 제조방법 - Google Patents

전력소자용 플라스틱 패키지 구조 및 그 제조방법 Download PDF

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Publication number
KR960000706B1
KR960000706B1 KR1019930013085A KR930013085A KR960000706B1 KR 960000706 B1 KR960000706 B1 KR 960000706B1 KR 1019930013085 A KR1019930013085 A KR 1019930013085A KR 930013085 A KR930013085 A KR 930013085A KR 960000706 B1 KR960000706 B1 KR 960000706B1
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South Korea
Prior art keywords
power device
lead
device chip
lead frame
paddle
Prior art date
Application number
KR1019930013085A
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English (en)
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KR950004507A (ko
Inventor
김동구
송민규
박성수
김승구
윤형진
박형무
Original Assignee
한국전기통신공사
조백제
재단법인한국전자통신연구소
양승택
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Application filed by 한국전기통신공사, 조백제, 재단법인한국전자통신연구소, 양승택 filed Critical 한국전기통신공사
Priority to KR1019930013085A priority Critical patent/KR960000706B1/ko
Priority to US08/268,104 priority patent/US5446959A/en
Priority to GB9413867A priority patent/GB2280062B/en
Priority to FR9408824A priority patent/FR2707798B1/fr
Priority to DE4424549A priority patent/DE4424549C2/de
Priority to JP6159894A priority patent/JP2560205B2/ja
Priority to US08/381,304 priority patent/US5612853A/en
Publication of KR950004507A publication Critical patent/KR950004507A/ko
Application granted granted Critical
Publication of KR960000706B1 publication Critical patent/KR960000706B1/ko

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Abstract

내용 없음.

Description

전력소자용 플라스틱 패키지 구조 및 그 제조방법
제1도는 본 발명에 따른 리드프레임의 평면도.
제2도는 본 발명의 (a) 내지 (g)공정에 대한 설명도.
* 도면의 주요부분에 대한 부호의 설명
1 : 리드프레임 2 : 패들
3 : 게이트 전극용 리드 4 : 드레인 전극용 리드
5, 6 : 소오스 전극용 리드 7 : 방열판
8 : 코바르(Kovar) 기판 9 : 전력소자 칩
10 : 본딩 와이어 11 : 금속 캡(cap)
12 : 플라스틱 몰딩
본 발명은 반도체 패키지 구조 및 그 제조방법에 관한 것으로, 특히 전력소자용 플라스틱 패키지(package)의 구조 및 그 제조방법에 관한 것이다.
종래의 전력소자 패키지는 저 전력용 소자 패키지(소비전력 0.5W 이하)인 경우 통상적으로 플라스틱 패키지를 사용하고 있으나, 소비전력이 0.5W인 경우에는 세라믹 기판과 금속프레임을 사용하여 전력소자에서 발생되는 열이 금속프레임과 방열판을 통하여 발산하도록 제조되었기 때문에 반도체 제조공정이 복잡하고 제작단가가 높은 것이 특징이었다.
이런 상기의 플라스틱 패키지에서 종종 발생되는 결함으로는 반도칩과 봉지제와의 경계를 이루는 면에서의 박리현상 및 봉지제에 의한 내부응력에서 오는 균열문제를 들 수 있고, 또한 고주파 특성이 열악하다는 문제를 들 수 있다.
이에 따라, 위의 고주파 특성의 향상을 위해서 패키지 자체의 노이즈 차폐(noise shielding)를 위한 하부 세라믹 부분의 측면에 금속증착과 금속 뚜껑을 사용해야 하는 제조공정의 복잡성과 제조비용이 높아지는 또다른 문제점들이 있다.
또한, 종래의 세라믹 패키지에서 발생되는 고주파 신호에 의한 동조(resonance)를 방지하기 위해 최근 개발된 금속 프레임(frame)형 패키지는 전기적 성능은 향상되었으나 가동하기가 어려운 문제를 가지고 있다.
한편, 고주파용 전력소자인 경우에는 전력이득 및 잡음지수가 영향을 미치므로 고주파 성능향상을 위한 임피던스 정합이 고려된 다층 세라믹 패키지가 최근 개발되고 있다.
따라서. 상기의 문제점들을 개선하기 위하여 본 발명에서는. 고주파용 전력소자를 제조함에 있어서 인피던스 정합을 고려한 리드프레임을 사용하고 종래의 플라스틱 패키지 제조공정을 그대로 사용하는 전력소자용 플라스틱 패키지의 구조 및 그 제조방법을 제공하는데 목적이 있다.
상기 목적을 달성하기 위하여, 본 발명에서는 도면을 참조하면서 상세히 설명한다.
먼저, 제1도는 전력소자용 리드프레임을 이용한 간단한 제조방법을 설명한다.
종래에 리드프레임(1)의 각 리드를 임피던스 정합을 고려하여 제작하고, 타이 바(tie bar)에 위치한 소오스 전극용 리드(5,6)와 게이트 및 드레인 전극용 리드(3,4)를 포함한 다핀(4∼20핀) 리드프레임을 이용하여 전력소자의 상기 게이트(3), 드레인(4) 전극들을 양쪽 리드에 와이어(wire) 본딩(bonding)한다.
그리고, 소오스(5,6) 전극들은 패들(paddle)(2)에 와이어 본딩시켜 타이바를 통해 접지시키며, 동시에 금속 캡(cap)을 전력소자 위에 놓아 패들(2)과 전기적 연결을 통해 전력소자 전체의 노이즈를 차폐함으로써, 고주파 특성을 향상시키는 동시에 발열되는 전력소자 표면과 에폭시와의 반응을 방지시킨다.
또한, 리드프레임(1)과 갈륨비소 전력소자 칩 사이에 코바르 기판을 삽입함으로써 갈륨비소 전력소자 칩과 리드프레임(1)의 열팽창계수 차이로부터 발생되는 응력을 제거한다. 특히, 방열판을 리드프레임(1)에 부착함으로써 전력소자로부터 발생되는 열을 제거하는 1 내지 3w급의 전력소자용 플라스틱 패키지 제조방법을 제공한다.
상기에 따른 공정들의 도면인 제2도를 참조하여 더욱 상세히 설명하는데 있어서, (D)공정, (E)공정, (G)공정의 리드프레임(1)으로부터 좌측의 단면도는 중심부를 자른 부분에서 본 종단면도이고, 우측의 단면도는 중심부를 자른 부분에서 본 횡단면도를 나타낸다.
제2도는, (a)공정은 클래딩(cladding) 방법에 의해 방열판(7) 상부에 리드프레임(1) 상면보다 상대적으로 낮은 위치에 연결되어 있는 패들(2)을 접합하는데 이때, 이 방열판(7) 재료는 구리(Cu)를 이용한다.
(b)공정은 납땜(soldering) 방법에 의해 갈륨비소(GaAs) 칩과 리드프레임(1) 사이의 열팽창 계수 차이로부터 발생되는 열응력제거를 위해 리드프레임(1) 상부에 코바르(Kovar) 기판(8)을 부착하는데 이때, 공정온도는 290 내지 310℃, 땜납은 납, 인듐, 은의 비율이 92.5 : 5 : 2.5로 된 합금을 사용한다. (c)공정은 반도체 칩을 기판 또는 패키지에 접착시키는 다이본딩(die bonding)공정으로서 납땜방법에 의해 갈륨비소 전력소자 칩(9)을 코바르 기판(8) 위에 접착하는데 이때, 공정온도는 280 내지 290℃이며. 다이본더(die bonder, 즉, 칩 접합제)는 금,주석의 비율이 80 : 20로 된 합금을 사용한다. (d)공정은 와이어 본딩 공정으로서 전력소자 칩(9)의 게이트 전극을 게이트 전극용 리드(3)에, 드레인 전극을 드레인 전극용 리드(4)에 각각 와이어(10) 본딩하고, 소오스 전극을 소오스 전극용 리드(5,6)들이 있는 리드프레임 패들(2)에 와이어(10) 본딩함으로써 접지시키고, 상기 게이트 전극용 리드(3)와 상기 드레인 전극용 리드(4)는 냉각핀인 소오스 전극용 리드(5,6)들과는 상대적으로 반대쪽으로 굽혀서 칩이 칩다운(chip down)되도록 한 횡단면도처럼 인쇄회로 기판에 표면실장형으로 가공하고, 플라스틱 몰딩시 상기 전력소자칩(9)을 도포하기 위해서 이 전력소자 칩(9)과 에폭시와의 반응을 피하는데에 있어서 미리 이미드화된(pre-imidized) 저온용 폴리이미드(polyimide)를 사용하는 스핀(spin) 방법이 있다.
이때의 조건은 스핀속도 3000rpm, 도포두께 5μm, 큐어링(curing) 온도 220℃에서 열처리를 한다.
(e)공정은 금속 캡(11) 부착 공정으로서 납땜방법으로 금속 캡(11)을 상기 리드프레임 패들(2) 전력소자 칩(9) 상부에 부착한다.
이때 공정온도는 240 내지 250℃, 땜납은 주석, 안티몬의 비율이 95 : 5로 된 합금을 사용하고, 상기 (d)공정에서 리드프레임 패들(2)에 와이어 본딩된 상기 소오스 전극과 금속 캡 (11)이 전기적으로 함께 접지됨으로써, 임피던스 정합을 고려한 리드프레임(1)과 함께 전력소자 칩(9)의 고주파 특성을 향상시킨다.
(f)공정은 플라스틱 몰딩(molding)(12)공정으로 금형을 사용하여 에폭시 몰딩을 행한 후 175 내지 200℃에서 열처리를 행한다.
(g)공정은 상기에서 기술한 공정들에 의해 완성된 4개(3,4,5,6) 리드가 있는 리드프레임(1)을 이용한 전력소자용 플라스틱 패키지의 최종 공정으로 구성되는 것을 포함한다. 이상과 같은 공정들에 의해서, 본 발명은 임피던스 정합을 고려한 리드프레임(1)을 이용한 전력소자용 패키지를 플라스틱 몰딩 방식으로 제조함으로써, 종래의 플라스틱 패키지 제조공정을 그대로 사용할 수 있도록 하고. 세라믹 전력소자용 패키지의 제조단가를 낮추도록 한다.
또한, 금속 캡(11)을 사용하여 노이즈를 차폐함으로써 전력소자의 특성 향상을 꾀할 수 있으며, 와이어 본딩 후 폴리이미드를 도포하여서 플라스틱 패키지의 신뢰성을 향상시키고, 공정의 단순화를 한 효과가 있다.

Claims (7)

  1. 방열판(7) 상부에 접착되는 4개의 리드를 가진 리드프레임(1)의 면보다 상대적으로 낮은 위치에 연결된 패들(2)과, 상기 패들(2) 상부에 부착되는 코바르 기판(8)과, 상기 코바르 기판(8) 상부에 접착되는 전력소자 칩(9)과, 상기 전력소자 칩(9)의 게이트 전극이 게이트 전극용 리드(3)에, 드레인 전극이 드레인 전극용 리드(4)에 각각 접속되고, 소오스 전극이 리드프레임 패들(2)에 접속되는 본딩 와이어(10)와, 상기 리드프레임 패들(2) 위에 부착되는 금속 캡(11)과, 상기 금속 캡(11) 및 상기 본딩 와이어(10)를 플라스틱으로 덮는 것을 특징으로 하는 전력소자용 플라스틱 패키지 구조.
  2. 제1항에 있어서, 상기 패들(2)은 양측에 타이바가 있고, 이 타이바는 전력소자 칩(9)의 소오스 전극용 리드(5,6)들로서 사용되는 것을 특징으로 하는 전력소자용 플라스틱 패키지 구조.
  3. 제1항에 있어서, 상기 4개의 리드는 상기의 게이트 전극용 리드(3) 및 상기의 드레인 전극용 리드(4)와 두개의 소오스 전극용 리드(5,6)들이 포함되되, 상기 게이트 전극용 리드(3)와 상기 드레인 전극용 리드(4)는 냉각 핀인 상기 두개의 소오스 전극용 리드(5,6)들과 반대편으로 굽혀지는 것을 특징으로 하는 전력소자용 플라스틱 패키지 구조.
  4. 전력소자 칩(9)의 방열을 위해 리드프레임(1) 상부에 방열판(7)이 부착되는 (a)공정과. 상기 리드프레임(1) 상부에 갈륨비소 전력소자 칩(9)과 리드프레임(1)의 열팽창계수 차이로부터 발생되는 열응력을 제거하기 위해 코바르 기판(8)이 부착되는(b)공정과, 상기 코바르 기관(8) 상부에 갈륨비소 전력소자 칩(9)이 접착되는 (c)공정과, 상기 전력소자 칩(9)의 전극들을 리드프레임(1)의 리드에 와이어(10)본딩하고, 이 전력소자 칩(9)이 에폭시와 반응되지 않도록 하기 위한 저온용 폴리이미드를 스핀에 의해서 전력소자 칩(9)에 도포하는 (d)공정과, 상기 리드프레임(1)의 리드를 임피던스가 정합되도록 하고, 상기 전력소자 칩 (9) 상부에 노이즈를 차폐하기 위한 금속 캡(11)이 부착되는 (e)공정과, 상기 금속 캡(11)을 에폭시를 이용하여 플라스틱 몰딩하는 (f)공정을 포함하는 것을 특징으로 하는 전력소자용 플라스틱 패키지 제조방법.
  5. 제4항에 있이서, 상기 코바르 기판(8)은 310 내지 320℃에서 납, 인듐은 비율이 9.25 : 5 : 2.5로 된 합금이 사용되어 부착되는 것을 특징으로 하는 전력소자용 패키지 제조방법.
  6. 제4항에 있어서, 상기 (d)공정에서 상기 저온용 폴리아미드는 3000rpm의 스핀속도, 5μm의 도포두께, 220℃ 온도에서 큐어링 되는 것을 특징으로 하는 전력소자용 플라스틱 패키지 제조방법.
  7. 제4항에 있어서, 상기 금속 캡(11)은 240 내지 250℃에서 주석, 안티몬의 비율이 95 : 5로 된 합금이 사용되어 부착되는 것을 특징으로 하는 전력소자용 플라스틱 패키지 제조방법.
KR1019930013085A 1993-07-12 1993-07-12 전력소자용 플라스틱 패키지 구조 및 그 제조방법 KR960000706B1 (ko)

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KR1019930013085A KR960000706B1 (ko) 1993-07-12 1993-07-12 전력소자용 플라스틱 패키지 구조 및 그 제조방법
US08/268,104 US5446959A (en) 1993-07-12 1994-07-06 Method of packaging a power semiconductor device
GB9413867A GB2280062B (en) 1993-07-12 1994-07-08 Method of packaging a power semiconductor device and package produced by the method
FR9408824A FR2707798B1 (fr) 1993-07-12 1994-07-11 Procédé d'encapsulation d'un dispositif à semi-conducteurs de puissance et encapsulage fabriqué selon ce procédé.
DE4424549A DE4424549C2 (de) 1993-07-12 1994-07-12 Verfahren zum Gehäusen eines Leistungshalbleiterbauelements und durch dieses Verfahren hergestelltes Gehäuse
JP6159894A JP2560205B2 (ja) 1993-07-12 1994-07-12 電力素子用プラスチックパッケージ構造及びその組立方法
US08/381,304 US5612853A (en) 1993-07-12 1995-01-31 Package for a power semiconductor device

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US5612853A (en) 1997-03-18
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DE4424549A1 (de) 1995-01-19
DE4424549C2 (de) 1996-10-17
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US5446959A (en) 1995-09-05
FR2707798B1 (fr) 1996-06-14

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