JPH08330434A - 半導体集積回路装置およびその配置配線方法並びにレイアウト方法 - Google Patents

半導体集積回路装置およびその配置配線方法並びにレイアウト方法

Info

Publication number
JPH08330434A
JPH08330434A JP7220877A JP22087795A JPH08330434A JP H08330434 A JPH08330434 A JP H08330434A JP 7220877 A JP7220877 A JP 7220877A JP 22087795 A JP22087795 A JP 22087795A JP H08330434 A JPH08330434 A JP H08330434A
Authority
JP
Japan
Prior art keywords
wiring
region
functional circuit
cell
passage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7220877A
Other languages
English (en)
Japanese (ja)
Other versions
JPH08330434A5 (enExample
Inventor
Hideto Hidaka
秀人 日高
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7220877A priority Critical patent/JPH08330434A/ja
Publication of JPH08330434A publication Critical patent/JPH08330434A/ja
Priority to US08/868,046 priority patent/US5880493A/en
Priority to US09/241,079 priority patent/US6100550A/en
Publication of JPH08330434A5 publication Critical patent/JPH08330434A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP7220877A 1994-12-09 1995-08-29 半導体集積回路装置およびその配置配線方法並びにレイアウト方法 Pending JPH08330434A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP7220877A JPH08330434A (ja) 1994-12-09 1995-08-29 半導体集積回路装置およびその配置配線方法並びにレイアウト方法
US08/868,046 US5880493A (en) 1994-12-09 1997-06-03 Semiconductor integrated circuit devices adapted for automatic design and method of arranging such devices
US09/241,079 US6100550A (en) 1994-12-09 1999-02-01 Circuit cell based semiconductor integrated circuit device and method of arrangement-interconnection therefor

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP6-306409 1994-12-09
JP30640994 1994-12-09
JP7-71930 1995-03-29
JP7193095 1995-03-29
JP7220877A JPH08330434A (ja) 1994-12-09 1995-08-29 半導体集積回路装置およびその配置配線方法並びにレイアウト方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2005240178A Division JP2006032981A (ja) 1994-12-09 2005-08-22 半導体集積回路装置およびその配置配線方法

Publications (2)

Publication Number Publication Date
JPH08330434A true JPH08330434A (ja) 1996-12-13
JPH08330434A5 JPH08330434A5 (enExample) 2005-11-04

Family

ID=27300809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7220877A Pending JPH08330434A (ja) 1994-12-09 1995-08-29 半導体集積回路装置およびその配置配線方法並びにレイアウト方法

Country Status (2)

Country Link
US (2) US5880493A (enExample)
JP (1) JPH08330434A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013026245A (ja) * 2011-07-15 2013-02-04 Fujitsu Semiconductor Ltd 配線パターンデータの生成方法
JP2020057679A (ja) * 2018-10-01 2020-04-09 ルネサスエレクトロニクス株式会社 半導体装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000077609A (ja) * 1998-08-28 2000-03-14 Hitachi Ltd 半導体集積回路装置
JP3349989B2 (ja) * 1999-06-18 2002-11-25 エヌイーシーマイクロシステム株式会社 半導体集積回路装置及びそのレイアウト方法及び装置
JP4008629B2 (ja) * 1999-09-10 2007-11-14 株式会社東芝 半導体装置、その設計方法、及びその設計プログラムを格納したコンピュータ読み取り可能な記録媒体
US6528735B1 (en) 2001-09-07 2003-03-04 International Business Machines Corporation Substrate design of a chip using a generic substrate design
US7698681B2 (en) * 2007-08-14 2010-04-13 International Business Machines Corporation Method for radiation tolerance by logic book folding
US7725870B2 (en) * 2007-08-14 2010-05-25 International Business Machines Corporation Method for radiation tolerance by implant well notching
JP5741234B2 (ja) * 2011-06-10 2015-07-01 富士通株式会社 セルの配置構造、半導体集積回路、及び回路素子セルの配置方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197747A (ja) * 1982-05-14 1983-11-17 Hitachi Ltd マスタスライスｌｓｉ
JPS58200570A (ja) * 1982-05-19 1983-11-22 Hitachi Ltd 半導体集積回路装置
EP0154346B1 (en) * 1984-03-08 1991-09-18 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device
JPH0644593B2 (ja) * 1984-11-09 1994-06-08 株式会社東芝 半導体集積回路装置
JPS61240652A (ja) * 1985-04-18 1986-10-25 Toshiba Corp 半導体集積回路装置
JP2606845B2 (ja) * 1987-06-19 1997-05-07 富士通株式会社 半導体集積回路
JP2529342B2 (ja) * 1988-03-14 1996-08-28 富士通株式会社 チャネル配線方法
JP2580301B2 (ja) * 1988-12-27 1997-02-12 株式会社日立製作所 半導体集積回路装置
JPH03255665A (ja) * 1990-03-06 1991-11-14 Nissan Motor Co Ltd 半導体集積回路装置
EP0466463A1 (en) * 1990-07-10 1992-01-15 Kawasaki Steel Corporation Basic cell and arrangement structure thereof
JPH04340252A (ja) * 1990-07-27 1992-11-26 Mitsubishi Electric Corp 半導体集積回路装置及びセルの配置配線方法
JP2894814B2 (ja) * 1990-09-28 1999-05-24 株式会社東芝 スタンダード・セル方式の半導体集積回路
JP3061928B2 (ja) * 1992-03-30 2000-07-10 日本電気株式会社 半導体装置
US5384472A (en) * 1992-06-10 1995-01-24 Aspec Technology, Inc. Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density
US5452245A (en) * 1993-09-07 1995-09-19 Motorola, Inc. Memory efficient gate array cell
US5416431A (en) * 1994-03-21 1995-05-16 At&T Corp. Integrated circuit clock driver having improved layout

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013026245A (ja) * 2011-07-15 2013-02-04 Fujitsu Semiconductor Ltd 配線パターンデータの生成方法
JP2020057679A (ja) * 2018-10-01 2020-04-09 ルネサスエレクトロニクス株式会社 半導体装置

Also Published As

Publication number Publication date
US5880493A (en) 1999-03-09
US6100550A (en) 2000-08-08

Similar Documents

Publication Publication Date Title
JP4287294B2 (ja) 自動設計方法、自動設計装置、及び半導体集積回路
KR102593720B1 (ko) 집적회로 설계 및/또는 제조
CN108281419B (zh) 无传输门的电路单元以及包括该单元的集成电路布局
US6035111A (en) Manufacturing method and apparatus of a semiconductor integrated circuit device
JPH08330434A (ja) 半導体集積回路装置およびその配置配線方法並びにレイアウト方法
JP2001127161A (ja) 集積回路
KR20170063410A (ko) 파워 혼 및 스마크 금속 절단부를 가진 표준-셀 레이아웃 구조물
JPH10335612A (ja) 高密度ゲートアレイセル構造およびその製造方法
JP2019114641A (ja) 半導体装置
US6675361B1 (en) Method of constructing an integrated circuit comprising an embedded macro
CN114487796B (zh) 一种测试芯片中外围电路的设计方法及其测试芯片
US20040005738A1 (en) Sea-of-cells array of transistors
US11239228B2 (en) Integrated circuit layout and method of configuring the same
EP0290672B1 (en) A semiconductor integrated circuit device
JPS5969948A (ja) マスタ−スライス型半導体集積回路
JP2009289797A (ja) 半導体装置
US8178904B2 (en) Gate array
JP2008078508A (ja) 半導体集積回路及び半導体集積回路の製造方法
JP2006032981A (ja) 半導体集積回路装置およびその配置配線方法
US12255140B2 (en) Semiconductor device and layout method of the same
CN112100967A (zh) 一种标准单元版图、标准单元库版图及布线方法
JP2005197518A (ja) 半導体装置とセル
JP5503168B2 (ja) 半導体集積回路装置
JP2017037920A (ja) セルライブラリ及び設計用データ
KR20020042507A (ko) 반도체장치, 그 제조방법 및 기억매체

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050822

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060728

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060829

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20070109