JPH0574927A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPH0574927A
JPH0574927A JP3234195A JP23419591A JPH0574927A JP H0574927 A JPH0574927 A JP H0574927A JP 3234195 A JP3234195 A JP 3234195A JP 23419591 A JP23419591 A JP 23419591A JP H0574927 A JPH0574927 A JP H0574927A
Authority
JP
Japan
Prior art keywords
film
bpsg
groove
semiconductor substrate
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3234195A
Other languages
English (en)
Japanese (ja)
Inventor
Shinya Nishio
信哉 西尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3234195A priority Critical patent/JPH0574927A/ja
Priority to US07/942,290 priority patent/US5229317A/en
Priority to EP92308324A priority patent/EP0532361B1/en
Priority to DE69231653T priority patent/DE69231653T2/de
Publication of JPH0574927A publication Critical patent/JPH0574927A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0128—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising multiple local oxidation process steps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective

Landscapes

  • Element Separation (AREA)
JP3234195A 1991-09-13 1991-09-13 半導体装置の製造方法 Pending JPH0574927A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP3234195A JPH0574927A (ja) 1991-09-13 1991-09-13 半導体装置の製造方法
US07/942,290 US5229317A (en) 1991-09-13 1992-09-09 Method for preventing out-diffusion of phosphorous and boron in a bpsg-buried trench
EP92308324A EP0532361B1 (en) 1991-09-13 1992-09-14 Method of manufacturing semiconductor device
DE69231653T DE69231653T2 (de) 1991-09-13 1992-09-14 Verfahren zur Herstellung einer Halbleiteranordnung mit Isolierzonen

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3234195A JPH0574927A (ja) 1991-09-13 1991-09-13 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPH0574927A true JPH0574927A (ja) 1993-03-26

Family

ID=16967175

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3234195A Pending JPH0574927A (ja) 1991-09-13 1991-09-13 半導体装置の製造方法

Country Status (4)

Country Link
US (1) US5229317A (enExample)
EP (1) EP0532361B1 (enExample)
JP (1) JPH0574927A (enExample)
DE (1) DE69231653T2 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0745694A (ja) * 1993-07-26 1995-02-14 Nec Corp 半導体装置およびその製造方法
US5399516A (en) * 1992-03-12 1995-03-21 International Business Machines Corporation Method of making shadow RAM cell having a shallow trench EEPROM
JPH0831926A (ja) * 1994-07-15 1996-02-02 Nec Corp 半導体装置の製造方法
JP2009539105A (ja) * 2006-05-31 2009-11-12 エージェンシー フォー サイエンス，テクノロジー アンド リサーチ 透明なマイクロ流体デバイス

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2768106B2 (ja) * 1992-01-28 1998-06-25 三菱自動車工業株式会社 液圧パワーステアリング用圧力センサの零圧値補正方法
US5433794A (en) * 1992-12-10 1995-07-18 Micron Technology, Inc. Spacers used to form isolation trenches with improved corners
FR2717306B1 (fr) * 1994-03-11 1996-07-19 Maryse Paoli Procédé d'isolement de zones actives d'un substrat semi-conducteur par tranchées peu profondes, notamment étroites, et dispositif correspondant.
US5447884A (en) * 1994-06-29 1995-09-05 International Business Machines Corporation Shallow trench isolation with thin nitride liner
US5495476A (en) * 1995-01-26 1996-02-27 International Business Machines Corporation Parallel algorithm to set up benes switch; trading bandwidth for set up time
KR0147630B1 (ko) * 1995-04-21 1998-11-02 김광호 반도체 장치의 소자분리방법
KR100338767B1 (ko) * 1999-10-12 2002-05-30 윤종용 트렌치 소자분리 구조와 이를 갖는 반도체 소자 및 트렌치 소자분리 방법
US6861334B2 (en) * 2001-06-21 2005-03-01 Asm International, N.V. Method of fabricating trench isolation structures for integrated circuits using atomic layer deposition
US6890833B2 (en) * 2003-03-26 2005-05-10 Infineon Technologies Ag Trench isolation employing a doped oxide trench fill
DE10348021A1 (de) * 2003-10-15 2005-05-25 Infineon Technologies Ag Verfahren zur Herstellung einer Halbleiterstruktur mit einer Einkapselung einer Füllung, welche zum Anfüllen von Gräben verwendet wird
CN108168743B (zh) * 2017-12-20 2024-08-27 南京方旭智芯微电子科技有限公司 压力传感器及制造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4506435A (en) * 1981-07-27 1985-03-26 International Business Machines Corporation Method for forming recessed isolated regions
JPS59106133A (ja) * 1982-12-09 1984-06-19 Nec Corp 集積回路装置
JPS59119848A (ja) * 1982-12-27 1984-07-11 Fujitsu Ltd 半導体装置の製造方法
JPS6020530A (ja) * 1983-07-14 1985-02-01 Nec Corp 素子分離領域の形成方法
JPS618945A (ja) * 1984-06-25 1986-01-16 Nec Corp 半導体集積回路装置
JPH077794B2 (ja) * 1984-07-11 1995-01-30 株式会社日立製作所 半導体集積回路装置の製造方法
US4571819A (en) * 1984-11-01 1986-02-25 Ncr Corporation Method for forming trench isolation structures
SE8603126L (sv) * 1985-08-05 1987-02-06 Rca Corp Cmos-integrerad krets och metod att tillverka en sadan
FR2598557B1 (fr) * 1986-05-09 1990-03-30 Seiko Epson Corp Procede de fabrication d'une region d'isolation d'element d'un dispositif a semi-conducteurs
JPH023349A (ja) * 1988-06-17 1990-01-08 Nec Corp 感熱紙自動濃度制御方式
JPH082848B2 (ja) * 1988-06-20 1996-01-17 東レ株式会社 ４−ニトロソジフェニルアミン類の製造法
JPH0215650A (ja) * 1988-07-01 1990-01-19 Nec Corp 半導体装置及びその製造方法
JPH0258439A (ja) * 1988-08-24 1990-02-27 Fujitsu Ltd 多重光伝送装置の障害点識別方式
US5306940A (en) * 1990-10-22 1994-04-26 Nec Corporation Semiconductor device including a locos type field oxide film and a U trench penetrating the locos film
JP2815255B2 (ja) * 1991-08-26 1998-10-27 シャープ株式会社 半導体装置の製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399516A (en) * 1992-03-12 1995-03-21 International Business Machines Corporation Method of making shadow RAM cell having a shallow trench EEPROM
JPH0745694A (ja) * 1993-07-26 1995-02-14 Nec Corp 半導体装置およびその製造方法
JPH0831926A (ja) * 1994-07-15 1996-02-02 Nec Corp 半導体装置の製造方法
JP2009539105A (ja) * 2006-05-31 2009-11-12 エージェンシー フォー サイエンス，テクノロジー アンド リサーチ 透明なマイクロ流体デバイス

Also Published As

Publication number Publication date
EP0532361A3 (enExample) 1995-03-22
EP0532361B1 (en) 2001-01-24
DE69231653T2 (de) 2001-05-03
US5229317A (en) 1993-07-20
DE69231653D1 (de) 2001-03-01
EP0532361A2 (en) 1993-03-17

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