JPH0569292B2 - - Google Patents

Info

Publication number
JPH0569292B2
JPH0569292B2 JP60103652A JP10365285A JPH0569292B2 JP H0569292 B2 JPH0569292 B2 JP H0569292B2 JP 60103652 A JP60103652 A JP 60103652A JP 10365285 A JP10365285 A JP 10365285A JP H0569292 B2 JPH0569292 B2 JP H0569292B2
Authority
JP
Japan
Prior art keywords
recess
layer
photoresist
metal
photoresist layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60103652A
Other languages
English (en)
Other versions
JPS6144470A (ja
Inventor
Andrew L Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of JPS6144470A publication Critical patent/JPS6144470A/ja
Publication of JPH0569292B2 publication Critical patent/JPH0569292B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/105—Masks, metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/945—Special, e.g. metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、集積回路チツプの凹所に金属を充填
する方法に関する。
従来の技術 集積回路チツプを処理する際には、例えば、酸
化物層のような絶縁材の凹所に金属導体物質を充
填することがしばしば必要となる。米国特許第
4617193号明細書には、このような処理を行うた
めの方法が開示されている。簡単に述べると、チ
ツプの表面に金属フイルムが付与される。このフ
イルムの深さは、少なくとも絶縁材の凹所を充填
し且つ金属フイルムの上表面に凹所を残すに十分
なものである。金属フイルム上にホトレジスト被
膜を設けて金属フイルムの凹所を充填し平らな上
表面を形成する。次いで、このホトレジスト被膜
を反応性イオンエツチング方法によつてエツチン
グし、金属フイルムの凹所にホトレジストを残す
ようにする。次いで、金属をエツチングし、凹所
の外側の金属を除去する。その後、残りのホトレ
ジストを除去し、凹所に金属を残すようにする。
この方法は、一般に、一様な巾の凹所を有するチ
ツプにおける10ミクロン以下の巾を有する凹所を
充填する場合に限定される。
発明が解決しようとする問題点 本発明は、凹所の巾が著しく変化したり、ある
いは凹所の巾が約10ミクロン以上の場合であつて
も、金属と凹所の間に不所望なギヤツプ等を形成
することなく、その凹所を金属によつて満足に充
填する方法を提供する。
問題点を解決するための手段 本発明の特徴によれば、絶縁材の凹所に金属フ
イルムを充填する新規で且つ改良された方法が提
供される。凹所を形成すべき絶縁材の領域は、ホ
トレジストによつて定められ、その領域が凹所を
形成すべくエツチングされるのであるが、このと
き、ホトレジストがその凹所に若干張り出すよう
にされる。次いで、その凹所に充填するように、
少なくともその凹所とその周囲のホトレジストの
前面にわたつて金属フイルムを冷間スパツタリン
グする。この状態においては、その金属は、ホト
レジストの上表面及び張り出し部の境界を定める
ホトレジストの側面をも覆つている。ホトレジス
トの側面を覆つている金属は、凹所に付与された
金属とは分離されている。次いで、金属の表面
を、例えば、ホトレジストの層で覆う。このホト
レジスト層は、部分的にエツチング除去され、そ
の下のホトレジスト層の角部付近の金属の縁が露
出するようにする。次いで、その露出された金属
をエツチング除去し、その下のホトレジストの角
部を露出させる。次いで、下方のホトレジスト層
を除去し、これにより、それを覆つていた金属及
び上方のホトレジスト層も除去される。同時に、
凹所の金属を覆つているホトレジストを除去す
る。
実施例 次に、添附図面に基づいて、本発明の実施例に
ついて、本発明をより詳細に説明する。
第１Ａ図は、ホトレジストの層１０２で覆われ
た基体１００を有する集積回路チツプを示してい
る。ホトレジスト層１０２には、全体的に参照符
号１０４として示した穴が通常の仕方で形成され
ており、基体１００には、側面１０７にて定めら
れた凹所１０６が形成されている。従つて、ホト
レジスト層１０２は、穴１０４の周囲を定める側
面１０３を有している。凹所１０６は、この凹所
１０６を定める側面１０７の上にホトレジスト層
１０２の張り出し部１０８が与えられるように、
指向性のある反応性イオンエツチングによつて形
成されている。
凹所１０６に充填しようとする金属を、チツプ
の表面上に、凹所１０６を充填するに十分な深さ
まで冷間スパツタリングする（第１Ｂ参照）。ホ
トレジスト１０２上の金属フイルム１１２の深さ
は、凹所内の深さとほぼ同じである。第１Ｂ図に
示すように、張り出し部の付近では、ホトレジス
トを覆う金属が、ホトレジスト層１０２の側面１
０３及び上表面によつて定められた角部の周りで
湾曲している。金属フイルムの深さには限度があ
るのと、張り出し部１０８が与えられているのと
で、凹所内のフイルム１１０の表面は、張り出し
部の下で若干凹状になつており、従つて、ホトレ
ジストを覆う金属フイルムは、凹所内の金属フイ
ルムとは接触していない。
次いで、チツプの全面を第２のホトレジスト層
１１４で覆う（第１Ｃ図参照）。凹所１０６の領
域では、第２のホトレジスト層の上表面が若干凹
状となり、穴１０４の周囲を定める側面１０３付
近の領域の方がチツプの他の領域よりも全体的に
薄くなる。反応性イオンエツチングを用いて、ホ
トレジスト１１４の表面の部分を除去して、ホト
レジスト層１０２の穴１０４の周囲付近にある金
属フイルム１１２の角部を露出させる（第１Ｄ図
参照）。次いで、ウエツト金属エツチングを使用
して、金属層１１２の露出部分を、その下のホト
レジスト層１０２を露出させるに十分な程、エツ
チングする（第１Ｅ図参照）。凹所の金属層１１
０は、残りのホトレジスト層１１４によつて覆わ
れており、このホトレジスト層１１４及び張り出
し部１０８によつてウエツト金属エツチングから
保護されているので、金属層１１０は、ウエツト
金属エツチングによつて損傷を受けない。更に、
ホトレジスト層１０２は、通常の仕方で除去さ
れ、このホトレジスト層１０２に共に、その上の
金属層１１２及びホトレジスト層１１４も除去さ
れる。これと同時に、金属層１１０上のホトレジ
スト層１１４も除去され、第１Ｆ図に示す構成が
得られる。
以上、特定の実施例について、本発明の種々な
特徴について説明した。しかしながら、本発明
は、前述した以外の種々な変形においても、本発
明の効果のうちのいくつか、またはすべてを達成
することができるものであることは、明らかであ
ろう。したがつて、本特許請求の範囲の記載は、
本発明の真の精神および範囲内に包含されるよう
なすべての変形態様をカバーしようとするもので
ある。
【図面の簡単な説明】
第１Ａ図から第１Ｆ図は、本発明により凹所に
金属フイルムを充填する方法を詳細に示す断面図
である。 １００……基体、１０２……ホトレジスト層、
１０６……凹所、１０８……張り出し部、１１０
……金属層、１１２……金属層、１１４……ホト
レジスト層。

Claims (1)

  1. 【特許請求の範囲】 １ 集積回路チツプに凹所を形成して該凹所に金
    属を充填する方法において、 Ａ 前記チツプ上にホトレジストの層を付与し、
    前記凹所を形成すべき領域におけるホトレジス
    トを除去し、 Ｂ 前記除去されたホトレジストによつて定めら
    れた前記チツプの領域に、凹所を、ホトレジス
    トがその凹所上に張り出すようにして、形成
    し、 Ｃ 前記凹所及び前記ホトレジスト層の表面の上
    に金属の層をスパツタリングして、前記金属
    が、前記凹所に層状に付与され、且つ前記ホト
    レジスト層の上面及び側面を覆い、しかも、前
    記ホトレジスト層上の金属は、前記凹所の金属
    層から分離されているようにし、 Ｄ 前記凹所上にくぼみができるに十分な深さま
    で前記チツプの表面をマスキング材料で覆い、 Ｅ 前記マスキング材料の層をエツチングして、
    前記ホトレジスト層の上表面および側面によつ
    て定められた前記ホトレジスト層の角部の上の
    前記金属層の部分を露出させ、 Ｆ 前記露出した金属をエツチングして、前記ホ
    トレジスト層の角部の領域における前記ホトレ
    ジスト層の上表面及び側面を露出させ、 Ｇ 前記ホトレジスト層を除去して、その上のマ
    スキング材料層および金属層を除去し、 Ｈ 前記凹所における前記金属層上のマスキング
    材料層を除去する。 ことを特徴とする方法。 ２ 前記マスキング材料は、前記ホトレジストを
    除去する段階と前記マスキング材料層を除去する
    段階とを同時に行えるように、ホトレジストであ
    る特許請求の範囲第１項に記載の方法。
JP60103652A 1984-05-15 1985-05-15 集積回路チップにおける金属充填方法 Granted JPS6144470A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/610,337 US4584761A (en) 1984-05-15 1984-05-15 Integrated circuit chip processing techniques and integrated chip produced thereby
US610337 1984-05-15

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP4335941A Division JP2749750B2 (ja) 1984-05-15 1992-12-16 集積回路チップの製造方法

Publications (2)

Publication Number Publication Date
JPS6144470A JPS6144470A (ja) 1986-03-04
JPH0569292B2 true JPH0569292B2 (ja) 1993-09-30

Family

ID=24444623

Family Applications (3)

Application Number Title Priority Date Filing Date
JP60103652A Granted JPS6144470A (ja) 1984-05-15 1985-05-15 集積回路チップにおける金属充填方法
JP4335941A Expired - Lifetime JP2749750B2 (ja) 1984-05-15 1992-12-16 集積回路チップの製造方法
JP8039365A Expired - Lifetime JP2886494B2 (ja) 1984-05-15 1996-02-27 集積回路チップの製造方法

Family Applications After (2)

Application Number Title Priority Date Filing Date
JP4335941A Expired - Lifetime JP2749750B2 (ja) 1984-05-15 1992-12-16 集積回路チップの製造方法
JP8039365A Expired - Lifetime JP2886494B2 (ja) 1984-05-15 1996-02-27 集積回路チップの製造方法

Country Status (5)

Country Link
US (1) US4584761A (ja)
EP (2) EP0392642B1 (ja)
JP (3) JPS6144470A (ja)
CA (1) CA1234226A (ja)
DE (2) DE3588129T2 (ja)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4696098A (en) * 1986-06-24 1987-09-29 Advanced Micro Devices, Inc. Metallization technique for integrated circuit structures
JPH01129440A (ja) * 1987-11-14 1989-05-22 Fujitsu Ltd 半導体装置
US4868138A (en) * 1988-03-23 1989-09-19 Sgs-Thomson Microelectronics, Inc. Method for forming a self-aligned source/drain contact for an MOS transistor
US5202286A (en) * 1989-02-27 1993-04-13 Mitsubishi Denki Kabushiki Kaisha Method of forming three-dimensional features on substrates with adjacent insulating films
JP2597703B2 (ja) * 1989-02-27 1997-04-09 三菱電機株式会社 半導体装置の製造方法
JPH0382126A (ja) * 1989-08-25 1991-04-08 Hitachi Ltd 半導体集積回路装置の製造方法
US5091339A (en) * 1990-07-23 1992-02-25 Microelectronics And Computer Technology Corporation Trenching techniques for forming vias and channels in multilayer electrical interconnects
KR930006128B1 (ko) * 1991-01-31 1993-07-07 삼성전자 주식회사 반도체장치의 금속 배선 형성방법
US5187119A (en) * 1991-02-11 1993-02-16 The Boeing Company Multichip module and integrated circuit substrates having planarized patterned surfaces
US5266516A (en) * 1992-01-02 1993-11-30 Chartered Semiconductor Manufacturing Pte Ltd Method for making electrical contact through an opening of one micron or less for CMOS technology
JP2885616B2 (ja) * 1992-07-31 1999-04-26 株式会社東芝 半導体装置およびその製造方法
US5242534A (en) * 1992-09-18 1993-09-07 Radiant Technologies Platinum lift-off process
US5733812A (en) * 1993-11-15 1998-03-31 Matsushita Electric Industrial Co., Ltd. Semiconductor device with a field-effect transistor having a lower resistance impurity diffusion layer, and method of manufacturing the same
US20040070048A1 (en) * 2002-10-15 2004-04-15 Kwok Siang Ping Providing high precision resistance in an integrated circuit using a thin film resistor of controlled dimension
US20060009038A1 (en) 2004-07-12 2006-01-12 International Business Machines Corporation Processing for overcoming extreme topography
JP4825477B2 (ja) * 2005-09-21 2011-11-30 東芝エレベータ株式会社 乗客コンベヤの内レッジ、乗客コンベヤ、乗客コンベヤの固定サポートの位置決め方法、並びに乗客コンベヤの固定サポート
JP4920949B2 (ja) * 2005-11-02 2012-04-18 株式会社日立製作所 乗客コンベアの内デッキの取付け構造
US8649123B1 (en) 2008-11-26 2014-02-11 Western Digital (Fremont), Llc Method to eliminate reactive ion etching (RIE) loading effects for damascene perpendicular magnetic recording (PMR) fabrication
US8257597B1 (en) 2010-03-03 2012-09-04 Western Digital (Fremont), Llc Double rie damascene process for nose length control
WO2017011723A1 (en) * 2015-07-16 2017-01-19 Pixelteq, Inc. Lithography process for the encapsulation of patterned thin film coatings

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4929067A (ja) * 1972-07-12 1974-03-15
JPS54159168A (en) * 1978-06-05 1979-12-15 Ibm Method of forming doping area automatically positioned
JPS57112028A (en) * 1980-12-29 1982-07-12 Fujitsu Ltd Manufacture of semiconductor device
JPS57196573A (en) * 1981-05-27 1982-12-02 Toshiba Corp Manufacture of mos type semiconductor device

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5169363A (en) * 1974-12-13 1976-06-15 Fujitsu Ltd Handotaisochino seizohoho
US3985597A (en) * 1975-05-01 1976-10-12 International Business Machines Corporation Process for forming passivated metal interconnection system with a planar surface
JPS5819129B2 (ja) * 1975-12-10 1983-04-16 株式会社東芝 ハンドウタイソウチノ セイゾウホウホウ
NL7604986A (nl) * 1976-05-11 1977-11-15 Philips Nv Werkwijze voor het vervaardigen van een halfgeleider- inrichting, en inrichting vervaardigd door toe- passing van de werkwijze.
US4114255A (en) * 1976-08-16 1978-09-19 Intel Corporation Floating gate storage device and method of fabrication
US4360823A (en) * 1977-03-16 1982-11-23 U.S. Philips Corporation Semiconductor device having an improved multilayer wiring system
US4192059A (en) * 1978-06-06 1980-03-11 Rockwell International Corporation Process for and structure of high density VLSI circuits, having inherently self-aligned gates and contacts for FET devices and conducting lines
US4277881A (en) * 1978-05-26 1981-07-14 Rockwell International Corporation Process for fabrication of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US4219379A (en) * 1978-09-25 1980-08-26 Mostek Corporation Method for making a semiconductor device
JPS5575241A (en) * 1978-12-02 1980-06-06 Toshiba Corp Method of fabricating semiconductor device
US4266985A (en) * 1979-05-18 1981-05-12 Fujitsu Limited Process for producing a semiconductor device including an ion implantation step in combination with direct thermal nitridation of the silicon substrate
NL8004573A (nl) * 1979-09-19 1981-03-23 Gen Electric Werkwijze voor het vervaardigen van samengestelde voorwerpen.
JPS56111241A (en) * 1980-02-01 1981-09-02 Chiyou Lsi Gijutsu Kenkyu Kumiai Preparation of semiconductor device
US4441941A (en) * 1980-03-06 1984-04-10 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device employing element isolation using insulating materials
US4322883A (en) * 1980-07-08 1982-04-06 International Business Machines Corporation Self-aligned metal process for integrated injection logic integrated circuits
US4367119A (en) * 1980-08-18 1983-01-04 International Business Machines Corporation Planar multi-level metal process with built-in etch stop
US4391650A (en) * 1980-12-22 1983-07-05 Ncr Corporation Method for fabricating improved complementary metal oxide semiconductor devices
US4564997A (en) * 1981-04-21 1986-01-21 Nippon-Telegraph And Telephone Public Corporation Semiconductor device and manufacturing process thereof
JPS58111241A (ja) * 1981-12-25 1983-07-02 Hitachi Ltd マグネトロン
US4424621A (en) * 1981-12-30 1984-01-10 International Business Machines Corporation Method to fabricate stud structure for self-aligned metallization
US4419810A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Self-aligned field effect transistor process
DE3211761A1 (de) * 1982-03-30 1983-10-06 Siemens Ag Verfahren zum herstellen von integrierten mos-feldeffekttransistorschaltungen in siliziumgate-technologie mit silizid beschichteten diffusionsgebieten als niederohmige leiterbahnen
US4440804A (en) * 1982-08-02 1984-04-03 Fairchild Camera & Instrument Corporation Lift-off process for fabricating self-aligned contacts
US4617193A (en) * 1983-06-16 1986-10-14 Digital Equipment Corporation Planar interconnect for integrated circuits

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4929067A (ja) * 1972-07-12 1974-03-15
JPS54159168A (en) * 1978-06-05 1979-12-15 Ibm Method of forming doping area automatically positioned
JPS57112028A (en) * 1980-12-29 1982-07-12 Fujitsu Ltd Manufacture of semiconductor device
JPS57196573A (en) * 1981-05-27 1982-12-02 Toshiba Corp Manufacture of mos type semiconductor device

Also Published As

Publication number Publication date
CA1234226A (en) 1988-03-15
EP0392642B1 (en) 1994-12-21
EP0162774A3 (en) 1988-01-07
EP0162774A2 (en) 1985-11-27
DE3588129D1 (de) 1996-12-12
JPH0951033A (ja) 1997-02-18
DE3587963D1 (de) 1995-02-02
US4584761A (en) 1986-04-29
EP0162774B1 (en) 1996-11-06
EP0392642A1 (en) 1990-10-17
DE3587963T2 (de) 1995-08-03
JP2749750B2 (ja) 1998-05-13
DE3588129T2 (de) 1997-05-28
JP2886494B2 (ja) 1999-04-26
JPH05243373A (ja) 1993-09-21
JPS6144470A (ja) 1986-03-04

Similar Documents

Publication Publication Date Title
JPH0569292B2 (ja)
JP2583408B2 (ja) 集積回路上にパターン化された導電体の層を形成する方法
US5436199A (en) Pillar alignment and formation process
US5187121A (en) Process for fabrication of a semiconductor structure and contact stud
US4007103A (en) Planarizing insulative layers by resputtering
US5863828A (en) Trench planarization technique
US5530294A (en) Semiconductor contact that partially overlaps a conductive line pattern and a method of manufacturing same
JPH098130A (ja) 半導体デバイスのビアホール形成方法
US4783238A (en) Planarized insulation isolation
JP2822430B2 (ja) 層間絶縁膜の形成方法
US4035206A (en) Method of manufacturing a semiconductor device having a pattern of conductors
JP4398524B2 (ja) 境界領域の導電層形成を防止する半導体メモリ装置のゲート形成方法
US4693783A (en) Method of producing interconnections in a semiconductor integrated circuit structure
CA1135852A (en) Bubble memory chip and method for manufacture
KR19980068004A (ko) 반도체소자 분리구조 및 그 제조방법
JPS62222657A (ja) 導体配線およびその形成方法
JPS61244042A (ja) 素子分離領域の形成方法
JPH0770523B2 (ja) 半導体装置の製造方法
JPH0713958B2 (ja) 半導体装置の製造方法
JPS5952542B2 (ja) 半導体装置の製造方法
JPH0531301B2 (ja)
JPH02105529A (ja) 半導体装置の製造方法
JPH04247642A (ja) メタルプラグの形成方法
JPH0153500B2 (ja)
JPH0562983A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term