CA1135852A - Bubble memory chip and method for manufacture - Google Patents
Bubble memory chip and method for manufactureInfo
- Publication number
- CA1135852A CA1135852A CA000342357A CA342357A CA1135852A CA 1135852 A CA1135852 A CA 1135852A CA 000342357 A CA000342357 A CA 000342357A CA 342357 A CA342357 A CA 342357A CA 1135852 A CA1135852 A CA 1135852A
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- CA
- Canada
- Prior art keywords
- layer
- conductor
- dielectric
- resist material
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/02—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
- G11C19/08—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
- H01F41/32—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying conductive, insulating or magnetic material on a magnetic film, specially adapted for a thin magnetic film
- H01F41/34—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for applying conductive, insulating or magnetic material on a magnetic film, specially adapted for a thin magnetic film in patterns, e.g. by lithography
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Magnetic Films (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
Disclosed is a bubble memory chip manufactured using the following processing steps: a first dielectric insulation layer is deposited on an epitaxial garnet substrate, next, a comparatively thicker layer of a second dielectric insulator is deposited on the surface of the first layer of di-electric insulation, next, the reverse of the desired conductor image is printed on the surface of the second layer of dielectric insulator using a resist material such as a photoresist, next, a straight wall etching process is used to achieve a straight wall etching of the second layer of dielectric insulation but not affecting the first layer of dielectric insulation, next, the selected conductor material is deposited into the exposed groove from the previous etching process and over any remaining resist material such as a photoresist, next, a resist material is applied over the resulting conducting surface from the previous step, next, a coarse featured pattern is printed over the desired conductor regions leaving exposed the extensive surface area of the chip where no finished conductor features will be present, next, all exposed conductor is etched off using chemical processes, and finally, the last step is a stripping of the photoresist including lift-off of remaining unused conductor material to leave a planar surface.
Disclosed is a bubble memory chip manufactured using the following processing steps: a first dielectric insulation layer is deposited on an epitaxial garnet substrate, next, a comparatively thicker layer of a second dielectric insulator is deposited on the surface of the first layer of di-electric insulation, next, the reverse of the desired conductor image is printed on the surface of the second layer of dielectric insulator using a resist material such as a photoresist, next, a straight wall etching process is used to achieve a straight wall etching of the second layer of dielectric insulation but not affecting the first layer of dielectric insulation, next, the selected conductor material is deposited into the exposed groove from the previous etching process and over any remaining resist material such as a photoresist, next, a resist material is applied over the resulting conducting surface from the previous step, next, a coarse featured pattern is printed over the desired conductor regions leaving exposed the extensive surface area of the chip where no finished conductor features will be present, next, all exposed conductor is etched off using chemical processes, and finally, the last step is a stripping of the photoresist including lift-off of remaining unused conductor material to leave a planar surface.
Description
S~i2 This invention relates to fabrication of bubble memory chip de-vices. In particular, this invention relates to the production of the fine conductor patt,ern on the garnet substrate prior to the addition of rurther permalloy ana dielectric elements.
Conventional bubble memory circuits are fabricated in a non-planar process in which the permalloy elements cross over the conductor elements in the active areas of the chip. These non-planar devices are usually limited -~
in performance by weak margins or limits of performance in the areas ~rhere step coverage of conductors by permalloy elements exists. One solution to this problem of marginal performunce would ~e a process in which the perm-alloy elements are fabricated on a planar surface having buried conductors therein. It is one of the obJects o~ this invention to produce a bub~le memory chip and method for fabrication which would have buried conductors on which perm~lloy elements would be fabricated. Among the ad~antages of such an arrangement would be the linear flux continuity of the permalloy elements.
Because there would be no discontinuities at the steps of the permalloy ele-ments there is a reduced need ~or drive and power requirements and a corre-sponding increase in production yield and operating margin characteristics.
Also, all portior.s of each permalloy element would be spaced at the unifor~
optimum distance from the garnet substrate thereby reducing error rates and increasing performance margins. A further advantage ~ould be obtained in the fabrication steps involving the permalloy elements because a higher res-olution and greater density could be obtained in these elements without the step features. Also, the proper formation of steps in conductive elements requires care~ul contro] of the edges at the step to pro~ide pr~per conductor thickness and conductiYity. By eliminating steps the conductor conductivity would be optimized. Similarly, the planar conductors uniformly encased in the dielectric media would result in more uniform magnetic fields than those .-, , - ., . . . . , ., ,, - - ~ : : :
~358S2 achieved using step featllres.
Several planar processes have been developecl ~or semiconauctor de-ViC~5. ~hese processes involve the so called lift-off techniques in ~hich either the conductor or dielectric is back ~illed to bring the surface to a planar level. However the materials used in semiconductor manufacture are not appropriate for bubble memory device manufacture b~cause the materials used in the lift-off process are dielectric rather than conductive and be-cause of the comparatively different surface features in the bubble me~lory aesign.
An excellent paper discussing this subJect is that by J. P.
Reecksten and R. Kowalchuk ~ound in IEEE T.ransactions on Magnetics, Volume MAG-9, ~lumber 3, September 1973, entitled "Fabrication o~ Large Bubble Cir~
cuits" at page-LS~. The various processes described suffer from a variety of problems. Stencil deposition requires either double masking or metal/
resist lift-off. The firle ~eometr~ and unique topography o~ bubble circuits makes this difficult to implement. Dielectric lif't-off is not compatible ~ith the high temperature deposition techniques used in bubble memory fab-rication. Electroless stencil. techniques demand thin, buried~ catalytic layers or an additional masking step requiring close registration. A11 tech-. niques requiring more than a single registration process step becomes signif-icantly more complicated because the various registration layers have to be aligned with one another as well as features involved. The invention de-scribed in the present application is a development based on the stencil etch technique.
The present invention is a combination of fabrication steps in the formation o~ a conductor layer on a garnet su~strate for bubble memory chips.
The resulting product is a garnet substra.te having a cond~ctor layer ~ormed thereon and having a planar surface suitable for deposition of permalloy . . , ~ - ~
~3585~:
elements according to the desired bubble memory pat-tern.
Initially, the epitaxial garnet substrate has a two layer dielec-tric deposited thereon. The first layer of dielectric has a greater resis-tance to the etching process to ~e used than the second layer of dielectric material. Thus the first layer of dielectric material serves as a stop-off or a stop guard for the stencil etch processing step. Thus, the first laye of dielectric lnsulation provides a buried strain-relief layer of predictable and predetermined thickness.
A significant feature of bubble memory chips is that such a large portion of the garnet surface is not covered with conductor, or to say it in another way, only a very small proportion o~ the total area of the garnet substrate is covered by conductor. Thus, one of the significant steps in the -~
process is the use of a crude or coarse featured, minimally registered pat-tern in an additional masking step to aid with the lift-off step in the pro-cess. Because of the large unfeatured areas of the bubble memory chip, there would be no entry point for the resist stripper and the lift-off would be clifficult and perhsps incomplete at best. Thus the coarse masking step and the following etching steps reduce the final resist stripping step to only more essential features of the bubble memory chip.
'~his approach has advantages in that the processing steps are rel-atively straightforward in execution and do not require advanced technology.
The additional masking step, because it is only applied in a coarse fashion, does not require the care or processing technique required for close regis-tration and high resolution. Because of the fact that no dielectric li~t-off step is involved in this technique, there is no problem of compatibility with high temperatl~e dielectric deposition steps. ~he ~inal product results in a truly planar surface of the type desir~d and which is compatible with fine line features being developed.
` ;" ~L~358~:
Thus, in accordance with a broad aspect of the ;nvention, there is provided a method for forming a bubble memory chip comprising the steps of depositing a first layer of dielectric insula.tor on a garnet substrate, depositing a second layer of dielectric insulator on the surface formed of the first dielectric insulator, the second dielectric insulator being of a matcrial which will be etched by a particular process which will not affect the first dielectric insulation layer, applying an initial resist pat~ern in the reverse image of the predetermined desired conductor pattern to be formed, straight wall etching the second dielectric layer according to the pattern formed by the resist material by not etching the first dielectric insulator layer of mater-ial, applying a conductor material by a dep~sition process into the grooves formed by the previous etching process and on the surface of the remaining resist material, applying a coarse featured resist material over the compara-tively small portion of the chip corresponding to approximately five percent more or less of the surface area of the finished chip which is desired to be covered by a conductor pattern at the conclusion of processing and in coarse and not exact registration with the conductor features to be preserved but not over any comparatively larger features of the chip which are to have no con-ductor pattern, etching by chemical means all of the conductor material not covered by the coarse resist material applied in the previous step, and strip-ping away the coarse resist material left from the previous step and lifting off unused conductor material along with said initial photoresist to leave a planar surface comprised of conductor material formed in the pattern of con-ductor elements at a surface coplanar with the surface of the second dielectric insulator material.
In accordance with another broad aspect of the invention there is _ ~ _ ~ 35852 provided a chip for bubble memory fabrication comprised oE a garnet substrate, a first continuous dielectric layer :Eormed on the surface of ~he garnet sub-strate consisting of approximately 2,000 Angstroms thickness of magnesium oxide acting as a buried strain-relief layer, a second dielectric layer con- ;:
sisting of approximately 5,000 Angstroms thickness of silicon dioxide and approximately 2 1/2 times as thick as the first dielectric layer on the surface formed of the first dielectric layer and a conductor pattern of conductor material buried in said second dielectric layer and having straight wall con-tact with said second dielectric layer. :~
The invention will now be Eurther described in conjunction with the ^: :
4a -accompanying drawings, in which:
Figure 1 shows the first stages of the process in wbich the first and second dielectric layers are deposited on the garnet substrate according to the inven-t,ion.
Figure 2 shows a further processing stage according to the inven-tion in which a reverse conductor image resist material has been imprinted on the surface shown in Figure 1 and then straight-wall etched.
Figure 3 shows a further stage in the process according to the present invention in which the stage represented in Figure ~ has had a con-ductor layer deposited into the exposed groove and over all of the remainingresist material.
Figure ~ shows the stage in processing according to the invention after that shown in ~igure 3 in which a coarse featured block pattern resist material is printed over conductor regions in a further resist appl~ed to the chip.
Figure 5 shows the next stage of processing after Figure ~ accora-ing to the in~ention in which -the exposed conductor material is etched off using a chemical process.
Figure 6 shows the final step according to the present invention after the stage shown in Figure 5 in which the photoresist i9 stripped and the remainin~ unused conductor material is lifted off leaving a planar sur-face for further processing.
Referring now to Figure 1, an initial substrate 10 of epitaxial garnet of the type conventionally used for bubble memory chips is shown in which a first dielectric layer 12 has been deposited in a conventional fash-ion. This layer is a dielectric insulator such as a metal oxide and it is deposited to a thickness o~ approximately 2000 angstroms. The layers of materials shown in the fi~ures are not shown to scale. A second la~er 1~ of another dielectric insulator is shown aeposited on the ~irst ]ayer 1~ Or dielectric insulator. This second layer of dielectric material is deposited to a greater thickness than the first layer and may ~or example be on the order of 5000 angstroms thick or approximately 2-1/2 times as thick as the first layer of dielectric ma-terial. The material is chosen to be a material more easily etched than -the first layer of dielectric material and may for example be silicon dioxide. Other materials and relationships between the first and second dielectric layers exist. For example, silicon dioxide and maenesium oxide may be used as the appropriate dielectric layers. These materials are selected so that they may be vacuum deposited and dif*erential-ly etched, using a mass spectrometer to de-tect the end point of ion etching requires only a different atomic weight of the cation.
Rererring now to Figure 2 showing a further processing step from that shown in Figure 1 shows that a resist layer 16 ma-terial of any common and appropriate type such a~ a positive photoresist or metal resist is ap~
plied on the surface of the second dielectric layer 14. For example a metal or bismuth oxide resist may be used. ~his material would be used because of its temperature tolerance and ability to ~ithstand further processing steps.
This resist is applied to a thickness of approximately one to two microm-eters. This photoresist is applied in the re~erse image o* the desired con-ductor pattern. Figure 2 -then shows the -further processing step having been completed in which the second layer 14 o~' dielectric insulation material has been straight wall etched to expose the surface of the first layer 12 o* di-e]ectric insulator ma-t,erial. The straight wall etching processes may for example be plasma or ion beam etching and the *irst layer 12 o~ dielectric material acts as a stopping barrier or detectable endpoint where the first layer 1~ of diele~tric material is more easily etched.
Referring now to Figure 3, a further step ~rom that sh~wn in Figure
Conventional bubble memory circuits are fabricated in a non-planar process in which the permalloy elements cross over the conductor elements in the active areas of the chip. These non-planar devices are usually limited -~
in performance by weak margins or limits of performance in the areas ~rhere step coverage of conductors by permalloy elements exists. One solution to this problem of marginal performunce would ~e a process in which the perm-alloy elements are fabricated on a planar surface having buried conductors therein. It is one of the obJects o~ this invention to produce a bub~le memory chip and method for fabrication which would have buried conductors on which perm~lloy elements would be fabricated. Among the ad~antages of such an arrangement would be the linear flux continuity of the permalloy elements.
Because there would be no discontinuities at the steps of the permalloy ele-ments there is a reduced need ~or drive and power requirements and a corre-sponding increase in production yield and operating margin characteristics.
Also, all portior.s of each permalloy element would be spaced at the unifor~
optimum distance from the garnet substrate thereby reducing error rates and increasing performance margins. A further advantage ~ould be obtained in the fabrication steps involving the permalloy elements because a higher res-olution and greater density could be obtained in these elements without the step features. Also, the proper formation of steps in conductive elements requires care~ul contro] of the edges at the step to pro~ide pr~per conductor thickness and conductiYity. By eliminating steps the conductor conductivity would be optimized. Similarly, the planar conductors uniformly encased in the dielectric media would result in more uniform magnetic fields than those .-, , - ., . . . . , ., ,, - - ~ : : :
~358S2 achieved using step featllres.
Several planar processes have been developecl ~or semiconauctor de-ViC~5. ~hese processes involve the so called lift-off techniques in ~hich either the conductor or dielectric is back ~illed to bring the surface to a planar level. However the materials used in semiconductor manufacture are not appropriate for bubble memory device manufacture b~cause the materials used in the lift-off process are dielectric rather than conductive and be-cause of the comparatively different surface features in the bubble me~lory aesign.
An excellent paper discussing this subJect is that by J. P.
Reecksten and R. Kowalchuk ~ound in IEEE T.ransactions on Magnetics, Volume MAG-9, ~lumber 3, September 1973, entitled "Fabrication o~ Large Bubble Cir~
cuits" at page-LS~. The various processes described suffer from a variety of problems. Stencil deposition requires either double masking or metal/
resist lift-off. The firle ~eometr~ and unique topography o~ bubble circuits makes this difficult to implement. Dielectric lif't-off is not compatible ~ith the high temperature deposition techniques used in bubble memory fab-rication. Electroless stencil. techniques demand thin, buried~ catalytic layers or an additional masking step requiring close registration. A11 tech-. niques requiring more than a single registration process step becomes signif-icantly more complicated because the various registration layers have to be aligned with one another as well as features involved. The invention de-scribed in the present application is a development based on the stencil etch technique.
The present invention is a combination of fabrication steps in the formation o~ a conductor layer on a garnet su~strate for bubble memory chips.
The resulting product is a garnet substra.te having a cond~ctor layer ~ormed thereon and having a planar surface suitable for deposition of permalloy . . , ~ - ~
~3585~:
elements according to the desired bubble memory pat-tern.
Initially, the epitaxial garnet substrate has a two layer dielec-tric deposited thereon. The first layer of dielectric has a greater resis-tance to the etching process to ~e used than the second layer of dielectric material. Thus the first layer of dielectric material serves as a stop-off or a stop guard for the stencil etch processing step. Thus, the first laye of dielectric lnsulation provides a buried strain-relief layer of predictable and predetermined thickness.
A significant feature of bubble memory chips is that such a large portion of the garnet surface is not covered with conductor, or to say it in another way, only a very small proportion o~ the total area of the garnet substrate is covered by conductor. Thus, one of the significant steps in the -~
process is the use of a crude or coarse featured, minimally registered pat-tern in an additional masking step to aid with the lift-off step in the pro-cess. Because of the large unfeatured areas of the bubble memory chip, there would be no entry point for the resist stripper and the lift-off would be clifficult and perhsps incomplete at best. Thus the coarse masking step and the following etching steps reduce the final resist stripping step to only more essential features of the bubble memory chip.
'~his approach has advantages in that the processing steps are rel-atively straightforward in execution and do not require advanced technology.
The additional masking step, because it is only applied in a coarse fashion, does not require the care or processing technique required for close regis-tration and high resolution. Because of the fact that no dielectric li~t-off step is involved in this technique, there is no problem of compatibility with high temperatl~e dielectric deposition steps. ~he ~inal product results in a truly planar surface of the type desir~d and which is compatible with fine line features being developed.
` ;" ~L~358~:
Thus, in accordance with a broad aspect of the ;nvention, there is provided a method for forming a bubble memory chip comprising the steps of depositing a first layer of dielectric insula.tor on a garnet substrate, depositing a second layer of dielectric insulator on the surface formed of the first dielectric insulator, the second dielectric insulator being of a matcrial which will be etched by a particular process which will not affect the first dielectric insulation layer, applying an initial resist pat~ern in the reverse image of the predetermined desired conductor pattern to be formed, straight wall etching the second dielectric layer according to the pattern formed by the resist material by not etching the first dielectric insulator layer of mater-ial, applying a conductor material by a dep~sition process into the grooves formed by the previous etching process and on the surface of the remaining resist material, applying a coarse featured resist material over the compara-tively small portion of the chip corresponding to approximately five percent more or less of the surface area of the finished chip which is desired to be covered by a conductor pattern at the conclusion of processing and in coarse and not exact registration with the conductor features to be preserved but not over any comparatively larger features of the chip which are to have no con-ductor pattern, etching by chemical means all of the conductor material not covered by the coarse resist material applied in the previous step, and strip-ping away the coarse resist material left from the previous step and lifting off unused conductor material along with said initial photoresist to leave a planar surface comprised of conductor material formed in the pattern of con-ductor elements at a surface coplanar with the surface of the second dielectric insulator material.
In accordance with another broad aspect of the invention there is _ ~ _ ~ 35852 provided a chip for bubble memory fabrication comprised oE a garnet substrate, a first continuous dielectric layer :Eormed on the surface of ~he garnet sub-strate consisting of approximately 2,000 Angstroms thickness of magnesium oxide acting as a buried strain-relief layer, a second dielectric layer con- ;:
sisting of approximately 5,000 Angstroms thickness of silicon dioxide and approximately 2 1/2 times as thick as the first dielectric layer on the surface formed of the first dielectric layer and a conductor pattern of conductor material buried in said second dielectric layer and having straight wall con-tact with said second dielectric layer. :~
The invention will now be Eurther described in conjunction with the ^: :
4a -accompanying drawings, in which:
Figure 1 shows the first stages of the process in wbich the first and second dielectric layers are deposited on the garnet substrate according to the inven-t,ion.
Figure 2 shows a further processing stage according to the inven-tion in which a reverse conductor image resist material has been imprinted on the surface shown in Figure 1 and then straight-wall etched.
Figure 3 shows a further stage in the process according to the present invention in which the stage represented in Figure ~ has had a con-ductor layer deposited into the exposed groove and over all of the remainingresist material.
Figure ~ shows the stage in processing according to the invention after that shown in ~igure 3 in which a coarse featured block pattern resist material is printed over conductor regions in a further resist appl~ed to the chip.
Figure 5 shows the next stage of processing after Figure ~ accora-ing to the in~ention in which -the exposed conductor material is etched off using a chemical process.
Figure 6 shows the final step according to the present invention after the stage shown in Figure 5 in which the photoresist i9 stripped and the remainin~ unused conductor material is lifted off leaving a planar sur-face for further processing.
Referring now to Figure 1, an initial substrate 10 of epitaxial garnet of the type conventionally used for bubble memory chips is shown in which a first dielectric layer 12 has been deposited in a conventional fash-ion. This layer is a dielectric insulator such as a metal oxide and it is deposited to a thickness o~ approximately 2000 angstroms. The layers of materials shown in the fi~ures are not shown to scale. A second la~er 1~ of another dielectric insulator is shown aeposited on the ~irst ]ayer 1~ Or dielectric insulator. This second layer of dielectric material is deposited to a greater thickness than the first layer and may ~or example be on the order of 5000 angstroms thick or approximately 2-1/2 times as thick as the first layer of dielectric ma-terial. The material is chosen to be a material more easily etched than -the first layer of dielectric material and may for example be silicon dioxide. Other materials and relationships between the first and second dielectric layers exist. For example, silicon dioxide and maenesium oxide may be used as the appropriate dielectric layers. These materials are selected so that they may be vacuum deposited and dif*erential-ly etched, using a mass spectrometer to de-tect the end point of ion etching requires only a different atomic weight of the cation.
Rererring now to Figure 2 showing a further processing step from that shown in Figure 1 shows that a resist layer 16 ma-terial of any common and appropriate type such a~ a positive photoresist or metal resist is ap~
plied on the surface of the second dielectric layer 14. For example a metal or bismuth oxide resist may be used. ~his material would be used because of its temperature tolerance and ability to ~ithstand further processing steps.
This resist is applied to a thickness of approximately one to two microm-eters. This photoresist is applied in the re~erse image o* the desired con-ductor pattern. Figure 2 -then shows the -further processing step having been completed in which the second layer 14 o~' dielectric insulation material has been straight wall etched to expose the surface of the first layer 12 o* di-e]ectric insulator ma-t,erial. The straight wall etching processes may for example be plasma or ion beam etching and the *irst layer 12 o~ dielectric material acts as a stopping barrier or detectable endpoint where the first layer 1~ of diele~tric material is more easily etched.
Referring now to Figure 3, a further step ~rom that sh~wn in Figure
2 has occurred in which a layer of metal 20 has been applied in the grooves 18 etched in the previous processing step a~d also covering the resist mate-rial 16. ~his metal conductor material is deposited to a -thickness of ap-proximately 5000 angstroms and may consist of metals such as aluminu~ or gold. Once again, the thickness of the conductor layer is intentionally not shown to scale in Figure 3 to more clearly illustrate the invention and to more clearly emphasize the fact that this in~ention is not to be limited by exact thicknesses or dimensions of materials. The conductor ~Ry be an alumi-num-copper allo~ or gold or any highly conductive metal resis-tant to electro-migration.
Referring now to ~igure 4, a resist material layer 22 is applied over all o~ the features that have been produced throueh the processing stages shown in Figure 3 to cover all exposed sec-tions of` the conductor mate-rial 20 in regions where grooves 18 exist which represent the final desired conductor pattern to remain after a~l processing is completea. Material layer 22 may be a photoresist. This resist material layer 22 is defined in an extre~ely coarse -featured pattern over these conductor regions but not over the remaining areas of the chip where no conductor is to exist when pro-cessing according to the present invention is complete. Thus in Figure 4, areas 24 and 26 of conductor 20 are shown uncovered by resist layer ?2 to represent the approximately 95 percent of the final chip in which there will be no conductor pattern according to this processing method. Thus~ resist layer 22 is applied to generally co~er in a coarse fashion areas where a con-ductor i~ to remain after all processing is complete.
Referring now to Figure 5, the processing step following the stage reached in ~igure 4 is shown in which a wet chemical or acid etch technique is used to remove all of the exposed conductor material 20 uncoverea by re~
sist layer 22. This acid etching step is not critical as to aetail since no ,.
: .
.~ .
51~5~
final feature remaining in the finished product is etched or created at this stage of processing. The advantage is that the remaining resist 22 covers in a coarse fashion conductor areas comprising approximately five percent, more or less, o~ the finished chip.
Referrin~ no~ to Fi6ure ~, all of the final processing steps have been completed and the finished product is shown. ~hese final processes con-sist of stripping the photoresist by an appropriate method~ ting off any unused conductor 20, and stripping any remaining resist covered by the con-ductor 20. Thus all of the resist layer 22 and the resist 16 is removed in the final processing steps together with the stripping off of the unused por tions of conductor 20. Thus, Figure 6 shows a finished product consisting of a garnet substrate 10, a uniform planar layer of a first dielectric and a second layer of dielectric 14 having conductor 20 formed into appropriate conductor patterns and buried in the dielectric 14 so that the resulting product has a planar unifor~ surface over both the dielectric 14 and the con-ductor material 20.
:`
;' ' ~ ' ' " ' ' ' ` ,, ', ' "
' ~, ' ' ' ' ' " , :'
Referring now to ~igure 4, a resist material layer 22 is applied over all o~ the features that have been produced throueh the processing stages shown in Figure 3 to cover all exposed sec-tions of` the conductor mate-rial 20 in regions where grooves 18 exist which represent the final desired conductor pattern to remain after a~l processing is completea. Material layer 22 may be a photoresist. This resist material layer 22 is defined in an extre~ely coarse -featured pattern over these conductor regions but not over the remaining areas of the chip where no conductor is to exist when pro-cessing according to the present invention is complete. Thus in Figure 4, areas 24 and 26 of conductor 20 are shown uncovered by resist layer ?2 to represent the approximately 95 percent of the final chip in which there will be no conductor pattern according to this processing method. Thus~ resist layer 22 is applied to generally co~er in a coarse fashion areas where a con-ductor i~ to remain after all processing is complete.
Referring now to Figure 5, the processing step following the stage reached in ~igure 4 is shown in which a wet chemical or acid etch technique is used to remove all of the exposed conductor material 20 uncoverea by re~
sist layer 22. This acid etching step is not critical as to aetail since no ,.
: .
.~ .
51~5~
final feature remaining in the finished product is etched or created at this stage of processing. The advantage is that the remaining resist 22 covers in a coarse fashion conductor areas comprising approximately five percent, more or less, o~ the finished chip.
Referrin~ no~ to Fi6ure ~, all of the final processing steps have been completed and the finished product is shown. ~hese final processes con-sist of stripping the photoresist by an appropriate method~ ting off any unused conductor 20, and stripping any remaining resist covered by the con-ductor 20. Thus all of the resist layer 22 and the resist 16 is removed in the final processing steps together with the stripping off of the unused por tions of conductor 20. Thus, Figure 6 shows a finished product consisting of a garnet substrate 10, a uniform planar layer of a first dielectric and a second layer of dielectric 14 having conductor 20 formed into appropriate conductor patterns and buried in the dielectric 14 so that the resulting product has a planar unifor~ surface over both the dielectric 14 and the con-ductor material 20.
:`
;' ' ~ ' ' " ' ' ' ` ,, ', ' "
' ~, ' ' ' ' ' " , :'
Claims (4)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A method for forming a bubble memory chip comprising the steps of depositing a first layer of dielectric insulator on a garnet substrate, depos-iting a second layer of dielectric insulator on the surface formed of the first dielectric insulator, the second dielectric insulator being of a material which will be etched by a particular process which will not affect the first dielectric insulation layer, applying an initial resist pattern in the reverse image of the predetermined desired conductor pattern to be formed, straight wall etching the second dielectric layer according to the pattern formed by the resist material by not etching the first dielectric insulator layer of material, applying a conductor material by a deposition process into the grooves formed by the previous etching process and on the surface of the re-maining resist material, applying a coarse featured resist material over the comparatively small portion of the chip corresponding to approximately five percent more or less of the surface area of the finished chip which is desired to be covered by a conductor pattern at the conclusion of processing and in coarse and not exact registration with the conductor features to be preserved but not over any comparatively larger features of the chip which are to have no conductor pattern, etching by chemical means all of the conductor material not covered by the coarse resist material applied in the previous step, and stripping away the coarse resist material left from the previous step and lift-ing off unused conductor material along with said initial photoresist to leave a planar surface comprised of conductor material formed in the pattern of con-ductor elements at a surface coplanar with the surface of the second dielectric insulator material.
2. The method of claim 1 in which the coarse resist material is a photoresist.
3. The method of claim 1 in which the initial resist material is bismuth oxide.
4. A chip for bubble memory fabrication comprised of a garnet substrate, a first continuous dielectric layer formed on the surface of the garnet sub-strate consisting of approximately 2,000 Angstroms thickness of magnesium oxide acting as a buried strain-relief layer, a second dielectric layer con-sisting of approximately 5,000 Angstroms thickness of silicon dioxide and approximately 2 1/2 times as thick as the first dielectric layer on the surface formed of the first dielectric layer and a conductor pattern of conductor material buried in said second dielectric layer and having straight wall con-tact with said second dielectric layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US2399579A | 1979-03-27 | 1979-03-27 | |
| US23,995 | 1979-03-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1135852A true CA1135852A (en) | 1982-11-16 |
Family
ID=21818297
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000342357A Expired CA1135852A (en) | 1979-03-27 | 1979-12-20 | Bubble memory chip and method for manufacture |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS598908B2 (en) |
| AU (1) | AU532007B2 (en) |
| CA (1) | CA1135852A (en) |
| DE (1) | DE2947952C2 (en) |
| FR (1) | FR2452762A1 (en) |
| GB (1) | GB2046040B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2539556B1 (en) * | 1983-01-13 | 1986-03-28 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING CONDUCTORS FOR INTEGRATED CIRCUITS, IN PLANAR TECHNOLOGY |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3985597A (en) * | 1975-05-01 | 1976-10-12 | International Business Machines Corporation | Process for forming passivated metal interconnection system with a planar surface |
| US4178635A (en) * | 1976-06-14 | 1979-12-11 | Hewlett-Packard Company | Planar and near planar magnetic bubble circuits |
| US4088490A (en) * | 1976-06-14 | 1978-05-09 | International Business Machines Corporation | Single level masking process with two positive photoresist layers |
| US4092442A (en) * | 1976-12-30 | 1978-05-30 | International Business Machines Corporation | Method of depositing thin films utilizing a polyimide mask |
-
1979
- 1979-11-28 DE DE19792947952 patent/DE2947952C2/en not_active Expired
- 1979-12-03 GB GB7941624A patent/GB2046040B/en not_active Expired
- 1979-12-20 CA CA000342357A patent/CA1135852A/en not_active Expired
-
1980
- 1980-01-17 JP JP314380A patent/JPS598908B2/en not_active Expired
- 1980-01-29 AU AU55011/80A patent/AU532007B2/en not_active Ceased
- 1980-03-25 FR FR8006647A patent/FR2452762A1/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| DE2947952A1 (en) | 1980-10-09 |
| GB2046040A (en) | 1980-11-05 |
| AU5501180A (en) | 1980-10-02 |
| JPS55132588A (en) | 1980-10-15 |
| GB2046040B (en) | 1983-03-16 |
| AU532007B2 (en) | 1983-09-15 |
| JPS598908B2 (en) | 1984-02-28 |
| DE2947952C2 (en) | 1985-01-10 |
| FR2452762B1 (en) | 1985-05-10 |
| FR2452762A1 (en) | 1980-10-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |