GB2046040A - Method of forming a bubble memory chip and a bubble memory chip made thereby - Google Patents

Abstract

A method of forming a bubble memory chip comprises depositing a first dielectric layer (12) on a garnet substrate (10). A second dielectric layer (14) is formed on the first layer. A resist pattern (16) is formed on the second layer and then straight-wall etched by means which do not etch the first layer. A conductor layer (20) is deposited in grooves (18) formed by the etching and on the surface of the initial resist pattern. A coarse resist material (22) is formed over the relatively small portion desired to be covered by a conductor pattern and in coarse registration with the conductor layer to be preserved but not over the relatively larger portion which is to have no conductor pattern. This conductor layer is chemically etched in the areas not covered by the coarse resist material. Finally the remaining coarse resist material is removed with the conductor layer on the resist pattern 16 to leave a planar surface composed of a conductor pattern at a surface co-planar with the surface of the second layer. <IMAGE>

Description

SPECIFICATION Method of forming a bubble memory chip and a bubble memory chip made thereby.

This invention relates to methods of forming bubble memory chips.

Conventional bubble memory chips are fabricated in a non-planar process in which permalloy elements cross over conductor elements in active areas of a bubble memory chip.

These non-planar bubble memory chips are usually limited in performance by weak margins or limits of performance in the areas where step coverage of the conductors by the permalloy elements exist.

One solution to this problem of marginal performance would be a process in which the permalloy elements are fabricated on a planar surface having buried conductors therein. Among the advantages of such an arrangement would be the linear flux continuity of the permalloy elements. Because there would be no dicontinuities at the steps of the permalloy elements there would be a reduced need for drive and power requirements and a corresponding increase in production yield and operating margin characteristics. Also, all portions of each permalloy element would be spaced at the uniform optimum distance from a substrate thereby reducing error rates and increasing performance margins. A further advantage would be obtained in the fabrication steps involving the permalloy elements because a higher resolution and greater density could be obtained in these elements without the step features.Also, the proper formation of steps in conductive elements requires careful control of the edges at the step to provide proper conductor thickness and conductivity. By eliminating steps the conductor conductivity would be optimised. Similarly, the planar conductors uniformly encased in the dielectric media would result in more uniform magnetic fields than those achieved using step features.

Several planar processes have been developed for semiconductor devices. These processes involve the so-called lift-off techniques in which either the conductor or dielectric is back filled to bring the surface to a planar level. However, the materials used in semiconductor manufacture are not appropriate for manufacture of bubble memory chips because the materials used in the lift-off process are dielectric rather than conductive and because of the comparatively different surface features in the design of the bubble memory chips.

An excellent paper discussing the subject is that by J. P. Reecksten and R. Kowalchuk found in IEEE Transactions on Magnetics, Volume MAG-9, Number 3, September 1973, entitled "Fabrication of Large Bubble Circuits" at page 465. The various processes described suffer from a variety of problems. Stencil deposition requires either double masking or metal/resist lift-off. The fine geometry and unique topography of bubble memory chips makes this difficult to implement.

Dielectric lift-off is not compatible with the high temperature disposition techniques used in the fabrication of bubble memory chips. Electroless stencil techniques demand thin, buried, catalytic layers or an additional masking step requiring close registration. All techniques requiring more than a single registration process step becomes significantly more complicated because the various registration layers have to be aligned with one another as well as features involved.

According to one aspect of the present invention there is provided a method of forming a bubble memory chip comprising the steps of: depositing a first layer of dielectric material on a garnet substrate; depositing a second layer of dielectric material on the first layer, the second layer being of a material which will be etched by means which will not etch the first layer; applying on the second layer an initial resist pattern in reverse imagine of a predetermined desired conductor pattern to be formed; straight wall etching the second layer but not the first layer according to the said initial resist pattern; depositing a conductor layer into grooves formed by the aforementioned etching step on the surface of the initial resist pattern; applying a coarse resist material over a relatively small portion desired to be covered by a conductor pattern and in coarse registration with the conductor layer to be preserved but not over the relatively larger portion which is to have no conductor pattern thereon; chemically etching all of the conductor layer not covered by the said coarse resist material; and removing the coarse resist material and conductor layer to leave a planar surface composed of a conductor pattern at a surface coplanar with the surface of the second layer.

The coarse resist material may be a photo resists.

The initial resist pattern may be of bismuth oxide.

According to a further aspect of the present invention there is provided a bubble memory chip when made by the method recited above.

The invention is illustrated, merely by way of example, in the accompanying drawings, in which:~ Figure 1 shows the first stage of a method according to the present invention of forming a bubble memory chip, first and second dielectric layers being deposited on a garnet substrate; Figure 2 shows a further stage of the method in which a reverse conductor image resist material has been imprinted on a surface shown in Figure 1 and then straight-wall etched; Figure 3 shows a further stage in the method in which the stage represented in Figure 2 has had a conductor layer deposited into an exposed groove and over all of the remaining resist material; Figure 4 shows the stage in the method after that shown in Figure 3 in which a coarse featured block pattern resist material is printed over conductor regions in a further resist applied to the bubble memory chip;; Figure 5 shows the next stage of the method after Figure 4 in which the exposed conductor material is etched off using a chemical process; and Figure 6 shows the final step in the method after the stage shown in Figure 5 in which the photoresist is stripped and the remaining unused conductor material is lifted off leaving a planar surface.

A method according to the present invention of forming a bubble memory chip is illustrated in Figures 1 to 6. Referring now to Figure 1, a substrate 10 of expitaxial garnet of the type conventionally used for bubble memory chips has a first dielectric layer 12 deposited thereon in conventional manner. This layer 12 is a dielectric insulator such as metal oxide and of approximately 2000 A. The layers of material shown in the Figures are not shown to scale. A second layer 14 of another dielectric insulator is deposited on the layer 12. This layer 14 is deposited to a greater thickness than the layer 12 and may, for example, be of the order of 5000 A thick or approximately 23 times as thick as the layer 12. The material of the layer 14 is of a material more easily etched than the layer 12 and may, for example, be silicon dioxide.Other materials and relationships between the first and second layers 12, 14 exist.

For example, silicon dioxide and magnesium oxide may be used as the layers 12, 14. These materials are selected so that they may be vacuum deposited and differentially etched. Using a mass spectrometer to detect the end point of ion etching requires only a different atomic weight of the cation.

Referring now to Figure 2 a resist layer 16 of any common and appropriate material such a positive photoresist of metal resist is applied on the surface of the second layer 14. For example, the resist layer 16 may be of a metal or bismuth oxide. This material would be used because of its temperature tolerance and ability to withstand further processing steps. The resist layer 16 is applied to a thickness of approximately one or two micrometers. The resist layer 16 is applied in the negative or reverse image of the desired conductor pattern. Figure 2 shows that the second layer 14 has been straight-wall etched to expose the surface of the first layer 12 and to form grooves 18. The straight-wall etching process may, for example, be plasma or ion beam etching and the first layer 12 acts as a stopping barrier or detectable endpoint where the first layer 14 is more easily etched.

Referring now to Figure 3, a layer 20 of metal is applied in the groove 18 and covers the resist layer 16. The layer 20 is deposited to a thickness of approximately 5000A and may consist of, for example, aluminium or gold. The thickness of the layer 20 is intentionally not shown to scale in Figure 3 to illustrate more clearly in the invention and to emphasise more clearly the fact that this invention is not to be limited by exact thicknesses or dimensions. The layer 20 may be an aluminiumcopper alloy or gold or any highly conductive metal resistant to e lectrom igration.

Referring now to Figure 4, a resist material layer 22 is applied over all of the features that have been produced through the processing stages shown in Figure 3 to cover all exposed sections of the layer 20 in regions where the grooves 1 8 exist which represent the final desired conductor pattern to remain after the bubble memory chip has been formed. The layer 22 may be a photoresist. This layer 22 is defined in an extremely coarse featured pattern over the layer 20 but not over the remaining areas when no conductor pattern is to exist. Thus areas 24. 26 of the layer 20 are shown uncovered by the layer 22 to represent the approximately 95% of the final bubble memory chip in which there will be no conductor pattern.Thus the layer 22 is applied to cover generally in a coarse fashion areas where the conductor pattern is to remain after the final bubble memory chip is formed.

Figure 5 illustrates a wet chemical or acid etch technique to remove all of the exposed layer 20 not covered by the layer 22. This acid etching step is not critical as to detail since no final feature remaining in the final bubble memory chip is etched or created at this stage. The advantage is that the remaining layer 22 covers, in a coarse fashion, conductor pattern areas comprising approximately 5%, more or less, of the final bubble memory chip.

The final bubble memory chip is shown in Figure 6. The final steps of the method consist of stripping the layer 22 by an appropriate method, lifting off any unused layer 20, and stripping any remaining layer 16 covered by the layer 20. Thus all of the layer 22 and the layer 16 is removed during the final steps together with stripping off of the unused portions of the layer 20. Thus Figure 6 shows the final bubble memory chip consisting of a a substrate 10, a layer 12 of a first dielectric material and a second layer 14 of a second dielectric material having an appropriate conductor pattern formed from the layer 20 and buried in the second layer 14. Thus the final bubble memory chip has a planar uniform surface over both the second layer 14 and the layer 20.

A significant feature of the bubble memory chip described above that such a large portion of the substrate 10 is not covered with the conductor pattern. Thus, one of the significant steps in the method is the use of a crude or coarse featured minimally registered layer 22 in an additional masking step to aid with the lift-off step. Because of the large unfeatured areas of the bubble memory chip, there would be no entry point for the resist stripper and the lift-off would be difficult and perhaps incomplete at best. Thus the coarse masking step and the following etching steps reduced the final resist stripping step to only more essential features of the bubble memory chip.

This approach has the advantage that the method steps are relatively straightforward in execution and do not require advanced technology. The additional masking step, because it is only applied in a coarse fashion, does not require the care or processing technique required for close registration and high resolution. Because of the fact that no dielectric lift-off step is involved in this technique, there is no problem of compatibility with high temperautre dielectric deposition steps. The final bubble memory chip has a truly planar surface of the type desired and which is compatible with fine line features being developed.

Claims (5)

1. A method of forming a bubble memory chip comprising the steps of: depositing a first layer of dielectric material on a garnet substrate; depositing a second layer of dielectric material on the first layer, the second layer being of a material which will be etched by means which will not etch the first layer; applying on the second layer an initial resist pattern in reverse image of a predetermined desired conductor pattern to be formed; straight wall etching the second layer but not the first layer according to the said initial resist pattern; depositing a conductor layer into grooves formed by the aforementioned etching step on the surface of the initial resist pattern; applying a coarse resist material over a relatively small portion desired to be covered by a conductor pattern and in coarse registration with the conductor layer to be preserved but not over the relatively larger portion which is to have no conductor pattern thereon; chemically etching all of the conductor layer not covered by the said coarse resist material; and removing the coarse resist material and conductor layer to leave a planar surface composed of a conductor pattern at a surface coplanar with the surface of the second layer.

2. A method as claimed in claim 1 in which the coarse resist material is a photoresist.

3. A method as claimed in claim 1 or 2 in which the initial resist pattern is of bismuth oxide.

4. A method of forming a bubble memory chip substantially as herein described with reference to the accompanying drawings.

5. A bubble memory chip when made by the method claimed in any preceding claim.