JPH0315346B2 - - Google Patents

Info

Publication number
JPH0315346B2
JPH0315346B2 JP58187930A JP18793083A JPH0315346B2 JP H0315346 B2 JPH0315346 B2 JP H0315346B2 JP 58187930 A JP58187930 A JP 58187930A JP 18793083 A JP18793083 A JP 18793083A JP H0315346 B2 JPH0315346 B2 JP H0315346B2
Authority
JP
Japan
Prior art keywords
semiconductor
region
semiconductor region
diffusion
bipolar transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58187930A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6080267A (ja
Inventor
Hiroshi Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=16214675&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JPH0315346(B2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP58187930A priority Critical patent/JPS6080267A/ja
Priority to DE8484111849T priority patent/DE3476493D1/de
Priority to EP84111849A priority patent/EP0139266B1/en
Publication of JPS6080267A publication Critical patent/JPS6080267A/ja
Priority to US07/096,241 priority patent/US4818720A/en
Priority to US07/306,393 priority patent/US4965220A/en
Publication of JPH0315346B2 publication Critical patent/JPH0315346B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10P32/171—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H10P32/1414—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/01—Bipolar transistors-ion implantation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/032—Diffusion length
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/037—Diffusion-deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/038—Diffusions-staged
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/082—Ion implantation FETs/COMs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/123—Polycrystalline diffuse anneal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/124—Polycrystalline emitter

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
JP58187930A 1983-10-07 1983-10-07 半導体集積回路装置の製造方法 Granted JPS6080267A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP58187930A JPS6080267A (ja) 1983-10-07 1983-10-07 半導体集積回路装置の製造方法
DE8484111849T DE3476493D1 (en) 1983-10-07 1984-10-03 A semiconductor integrated circuit device comprising an mos transistor and a bipolar transistor and a manufacturing method of the same
EP84111849A EP0139266B1 (en) 1983-10-07 1984-10-03 A semiconductor integrated circuit device comprising an mos transistor and a bipolar transistor and a manufacturing method of the same
US07/096,241 US4818720A (en) 1983-10-07 1987-09-08 Method for manufacturing a BiCMOS device
US07/306,393 US4965220A (en) 1983-10-07 1989-02-06 Method of manufacturing a semiconductor integrated circuit device comprising an MOS transistor and a bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58187930A JPS6080267A (ja) 1983-10-07 1983-10-07 半導体集積回路装置の製造方法

Publications (2)

Publication Number Publication Date
JPS6080267A JPS6080267A (ja) 1985-05-08
JPH0315346B2 true JPH0315346B2 (enExample) 1991-02-28

Family

ID=16214675

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58187930A Granted JPS6080267A (ja) 1983-10-07 1983-10-07 半導体集積回路装置の製造方法

Country Status (4)

Country Link
US (2) US4818720A (enExample)
EP (1) EP0139266B1 (enExample)
JP (1) JPS6080267A (enExample)
DE (1) DE3476493D1 (enExample)

Families Citing this family (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280188A (en) * 1985-03-07 1994-01-18 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor integrated circuit device having at least one bipolar transistor and a plurality of MOS transistors
FR2581248B1 (fr) * 1985-04-26 1987-05-29 Efcis Procede de fabrication de transistors a effet de champ et transistors bipolaires lateraux sur un meme substrat
US4682409A (en) * 1985-06-21 1987-07-28 Advanced Micro Devices, Inc. Fast bipolar transistor for integrated circuit structure and method for forming same
JPS6231151A (ja) * 1985-08-02 1987-02-10 Nec Corp 半導体集積回路装置
DE3676781D1 (de) * 1985-09-13 1991-02-14 Siemens Ag Integrierte bipolar- und komplementaere mos-transistoren auf einem gemeinsamen substrat enthaltende schaltung und verfahren zu ihrer herstellung.
US4808548A (en) * 1985-09-18 1989-02-28 Advanced Micro Devices, Inc. Method of making bipolar and MOS devices on same integrated circuit substrate
US4922318A (en) * 1985-09-18 1990-05-01 Advanced Micro Devices, Inc. Bipolar and MOS devices fabricated on same integrated circuit substrate
JPH0628296B2 (ja) * 1985-10-17 1994-04-13 日本電気株式会社 半導体装置の製造方法
JPS62104068A (ja) * 1985-10-30 1987-05-14 Mitsubishi Electric Corp 半導体集積回路装置
US4752589A (en) * 1985-12-17 1988-06-21 Siemens Aktiengesellschaft Process for the production of bipolar transistors and complementary MOS transistors on a common silicon substrate
JPH0622273B2 (ja) * 1986-02-28 1994-03-23 キヤノン株式会社 半導体装置の製造方法
DE3745036C2 (de) * 1986-02-28 1996-05-15 Canon Kk Verfahren zum Herstellen einer Halbleitervorrichtung
DE3706278A1 (de) * 1986-02-28 1987-09-03 Canon Kk Halbleitervorrichtung und herstellungsverfahren hierfuer
DE3680520D1 (de) * 1986-03-22 1991-08-29 Itt Ind Gmbh Deutsche Verfahren zum herstellen einer monolithisch integrierten schaltung mit mindestens einem bipolaren planartransistor.
US5063168A (en) * 1986-07-02 1991-11-05 National Semiconductor Corporation Process for making bipolar transistor with polysilicon stringer base contact
EP0250721B1 (de) * 1986-07-04 1993-09-15 Siemens Aktiengesellschaft Integrierte Bipolar- und komplementäre MOS-Transistoren auf einem gemeinsamen Substrat enthaltende Schaltung und Verfahren zu ihrer Herstellung
US5023193A (en) * 1986-07-16 1991-06-11 National Semiconductor Corp. Method for simultaneously fabricating bipolar and complementary field effect transistors using a minimal number of masks
EP0256315B1 (de) * 1986-08-13 1992-01-29 Siemens Aktiengesellschaft Integrierte Bipolar- und komplementäre MOS-Transistoren auf einem gemeinsamen Substrat enthaltende Schaltung und Verfahren zu ihrer Herstellung
JP2635961B2 (ja) * 1986-09-26 1997-07-30 株式会社日立製作所 半導体装置の製造方法
JPS63132470A (ja) * 1986-11-21 1988-06-04 Mitsubishi Electric Corp 半導体集積回路装置
EP0270703B1 (de) * 1986-12-12 1991-12-18 Deutsche ITT Industries GmbH Verfahren zum Herstellen einer monolithisch integrierten Schaltung mit mindestens einem bipolaren Planartransistor
JP2654011B2 (ja) * 1987-03-31 1997-09-17 株式会社東芝 半導体装置の製造方法
EP0290268A3 (en) * 1987-05-08 1990-01-10 Raytheon Company Method of forming a bipolar transistor
JPS63304657A (ja) * 1987-06-04 1988-12-12 Fujitsu Ltd 半導体装置の製造方法
KR900001062B1 (ko) * 1987-09-15 1990-02-26 강진구 반도체 바이 씨 모오스 장치의 제조방법
JPH0666423B2 (ja) * 1987-10-21 1994-08-24 日本電気株式会社 半導体装置
KR900005353B1 (ko) * 1987-11-03 1990-07-27 삼성전자 주식회사 반도체 장치의 제조방법
US5173760A (en) * 1987-11-03 1992-12-22 Samsung Electronics Co., Ltd. BiCMOS semiconductor device
US4994887A (en) * 1987-11-13 1991-02-19 Texas Instruments Incorporated High voltage merged bipolar/CMOS technology
JPH01140761A (ja) * 1987-11-27 1989-06-01 Nec Corp 半導体装置
US5093707A (en) * 1988-04-27 1992-03-03 Kabushiki Kaisha Toshiba Semiconductor device with bipolar and cmos transistors
US4943536A (en) * 1988-05-31 1990-07-24 Texas Instruments, Incorporated Transistor isolation
US5047357A (en) * 1989-02-03 1991-09-10 Texas Instruments Incorporated Method for forming emitters in a BiCMOS process
US5206182A (en) * 1989-06-08 1993-04-27 United Technologies Corporation Trench isolation process
JPH0728371Y2 (ja) * 1989-06-12 1995-06-28 リョービ株式会社 用心錠
JPH0330334A (ja) * 1989-06-28 1991-02-08 Toshiba Corp バイポーラトランジスタの製造方法
US5171702A (en) * 1989-07-21 1992-12-15 Texas Instruments Incorporated Method for forming a thick base oxide in a BiCMOS process
JPH0362568A (ja) * 1989-07-31 1991-03-18 Hitachi Ltd 半導体装置の製造方法
US4960726A (en) * 1989-10-19 1990-10-02 International Business Machines Corporation BiCMOS process
US5182225A (en) * 1990-01-10 1993-01-26 Microunity Systems Engineering, Inc. Process for fabricating BICMOS with hypershallow junctions
US4983531A (en) * 1990-02-12 1991-01-08 Motorola, Inc. Method of fabricating a single polysilicon bipolar transistor which is compatible with a method of fabricating CMOS transistors
US5102811A (en) * 1990-03-20 1992-04-07 Texas Instruments Incorporated High voltage bipolar transistor in BiCMOS
US5231042A (en) * 1990-04-02 1993-07-27 National Semiconductor Corporation Formation of silicide contacts using a sidewall oxide process
US5219784A (en) * 1990-04-02 1993-06-15 National Semiconductor Corporation Spacer formation in a bicmos device
JP2950577B2 (ja) * 1990-04-27 1999-09-20 沖電気工業株式会社 ＢｉＣＭＯＳ半導体集積回路の製造方法
US5281544A (en) * 1990-07-23 1994-01-25 Seiko Epson Corporation Method of manufacturing planar type polar transistors and combination bipolar/MIS type transistors
EP0486134B1 (en) * 1990-11-14 1997-06-18 Samsung Semiconductor, Inc. A biCMOS process with low base recombination current bipolar transistors
JPH0547913A (ja) * 1991-08-12 1993-02-26 Sharp Corp 半導体装置の製造方法
US5258317A (en) * 1992-02-13 1993-11-02 Integrated Device Technology, Inc. Method for using a field implant mask to correct low doping levels at the outside edges of the base in a walled-emitter transistor structure
US5648288A (en) * 1992-03-20 1997-07-15 Siliconix Incorporated Threshold adjustment in field effect semiconductor devices
JP3175973B2 (ja) * 1992-04-28 2001-06-11 株式会社東芝 半導体装置およびその製造方法
US5557131A (en) * 1992-10-19 1996-09-17 At&T Global Information Solutions Company Elevated emitter for double poly BICMOS devices
US5516718A (en) * 1992-12-07 1996-05-14 At&T Global Information Solutions Company Method of making BI-CMOS integrated circuit having a polysilicon emitter
US6249030B1 (en) 1992-12-07 2001-06-19 Hyundai Electronics Industries Co., Ltd. BI-CMOS integrated circuit
US6350640B1 (en) 1994-07-18 2002-02-26 Intersil Americas Inc. CMOS integrated circuit architecture incorporating deep implanted emitter region to form auxiliary bipolar transistor
JPH08172100A (ja) * 1994-12-16 1996-07-02 Mitsubishi Electric Corp 半導体装置
JP3444002B2 (ja) * 1995-02-14 2003-09-08 ソニー株式会社 半導体装置およびその製造方法
JP3006825B2 (ja) * 1995-03-30 2000-02-07 日本電気株式会社 半導体集積回路装置の製造方法
JP2776350B2 (ja) * 1995-12-18 1998-07-16 日本電気株式会社 半導体集積回路装置の製造方法
US6245604B1 (en) * 1996-01-16 2001-06-12 Micron Technology Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits
JP3006531B2 (ja) * 1997-03-24 2000-02-07 日本電気株式会社 半導体装置の製造方法
KR100425582B1 (ko) * 2001-11-22 2004-04-06 한국전자통신연구원 얕은 소오스/드레인 접합 영역을 갖는 모스 트랜지스터의제조방법
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation

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JPS56169359A (en) * 1980-05-30 1981-12-26 Ricoh Co Ltd Semiconductor integrated circuit device
JPS5775453A (en) * 1980-10-29 1982-05-12 Fujitsu Ltd Semiconductor device and manufacture thereof
DE3205022A1 (de) * 1981-02-14 1982-09-16 Mitsubishi Denki K.K., Tokyo Verfahren zum herstellen einer integrierten halbleiterschaltung
JPS6052591B2 (ja) * 1981-02-14 1985-11-20 三菱電機株式会社 半導体集積回路装置の製造方法
EP0067661A1 (en) * 1981-06-15 1982-12-22 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JPS5866359A (ja) * 1981-09-28 1983-04-20 Fujitsu Ltd 半導体装置の製造方法
JPS5866352A (ja) * 1981-10-16 1983-04-20 Seiko Instr & Electronics Ltd 半導体集積回路とその製造方法
DE3175429D1 (en) * 1981-11-28 1986-11-06 Itt Ind Gmbh Deutsche Process for producing a monolithic integrated circuit having at least one pair of complementary field-effect transistors and at least one bipolar transistor
JPS58225663A (ja) * 1982-06-23 1983-12-27 Toshiba Corp 半導体装置の製造方法
JPS5975659A (ja) * 1982-10-22 1984-04-28 Fujitsu Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
DE3476493D1 (en) 1989-03-02
EP0139266B1 (en) 1989-01-25
EP0139266A3 (en) 1986-01-22
EP0139266A2 (en) 1985-05-02
US4818720A (en) 1989-04-04
US4965220A (en) 1990-10-23
JPS6080267A (ja) 1985-05-08

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