JP7462653B2 - 高電圧許容型高速インターフェースのための低漏れ電流による電気的過負荷保護 - Google Patents
高電圧許容型高速インターフェースのための低漏れ電流による電気的過負荷保護 Download PDFInfo
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Description
低漏れ電流と、低静電容量と、を伴う電気過剰応力保護が提供される。特定の実施形態では、半導体チップは、チップの電気的インターフェースのパッドで電気過剰応力から保護するための電力クランプを含む。電力クランプは、少なくとも1つの隔離遮断電圧デバイスによってパッドから隔離されている。パッドと電力クランプとの間に隔離遮断電圧デバイスを介在させることによって、パッドは電力クランプの静電容量から遮蔽され、および/またはパッドにおける漏れ電流の量が低減される。よって、電気インターフェースは、半導体チップを損傷する可能性のある電気過剰応力の存在下で堅牢性を維持しながら、高速、迅速な信号伝達、および/または低静電損失で動作することができる。
図11は、一実施形態による双方向保護回路305の概略図である。双方向保護回路305は、順方向保護SCR301と、逆保護SCR302と、を含む。SCRは、サイリスタとも呼ばれる。図示の実施形態では、双方向保護回路305は、第1のパッド303(この例ではAIO)と第2のパッド304(この例では低電力またはVSS)との間に電気的に接続されている。
上記のスキームを採用するデバイスは、様々な電子システムに実装することができる。電子システムの例としては、家庭用電子製品、家庭用電子製品の部品、電子試験機器、通信インフラストラクチャアプリケーションなどが挙げられるが、これらに限定されない。さらに、電子システムは、通信、産業、医療、および自動車用途のためのものを含む未完成製品を含み得る。
前述の説明は、共に「接続されている」または「結合されている」要素または特徴を指す場合がある。本明細書で使用される場合、別段の明示的な記載がない限り、「接続されている」とは、1つの要素/特徴が、必ずしも機械的にではなく、別の要素/特徴に直接的または間接的に接続されていることを意味する。同様に、別段の明示的な記載がない限り、「結合されている」とは、1つの要素/特徴が、必ずしも機械的にではなく、別の要素/特徴に直接的または間接的に結合されていることを意味する。したがって、図に示される様々な概略図は、要素および構成要素の例示的な配置を図示しているが、追加の介在要素、デバイス、特徴、または構成要素が、実際の実施形態に存在し得る(図示の回路の機能性が悪影響を受けないことを前提とする)。
1 チップピンまたはパッド
2 内部回路
3 隔離ダイオード
9 電力クランプ
Claims (20)
- 低漏れ電流と、高電圧耐性電気過剰応力保護と、を伴う、半導体ダイであって、前記半導体ダイが、
信号パッドと、
前記信号パッドに電気的に接続された内部回路と、
隔離されたノードと基準ノードとの間に電気的に接続された電力クランプと、
前記信号パッドと前記隔離されたノードとの間に電気的に接続された1つ以上の隔離遮断電圧デバイスであって、前記1つ以上の隔離遮断電圧デバイスが、前記電力クランプの静電容量から前記信号パッドを隔離するように動作可能である、隔離遮断電圧デバイスと、
前記電力クランプと並列に接続され、前記基準ノードに結合されたアノードおよび前記隔離されたノードに結合されたカソードを有するクランプ迂回ダイオードと、
前記隔離されたノードに結合されたアノードおよび前記信号パッドに結合されたカソードを有する第1の逆保護ダイオードと、を備える、半導体ダイ。 - 前記1つ以上の隔離遮断電圧デバイスが、少なくとも1つのゲートダイオードを備える、請求項1に記載の半導体ダイ。
- 前記少なくとも1つのゲートダイオードが、半導体領域と、前記半導体領域に形成されたp型活性(P+)アノード領域と、前記半導体領域に形成されたn型活性(N+)カソード領域と、前記P+アノード領域と前記N+カソード領域との間の前記半導体領域上の金属ゲートと、を備える、請求項2に記載の半導体ダイ。
- 前記少なくとも1つのゲートダイオードが、n型ウェルと、前記n型ウェルに内に形成されたP+アノード領域と、前記n型ウェルに形成されたN+カソード領域と、前記P+アノード領域と前記N+カソード領域との間の前記n型ウェル上の金属ゲートと、前記n型ウェルの周辺を囲繞するP+リングと、を備える、請求項2に記載の半導体ダイ。
- 前記少なくとも1つのゲートダイオードが、p型ウェルと、p型基板内に形成され、前記p型基板から前記p型ウェルを電気的に隔離するように動作可能なn型タブと、前記p型ウェル内に形成されたP+アノード領域と、前記p型ウェル内に形成されたN+カソード領域と、前記P+アノード領域と前記N+カソード領域との間の前記p型ウェル上の金属ゲートと、を備える、請求項2に記載の半導体ダイ。
- 前記1つ以上の隔離遮断電圧デバイスが、少なくとも2つの直列の隔離ダイオードを含む、請求項1に記載の半導体ダイ。
- 前記電力クランプが、能動的に制御されている、請求項1に記載の半導体ダイ。
- 前記電力クランプが、検出回路と、バイアス回路と、クランプとを備え、前記検出回路が、前記隔離されたノードにおいて電気過剰応力事象を検出することに応答して、検出信号を起動し、前記バイアス回路が、前記検出信号の起動に応答して、前記クランプをオンにする、請求項7に記載の半導体ダイ。
- 前記信号パッドが、高精細マルチメディアインターフェース(HDMI(登録商標))の家電制御(CEC)パッドである、請求項1に記載の半導体ダイ。
- 前記電力クランプが、前記信号パッドの電圧を増加させる電気過剰応力に応答して起動するように構成され、前記半導体ダイが、前記信号パッドに電気的に接続されており、かつ前記信号パッドの前記電圧を減少させる電気過剰応力に応答して起動するように構成されている、逆保護回路をさらに備える、請求項1に記載の半導体ダイ。
- 前記逆保護回路が、ダイオードまたはSCRのうちの少なくとも1つを含む、請求項10に記載の半導体ダイ。
- 前記逆保護回路が、2つ以上の直列のゲートダイオードを含む、請求項11または請求項10に記載の半導体ダイ。
- 低静電容量と、低漏れ電流と、を伴う、電気過剰応力保護を提供する方法であって、前記方法は、
半導体ダイの信号パッドにおいて、電気過剰応力事象を受け取ることと、
隔離されたノードと基準ノードとの間に電気的に接続されている電力クランプを使用して、前記電気過剰応力事象を放電することと、
前記信号パッドと前記隔離されたノードとの間に介在する少なくとも1つの遮断電圧デバイスを使用して、前記電力クランプの静電容量から前記信号パッドを隔離することと、
クランプ迂回ダイオードおよび第1の逆保護ダイオードを使用して前記電力クランプのための迂回経路を提供することであって、前記クランプ迂回ダイオードが前記電力クランプと並列に接続され、前記基準ノードに結合されたアノードおよび前記隔離されたノードに結合されたカソードを有し、前記第1の逆保護ダイオードが、前記隔離されたノードに結合されたアノードおよび前記信号パッドに結合されたカソードを有する、前記提供することと、を含む、方法。 - 前記電力クランプの前記静電容量から前記信号パッドを隔離することが、少なくとも1つのゲートダイオードを使用して隔離を提供することを含む、請求項13に記載の方法。
- 前記電力クランプを使用して前記電気過剰応力事象を放電することが、前記隔離されたノードにおいて前記電気過剰応力事象を検出することに応答して、検出信号を起動することと、前記検出信号の起動に応答してクランプをオンすることと、を含む、請求項13に記載の方法。
- 2つ以上の直列のゲートダイオードを含む逆保護回路を使用して信号を保護することをさらに含む、請求項13に記載の方法。
- 前記クランプが、前記隔離されたノードと前記基準ノードとの間に直列に接続された第1のクランプ電界効果トランジスタ(FET)および第2のクランプFETを含む、請求項8に記載の半導体ダイ。
- 前記バイアス回路が、前記隔離されたノードと前記基準ノードとの間に接続された電圧分割器をさらに含み、中電圧を前記第1のクランプFETのゲートに提供するように構成され、前記バイアス回路が、前記検出信号の起動に応答して前記中電圧をオーバーライドするように構成された、請求項17に記載の半導体ダイ。
- 前記第1の逆保護ダイオードのカソードに結合されたアノードと、前記信号パッドに結合されたカソードとを有する第2の逆保護ダイオードをさらに備える、請求項1に記載の半導体ダイ。
- 前記1つ以上の隔離遮断電圧デバイスが、前記隔離されたノードに結合されたアノード領域と、前記信号パッドに結合されたカソード領域とを有するゲートされたダイオードを備え、前記アノード領域および前記カソード領域が、半導体レイアウト内に形成され、前記カソード領域が、前記半導体レイアウトの第1の角で接触され、前記カソード領域が、前記第1の角と反対側の前記半導体レイアウトの第2の角で接触される、請求項1に記載の半導体ダイ。
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