JP7455951B2 - チップパッケージ構造、およびチップパッケージ構造の製造方法 - Google Patents

チップパッケージ構造、およびチップパッケージ構造の製造方法 Download PDF

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JP7455951B2
JP7455951B2 JP2022502145A JP2022502145A JP7455951B2 JP 7455951 B2 JP7455951 B2 JP 7455951B2 JP 2022502145 A JP2022502145 A JP 2022502145A JP 2022502145 A JP2022502145 A JP 2022502145A JP 7455951 B2 JP7455951 B2 JP 7455951B2
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chips
layer
package structure
vertical conductive
chip
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JP2022540260A (ja
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シンル・ゼン
ペン・チェン
ホウデ・ジョウ
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
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  • Engineering & Computer Science (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
JP2022502145A 2019-11-29 2019-11-29 チップパッケージ構造、およびチップパッケージ構造の製造方法 Active JP7455951B2 (ja)

Priority Applications (2)

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