CN113964102A - 芯片封装结构及其制造方法 - Google Patents

芯片封装结构及其制造方法 Download PDF

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Publication number
CN113964102A
CN113964102A CN202111230273.1A CN202111230273A CN113964102A CN 113964102 A CN113964102 A CN 113964102A CN 202111230273 A CN202111230273 A CN 202111230273A CN 113964102 A CN113964102 A CN 113964102A
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chip
layer
chips
vertical conductive
package structure
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CN202111230273.1A
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English (en)
Chinese (zh)
Inventor
曾心如
陈鹏
周厚德
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202111230273.1A priority Critical patent/CN113964102A/zh
Publication of CN113964102A publication Critical patent/CN113964102A/zh
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  • Engineering & Computer Science (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
CN202111230273.1A 2019-11-29 2019-11-29 芯片封装结构及其制造方法 Pending CN113964102A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111230273.1A CN113964102A (zh) 2019-11-29 2019-11-29 芯片封装结构及其制造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN202111230273.1A CN113964102A (zh) 2019-11-29 2019-11-29 芯片封装结构及其制造方法
PCT/CN2019/121821 WO2021102876A1 (en) 2019-11-29 2019-11-29 Chip package structure and manufacturing method thereof
CN201980003370.1A CN111066144B (zh) 2019-11-29 2019-11-29 芯片封装结构及其制造方法

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