KR102902502B1 - 칩 패키지 구조체 및 그 제조 방법 - Google Patents

칩 패키지 구조체 및 그 제조 방법

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Publication number
KR102902502B1
KR102902502B1 KR1020247014843A KR20247014843A KR102902502B1 KR 102902502 B1 KR102902502 B1 KR 102902502B1 KR 1020247014843 A KR1020247014843 A KR 1020247014843A KR 20247014843 A KR20247014843 A KR 20247014843A KR 102902502 B1 KR102902502 B1 KR 102902502B1
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South Korea
Prior art keywords
layer
vertical conductive
package structure
chip package
chip
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Application number
KR1020247014843A
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English (en)
Korean (ko)
Other versions
KR20240068079A (ko
Inventor
신뤼 쩡
펑 천
허우더 저우
Original Assignee
양쯔 메모리 테크놀로지스 씨오., 엘티디.
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Application filed by 양쯔 메모리 테크놀로지스 씨오., 엘티디. filed Critical 양쯔 메모리 테크놀로지스 씨오., 엘티디.
Priority to KR1020257042024A priority Critical patent/KR20260007629A/ko
Publication of KR20240068079A publication Critical patent/KR20240068079A/ko
Application granted granted Critical
Publication of KR102902502B1 publication Critical patent/KR102902502B1/ko
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00Arrangements for protection of devices
    • H10W42/121Arrangements for protection of devices protecting against mechanical damage
    • H01L25/0657
    • H01L21/56
    • H01L21/6835
    • H01L23/3135
    • H01L23/49811
    • H01L23/5389
    • H01L23/562
    • H01L24/19
    • H01L24/92
    • H01L25/03
    • H01L25/50
    • HELECTRICITY
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    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698Local interconnections
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
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    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
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    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
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    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63Vias, e.g. via plugs
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    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
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    • H10W74/00Encapsulations, e.g. protective coatings
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    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
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    • H10W74/00Encapsulations, e.g. protective coatings
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    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
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    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
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    • H10P72/74Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
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    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7436Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to support a device or a wafer when forming electrical connections thereto
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    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
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    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
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    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
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    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
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    • H10W74/131Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
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    • H10W90/732Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
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    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips

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  • Engineering & Computer Science (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
KR1020247014843A 2019-11-29 2019-11-29 칩 패키지 구조체 및 그 제조 방법 Active KR102902502B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020257042024A KR20260007629A (ko) 2019-11-29 2019-11-29 칩 패키지 구조체 및 그 제조 방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/CN2019/121821 WO2021102876A1 (en) 2019-11-29 2019-11-29 Chip package structure and manufacturing method thereof
KR1020227000528A KR102664356B1 (ko) 2019-11-29 2019-11-29 칩 패키지 구조체 및 그 제조 방법

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Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11469215B2 (en) * 2016-07-13 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
DE112016007295T5 (de) * 2016-10-01 2019-06-19 Intel Corporation Elektronisches bauelementgehäuse
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
JP2022002249A (ja) * 2020-06-19 2022-01-06 キオクシア株式会社 半導体装置およびその製造方法
KR102904560B1 (ko) * 2020-08-19 2025-12-26 에스케이하이닉스 주식회사 수직 인터커넥터를 포함하는 반도체 패키지
US11289130B2 (en) * 2020-08-20 2022-03-29 Macronix International Co., Ltd. Memory device
CN112614830A (zh) * 2020-11-30 2021-04-06 华为技术有限公司 一种封装模组及电子设备
JP2022098115A (ja) * 2020-12-21 2022-07-01 キオクシア株式会社 半導体装置およびその製造方法
US12266636B2 (en) 2020-12-23 2025-04-01 Stmicroelectronics Pte Ltd Stacked die package including a multi-contact interconnect
CN114715834B (zh) * 2021-01-05 2025-04-08 华邦电子股份有限公司 封装结构及其制造方法
KR102920160B1 (ko) * 2021-01-20 2026-02-02 에스케이하이닉스 주식회사 수직 인터커넥터를 포함하는 반도체 패키지
JP2022112923A (ja) * 2021-01-22 2022-08-03 キオクシア株式会社 半導体装置およびその製造方法
CN118366875A (zh) * 2021-01-26 2024-07-19 长江存储科技有限责任公司 基板结构及其制造和封装方法
CN113380762B (zh) * 2021-06-04 2022-08-30 长江存储科技有限责任公司 芯片封装结构及其制造方法
US11908838B2 (en) * 2021-08-26 2024-02-20 Taiwan Semiconductor Manufacturing Company Limited Three-dimensional device structure including embedded integrated passive device and methods of making the same
KR20230033362A (ko) 2021-09-01 2023-03-08 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
CN121510594A (zh) * 2021-12-28 2026-02-10 长江存储科技有限责任公司 存储器系统封装结构及制造方法
EP4437588A4 (en) * 2021-12-28 2025-08-27 Yangtze Memory Tech Co Ltd MEMORY SYSTEM PACKAGING STRUCTURE AND FORMING METHOD THEREOF
KR20230164794A (ko) 2022-05-25 2023-12-05 삼성전자주식회사 반도체 패키지
KR20230172743A (ko) * 2022-06-16 2023-12-26 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
KR20240062200A (ko) * 2022-10-28 2024-05-09 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
CN118451547A (zh) * 2022-11-03 2024-08-06 英诺赛科(苏州)半导体有限公司 半导体封装结构及其制造方法
US20240260281A1 (en) * 2023-01-26 2024-08-01 Micron Technology, Inc. Molded memory assemblies for a system in package semiconductor device assembly
CN118782602A (zh) * 2023-03-30 2024-10-15 长鑫存储技术有限公司 芯片堆叠封装结构及芯片堆叠封装方法
KR20240149904A (ko) * 2023-04-03 2024-10-15 양쯔 메모리 테크놀로지스 씨오., 엘티디. 집적 패키지 디바이스, 그 제조 방법 및 메모리 시스템
KR102950559B1 (ko) 2024-05-31 2026-04-10 주식회사 에이팩트 반도체 패키지 및 그 제조 방법
US20260033378A1 (en) * 2024-07-23 2026-01-29 Micron Technology, Inc. Stacked die substrate-less semiconductor package

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100193930A1 (en) * 2009-02-02 2010-08-05 Samsung Electronics Co., Ltd. Multi-chip semiconductor devices having conductive vias and methods of forming the same
CN110060984A (zh) * 2018-01-18 2019-07-26 爱思开海力士有限公司 包括多芯片层叠物的半导体封装及其制造方法

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5251497A (en) * 1975-10-24 1977-04-25 Bridgestone Corp Improved process for preparing flame-retarded polyurethane foam having a low smoking property
JPH05251497A (ja) * 1992-03-09 1993-09-28 Nec Corp 半導体装置
JP3727272B2 (ja) 2002-01-15 2005-12-14 沖電気工業株式会社 半導体装置及び半導体装置の製造方法
US8710675B2 (en) * 2006-02-21 2014-04-29 Stats Chippac Ltd. Integrated circuit package system with bonding lands
KR20090055316A (ko) * 2007-11-28 2009-06-02 삼성전자주식회사 반도체 패키지와, 이를 구비하는 전자 기기 및 반도체패키지의 제조방법
TW200939407A (en) * 2008-03-13 2009-09-16 Chipmos Technologies Inc Multi-chip package structure and the method thereof
KR20100112446A (ko) * 2009-04-09 2010-10-19 삼성전자주식회사 적층형 반도체 패키지 및 그 제조 방법
KR101053140B1 (ko) 2009-04-10 2011-08-02 주식회사 하이닉스반도체 적층 반도체 패키지
KR101624973B1 (ko) * 2009-09-23 2016-05-30 삼성전자주식회사 패키지 온 패키지 타입의 반도체 패키지 및 그 제조방법
KR101604605B1 (ko) * 2009-09-24 2016-03-21 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
KR101686553B1 (ko) * 2010-07-12 2016-12-14 삼성전자 주식회사 반도체 패키지 및 패키지 온 패키지
KR101738103B1 (ko) * 2010-09-10 2017-05-22 삼성전자주식회사 3차원 반도체 기억 소자
KR20120035297A (ko) * 2010-10-05 2012-04-16 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US8970046B2 (en) * 2011-07-18 2015-03-03 Samsung Electronics Co., Ltd. Semiconductor packages and methods of forming the same
KR101831938B1 (ko) * 2011-12-09 2018-02-23 삼성전자주식회사 팬 아웃 웨이퍼 레벨 패키지의 제조 방법 및 이에 의해 제조된 팬 아웃 웨이퍼 레벨 패키지
KR102110405B1 (ko) * 2013-11-01 2020-05-14 에스케이하이닉스 주식회사 반도체 패키지 및 그 제조방법
KR102143653B1 (ko) * 2013-12-31 2020-08-11 에스케이하이닉스 주식회사 전자기 간섭 차폐부를 갖는 반도체 패키지 및 제조방법
KR20150101762A (ko) 2014-02-27 2015-09-04 에스케이하이닉스 주식회사 반도체 장치
US20150262902A1 (en) * 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
KR102299673B1 (ko) * 2014-08-11 2021-09-10 삼성전자주식회사 반도체 패키지
KR20160055100A (ko) * 2014-10-03 2016-05-17 인텔 코포레이션 수직 기둥들을 갖는 오버랩핑 적층형 다이 패키지
TWI582917B (zh) * 2015-07-29 2017-05-11 力成科技股份有限公司 以封膠體取代基板核心之多晶片封裝構造
US10396055B2 (en) * 2015-09-25 2019-08-27 Intel Corporation Method, apparatus and system to interconnect packaged integrated circuit dies
TWI604591B (zh) * 2015-12-23 2017-11-01 力成科技股份有限公司 薄型扇出式多晶片堆疊封裝構造及其製造方法
US9984998B2 (en) * 2016-01-06 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Devices employing thermal and mechanical enhanced layers and methods of forming same
TWI606563B (zh) * 2016-04-01 2017-11-21 力成科技股份有限公司 薄型晶片堆疊封裝構造及其製造方法
TWI567897B (zh) * 2016-06-02 2017-01-21 力成科技股份有限公司 薄型扇出式多晶片堆疊封裝構造與製造方法
CN107579061B (zh) * 2016-07-04 2020-01-07 晟碟信息科技(上海)有限公司 包含互连的叠加封装体的半导体装置
US11469215B2 (en) * 2016-07-13 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US20200066701A1 (en) * 2016-09-28 2020-02-27 Intel Corporation Stacked chip package having substrate interposer and wirebonds
US11056465B2 (en) * 2016-12-29 2021-07-06 Intel Corporation Semiconductor package having singular wire bond on bonding pads
TWI613772B (zh) 2017-01-25 2018-02-01 Powertech Technology Inc. 薄型扇出式多晶片堆疊封裝構造
TWI638439B (zh) * 2017-04-17 2018-10-11 Powertech Technology Inc. 半導體封裝結構及其製造方法
CN107731761A (zh) * 2017-09-30 2018-02-23 睿力集成电路有限公司 底部半导体封装件及其制造方法
CN109979907B (zh) * 2017-12-28 2021-01-08 瀚宇彩晶股份有限公司 电子产品
DE112017008335T5 (de) * 2017-12-28 2020-09-03 Intel Corporation Multi-Die, Vertikal-Draht-Package-in-Package-Vorrichtung und Verfahren zum Herstellen desselben
KR102173811B1 (ko) * 2018-05-16 2020-11-04 주식회사 네패스 패키지 유닛 및 멀티 스택 패키지
CN110010481B (zh) * 2018-10-10 2020-12-29 浙江集迈科微电子有限公司 一种密闭型系统级光电模块封装方式和工艺
CN109585431A (zh) * 2018-12-17 2019-04-05 华进半导体封装先导技术研发中心有限公司 一种Flash芯片堆叠的扇出封装结构及其制造方法
US11948917B2 (en) * 2019-04-23 2024-04-02 Intel Corporation Die over mold stacked semiconductor package
KR102774713B1 (ko) * 2019-09-06 2025-03-04 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
KR102786360B1 (ko) * 2019-09-25 2025-03-26 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
KR102710260B1 (ko) * 2019-10-01 2024-09-27 에스케이하이닉스 주식회사 적층 반도체 칩을 포함하는 반도체 패키지
KR102610247B1 (ko) * 2020-11-11 2023-12-06 주식회사 네패스 반도체 패키지 및 이의 제조 방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100193930A1 (en) * 2009-02-02 2010-08-05 Samsung Electronics Co., Ltd. Multi-chip semiconductor devices having conductive vias and methods of forming the same
CN110060984A (zh) * 2018-01-18 2019-07-26 爱思开海力士有限公司 包括多芯片层叠物的半导体封装及其制造方法

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