CN105390467B - 芯片堆叠半导体封装件 - Google Patents
芯片堆叠半导体封装件 Download PDFInfo
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- CN105390467B CN105390467B CN201510523211.8A CN201510523211A CN105390467B CN 105390467 B CN105390467 B CN 105390467B CN 201510523211 A CN201510523211 A CN 201510523211A CN 105390467 B CN105390467 B CN 105390467B
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Classifications
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Abstract
可提供一种芯片堆叠半导体封装件,该芯片堆叠半导体封装件包括:第一芯片,具有多个第一真实凸点焊盘和多个第一虚设凸点焊盘;第二芯片,在第一芯片上,第二芯片包括多个真实凸点和多个桥接虚设凸点,所述多个真实凸点电连接到所述多个第一真实凸点焊盘,所述多个桥接虚设凸点连接到所述多个第一虚设凸点焊盘;密封构件,密封第一芯片和第二芯片。
Description
本申请要求于2014年8月22日在韩国知识产权局提交的第10-2014-0109958号韩国专利申请的优先权,该申请的公开内容通过引用全部包含于此。
技术领域
本发明构思涉及半导体封装件,更具体地,涉及堆叠有多个芯片的芯片堆叠半导体封装件。
背景技术
半导体制造方的目的是以低成本制造小型、多功能和高容量的半导体器件。半导体封装技术是有助于实现这各种目的的技术之一。具体地,提出堆叠有多个芯片的芯片堆叠半导体封装件来实现上述目的。
发明内容
本发明构思中的一些提供了堆叠有多个芯片的小型、多功能和高容量的芯片堆叠半导体封装件。
根据示例实施例,一种芯片堆叠半导体封装件包括:第一芯片,包括多个第一真实凸点焊盘和多个第一虚设凸点焊盘;第二芯片,在第一芯片上,第二芯片包括多个真实凸点和多个桥接虚设凸点,所述多个真实凸点电连接到所述多个第一真实凸点焊盘,所述多个桥接虚设凸点连接到所述多个第一虚设凸点焊盘;密封构件,密封第一芯片和第二芯片。
在一些示例实施例中,第一芯片还可包括第一芯片主体,所述多个第一真实凸点焊盘可以在所述第一芯片主体的上表面上,多个第一真实硅穿通孔可以在第一芯片主体中并且电连接到多个第一真实凸点焊盘。
在一些示例实施例中,所述多个第一虚设凸点焊盘可以在第一芯片主体的上表面上,多个虚设硅穿通孔可以在第一芯片主体中并且可电连接到所述多个第一虚设凸点焊盘。
在一些示例实施例中,多个连接构件可以在第一芯片主体的下表面上,所述多个连接构件可电连接到所述多个第一真实凸点焊盘和所述多个第一真实硅穿通孔。
在一些示例实施例中,第二芯片还可包括第二芯片主体和第二芯片主体的下表面上的多个第二真实凸点焊盘,所述多个第二真实凸点焊盘可电连接到所述多个真实凸点。
在一些示例实施例中,第二芯片还可包括第二芯片主体的下表面上的多个第二虚设凸点焊盘,所述多个第二虚设凸点焊盘可连接到所述多个桥接虚设凸点。
在一些示例实施例中,第二芯片主体还可包括多个第二真实硅穿通孔,所述多个第二真实硅穿通孔电连接到所述多个第二真实凸点焊盘。
在一些示例实施例中,第二芯片主体还可包括多个虚设硅穿通孔,所述多个虚设硅穿通孔可连接到所述多个第二虚设凸点焊盘。
在一些示例实施例中,所述多个第一虚设凸点焊盘之间的节距和所述多个第二虚设凸点焊盘之间的节距可分别小于所述多个第一真实凸点焊盘之间的节距和所述多个第二真实凸点焊盘之间的节距。
在一些示例实施例中,所述多个桥接虚设凸点可彼此分开并且所述多个桥接虚设凸点可连接到所述多个第一虚设凸点焊盘。
在一些示例实施例中,密封构件可包括底部填料,底部填料可处于在第一芯片和第二芯片之间和在第二芯片的侧面上这两种情况中的至少一种。
在一些示例实施例中,密封构件可包括模制构件,模制构件可处于(1)在第一芯片和第二芯片之间并且在第一芯片和第二芯片的侧面上和(2)在第一芯片和第二芯片的侧面和第二芯片的上表面上这两种情况中的一种。
在一些示例实施例中,密封构件可包括:底部填料,在第一芯片和第二芯片之间并且在第一芯片的侧面上;模制构件,覆盖(1)底部填料和第一芯片和第二芯片的侧面以及(2)第一芯片和第二芯片的侧面和第二芯片的上表面这两种情况中的一种。
根据示例实施例,一种芯片堆叠半导体封装件包括:第一芯片,包括第一真实连接部分和第一虚设连接部分,第一真实连接部分包括多个第一真实凸点焊盘,第一虚设连接部分包括多个第一虚设凸点焊盘并且与第一真实连接部分分开;第二芯片,在第一芯片的上表面上,第二芯片包括第二真实连接部分和第二虚设连接部分,第二真实连接部分包括与所述多个第一真实凸点焊盘电连接的多个第一真实凸点,第二虚设连接部分与第二真实连接部分分开并且包括多个第一桥接虚设凸点,所述多个第一桥接虚设凸点连接到所述多个第一虚设凸点焊盘;密封构件,密封第一芯片和第二芯片。
在一些示例实施例中,第一芯片还可包括第三真实连接部分,第三真实连接部分可与第一真实连接部分分开并且包括多个第三真实凸点焊盘,第二芯片还可包括第四真实连接部分,第四真实连接部分可与第二真实连接部分分开并且包括多个第二真实凸点,所述多个第二真实凸点可电连接到所述多个第三真实凸点焊盘。
在一些示例实施例中,第一芯片还可包括第三虚设连接部分,第三虚设连接部分可与第一虚设连接部分分开并且包括多个第三虚设凸点焊盘,第二芯片还可包括第四虚设连接部分,第四虚设连接部分可与第二虚设连接部分分开并且包括多个第二桥接虚设凸点,所述多个第二桥接虚设凸点可连接到第三虚设凸点焊盘。
在一些示例实施例中,第一芯片还可包括第一芯片主体并且第二芯片还可包括第二芯片主体,第一真实连接部分和第三真实连接部分可以在第一芯片主体的中心,第二真实连接部分和第四真实连接部分可以在第二芯片主体的中心。
在一些示例实施例中,第一虚设连接部分和第三虚设连接部分可以在第一芯片主体的边缘,第二虚设连接部分和第四虚设连接部分可以在第二芯片主体的边缘。
在一些示例实施例中,第一芯片还可包括第一芯片主体并且第二芯片还可包括第二芯片主体,第一真实连接部分和第三真实连接部分可以在第一芯片主体的边缘,第二真实连接部分和第四真实连接部分可以在第二芯片主体的边缘。
在一些示例实施例中,第一虚设连接部分和第三虚设连接部分可以在第一芯片主体的中心,第二虚设连接部分和第四虚设连接部分可以在第二芯片主体的中心。
在一些示例实施例中,第一芯片还可包括第一芯片主体、第一芯片主体中的多个硅穿通孔、在第一芯片主体的下表面上的多个连接构件,所述多个硅穿通孔可连接到所述多个第一真实凸点焊盘,所述多个连接构件可电连接到所述多个第一真实凸点焊盘和所述多个真实硅穿通孔。
在一些示例实施例中,密封构件可包括底部填料和模制构件,底部填料可以在第一芯片和第二芯片之间。
根据示例实施例,一种芯片堆叠半导体封装件可包括:主芯片;第一芯片,在主芯片上,第一芯片包括多个第一真实凸点焊盘、多个第一虚设凸点焊盘、多个第一硅穿通孔和多个第一连接构件,所述多个第一硅穿通孔被构造成将所述多个第一真实凸点焊盘电连接到所述多个第一连接构件,所述多个第一连接构件被构造成将第一芯片电连接到主芯片;第二芯片,在第一芯片的上表面上,第二芯片包括多个第二连接构件,所述多个第二连接构件包括多个真实凸点和多个桥接虚设凸点,所述多个真实凸点电连接到所述多个第一真实凸点焊盘,所述多个桥接虚设凸点连接到所述多个第一虚设凸点焊盘;第一密封构件,密封第一芯片和第二芯片。
在一些示例实施例中,第一芯片和第二芯片可具有相同的大小,主芯片的大小可大于第一芯片和第二芯片。
在一些示例实施例中,第一芯片和第二芯片可以是存储器芯片,主芯片可以是逻辑芯片。
在一些示例实施例中,第一密封构件可包括处于在第一芯片和第二芯片之间和在第一芯片的侧面上这两种情况中的至少一种情况的底部填料和覆盖底部填料的模制构件。
在一些示例实施例中,芯片堆叠半导体封装件还可包括主芯片和第一芯片之间的底部填料。
在一些示例实施例中,可将第一密封构件的下表面附着到主芯片的靠外区域。
在一些示例实施例中,多个第三连接构件可以在主芯片的下表面上,芯片堆叠半导体封装件还可包括板基板,第一芯片、第二芯片和主芯片可以在板基板上并且经由所述多个第三连接构件电连接到板基板。
在一些示例实施例中,主芯片可包括多个第二硅穿通孔,所述多个第一连接构件可电连接到所述多个第二硅穿通孔。
在一些示例实施例中,芯片堆叠半导体封装件还可包括在主芯片上并且覆盖第一密封构件的第二密封构件。
在一些示例实施例中,芯片堆叠半导体封装件还可包括板基板和主芯片之间的底部填料。
根据示例实施例,一种芯片堆叠半导体封装件包括:第一芯片,包括多个第一真实连接焊盘和多个第一虚设连接焊盘,所述多个第一真实连接焊盘在第一芯片的中心,所述多个第一虚设连接焊盘在第一芯片的边缘;第二芯片,在第一芯片上,第二芯片包括多个第二真实连接焊盘和多个第二虚设连接焊盘,所述多个第二真实连接焊盘在第二芯片的中心,所述多个第二虚设连接焊盘在第二芯片的边缘;多个真实连接构件,连接所述多个第一真实连接焊盘和所述多个第二真实连接焊盘;多个虚设连接构件,连接所述多个第一虚设连接焊盘和所述多个第二虚设连接焊盘;密封构件,覆盖第一芯片和第二芯片的侧面。
在一些示例实施例中,所述多个虚设连接构件可比所述多个真实连接构件宽,使得虚设连接构件中的每个提供所述多个第一虚设连接焊盘中的两个或更多个和所述多个第二虚设连接焊盘中对应的两个或更多个之间的物理连接。
在一些示例实施例中,第一芯片还可包括与第一真实连接焊盘连接的多个真实硅穿通孔。
在一些示例实施例中,所述多个第一虚设连接焊盘之间的节距和所述多个第二虚设连接焊盘之间的节距可分别小于所述多个第一真实连接焊盘之间的节距和所述多个第二真实连接焊盘之间的节距。
在一些示例实施例中,密封构件可在第一芯片和第二芯片之间。
在一些示例实施例中,密封构件可包括底部填料和模制构件,底部填料可在第一芯片和第二芯片之间,模制构件可覆盖底部填料。
在一些示例实施例中,密封构件可包括底部填料和模制构件,底部填料可部分地在第一芯片的侧面和第二芯片的侧面中的至少一个上,模制构件可覆盖底部填料。
附图说明
根据下面结合附图进行的详细描述,将更清楚地理解发明构思的示例性实施例,在附图中:
图1至图13是根据各种示例实施例的芯片堆叠半导体封装件的剖视图;
图14和图15是根据一些示例实施例的芯片堆叠半导体封装件的真实连接部分的剖视图;
图16至图19是根据一些示例实施例的芯片堆叠半导体封装件中使用的单元芯片的平面图;
图20是根据示例实施例的芯片堆叠半导体封装件的芯片堆叠结构的透视图;
图21A至图22B是示出图20的凸点焊盘和凸点之间的堆叠和连接关系的剖视图;
图23至图31是根据示例实施例的制造芯片堆叠半导体封装件的方法的剖视图;
图32至图42是根据另一个示例实施例的制造芯片堆叠半导体封装件的方法的剖视图;
图43至图46是根据一些示例实施例的芯片堆叠半导体封装件的剖视图;
图47至图49是根据一些示例实施例的芯片堆叠半导体封装件的剖视图;
图50是根据示例实施例的包括芯片堆叠半导体封装件的存储卡的示意性框图;
图51是根据示例实施例的包括芯片堆叠半导体封装件的电子系统的示意性框图;
图52是根据示例实施例的包括芯片堆叠半导体封装件的电子系统的透视图。
具体实施方式
下文中,将通过参照附图说明发明的一些示例实施例,详细地描述本发明构思。然而,示例实施例可以以多种不同的形式来实施,并且不应该被理解为局限于在此阐述的示例实施例;相反,提供这些示例实施例使得本公开将是彻底和完全的,并且将把示例实施例的构思和范围充分地传达给本领域的技术人员。在附图中,为了清晰起见,夸大了层和区域的厚度。
应该理解,当诸如层、膜、区域或板的组件被称为“在”另一组件“上”或“连接到”另一组件时,该组件可以直接在所述另一组件上或直接连接到所述另一组件,或者可以在所述另一组件上存在中间组件。当组件被称为“直接在”另一组件“上”或“直接连接到”另一组件时,在所述另一组件上可不存在中间组件。附图中同样的附图标记指示同样的元件。如在这里使用的,术语“和/或”包括一个或更多个相关所列项的任意组合和所有组合。
应该理解,尽管这里可使用术语第一、第二、第三等来描述各种元件、组件、区域、层和/或部分,但这些元件、组件、区域、层和/或部分不应该受这些术语限制。这些术语只是用于将一个元件、组件、区域、层或部分与另一个元件、组件、区域、层或部分区分开。例如,在不脱离本发明构思的教导的情况下,下面讨论的第一元件、组件、区域、层或部分可被称为第二元件、组件、区域、层或部分。
为了便于描述,在这里可使用诸如“在……下方”或“下面”等空间相对术语来描述如图中所示的一个元件或特征与其它元件或特征的关系。应该理解,除了附图中描绘的方位之外,空间相对术语意图涵盖装置在使用或操作中的不同方位。例如,如果附图中的装置被翻转,那么被描述为“在”其它元件或特征“下方”的元件将被定位“在”其它元件或特征“上方”。因此,示例术语“在……下方”可涵盖在……上方和在……下方这两种方位。装置可另外定位(旋转90度或在其它方位)并且相应解释这里使用的空间相对描述符。
应该理解,尽管这里可以使用术语来描述各种组件,但这些组件不应该受这些术语限制。这些组件只是用于将一个组件与另一个区分开。如这里使用的,单数形式“一”、“一个”和“该”意图也包括复数形式,除非上下文另外清楚地指示。还应该理解,这里使用的术语“包括”和/或其变型指明存在所述特征或组件,但不排除存在或添加一个或更多个其它特征或组件。
这里,参照作为发明构思的理想化示例实施例(和中间结构)的示意性示图的剖面示图,描述发明构思的一些示例实施例。如此,将预料到,由于(例如)制造技术和/或公差导致的示图的形状变化。因此,本发明构思的示例实施例应该不被理解为限于这里示出的区域的特定形状,而是将包括由(例如)制造导致的形状偏差。
尽管可不示出一些剖视图对应的平面图和/或透视图,但这里示出的装置结构的剖视图为沿着两个不同方向(如平面图中将示出的),和/或在三个不同方向上(如透视图中将示出的)延伸的多个装置结构提供了支承。所述两个不同方向可彼此正交或可不彼此正交。所述三个不同方向可包括可与所述两个不同方向正交的第三方向。多个装置结构可被集成在同一电子装置中。例如,当在剖视图中示出装置结构(例如,存储器单元结构或晶体管结构)时,电子装置可包括多个装置结构(例如,存储器单元结构或晶体管结构),如将在电子装置的平面图上示出的。多个装置结构可布置成阵列和/或二维图案。
下文中,将参照附图进一步详细说明一些示例实施例。
图1是根据示例实施例的芯片堆叠半导体封装件1000的剖视图。
具体地,芯片堆叠半导体封装件1000可包括:第一芯片100;第二芯片200,堆叠在第一芯片100上;密封构件330,密封第一芯片100和第二芯片200。芯片堆叠半导体封装件1000可具有其中第二芯片200的两个端部部分和第一芯片100的边缘可被形成为彼此齐平的结构。
第一芯片100和第二芯片200可包括真实连接部分A和虚设连接部分D。真实连接部分A可以是其中第一芯片100和第二芯片200通过真实硅穿通孔130及第一连接构件140和第二连接构件240而与外部装置(未示出)电连接的部分。下文中,真实连接部分可以是与外部装置电连接的部分的统称。
虚设连接部分D可以是其中第一芯片100和第二芯片200与第一桥接虚设凸点252电连接但可不与外部装置电连接的部分。下文中,虚设连接部分D可以是不与外部装置电连接的部分的统称。第一芯片100的真实连接部分A和虚设连接部分D可分别被指示为A1和D1,第二芯片200的真实连接部分A和虚设连接部分D可分别被指示为A2和D2。
第一芯片100可包括第一芯片主体110、第一下绝缘层120、第一真实硅穿通孔130、第一连接构件140、保护层160、第一真实凸点焊盘170和第一虚设凸点焊盘172。可存在多个第一真实凸点焊盘170。可存在多个第一虚设凸点焊盘172。
第一芯片主体110可包括形成在硅基板(未示出)上的集成电路层和覆盖集成电路层的层间绝缘层(未示出)。第一下绝缘层120可包括金属间绝缘层122和钝化层124。可在金属间绝缘层122内部形成多层布线图案(未示出)。
第一真实凸点焊盘170可形成在第一芯片主体110的上表面上。第一真实硅穿通孔130穿透真实连接部分A1的第一芯片主体110并且可连接到第一下绝缘层120中的多层布线图案。第一连接构件140可包括形成在第一芯片主体110的下表面上并且电连接和/或物理连接到外部装置的外部凸点焊盘142和外部凸点144。外部凸点焊盘142和外部凸点144可被称为凸点焊盘和凸点。
外部凸点焊盘142可由钝化层124的上表面上的导电材料形成,并且可电连接到第一下绝缘层120中的多层布线图案。因此,外部凸点焊盘142可经由多层布线图案电连接到第一真实硅穿通孔130。换句话讲,第一真实硅穿通孔130可电连接到第一连接构件140。
凸点下金属(UBM)(未示出)可形成在外部凸点焊盘142的上表面上。外部凸点焊盘142可由例如铝(Al)或铜(Cu)形成,并且可通过例如脉冲镀或直流(DC)电镀法形成。然而,形成外部凸点焊盘142的材料或方法不限于此。
外部凸点144可形成在外部凸点焊盘142的上表面上。外部凸点144可由导电材料(例如,Al、Cu、金(Au)、焊料等)形成,但其材料不限于此。由焊料形成的外部凸点144可被称为焊料凸点。
保护层160可由绝缘材料形成并且设置在第一芯片主体110的上表面的在真实连接部分A1处的那部分上,并且可以保护第一芯片主体110不受外部影响。保护层160可以是(例如)氧化物层或氮化物层,或者可以是包括例如氧化物层和氮化物层的双层。另外,保护层160可以是氧化物层,例如,通过高密度等离子体化学气相沉积(HDP-CVD)形成的氧化硅层(SiO2)。另外,保护层160可形成在第一芯片主体110的上表面的在第二芯片200的虚设连接部分D1处的那部分上。
第一真实凸点焊盘170可电连接到第一真实硅穿通孔130。如同外部凸点焊盘142,第一真实凸点焊盘170可由例如Al、Cu等形成。第一虚设凸点焊盘172可形成在第一芯片主体110的上表面上。第一虚设凸点焊盘172可不电连接到构成第一连接构件140的外部凸点焊盘142。如同外部凸点焊盘142,第一虚设凸点焊盘172可由例如Al、Cu等形成。
第二芯片200可包括第二芯片主体210、第二下绝缘层220、第二连接构件240、第二虚设凸点焊盘250和第一桥接虚设凸点252。如同第一芯片主体110,第二芯片主体210可包括形成在硅基板上的集成电路层和覆盖集成电路层的层间绝缘层(未示出)。第二芯片主体210的上表面可被暴露于外部。第二芯片主体210的上表面可以是上面形成有集成电路层的硅基板的后表面。
第二下绝缘层220可形成在第二芯片主体210的下表面上并且可包括金属间绝缘层222和钝化层224。可在金属间绝缘层222内部形成多层布线图案(未示出)。第二连接构件240可包括形成在第二芯片主体210的下表面上的第二真实凸点焊盘242和第一真实凸点244。可存在多个第二真实凸点焊盘242和多个第一真实凸点244。
第二真实凸点焊盘242可由钝化层224的上表面上的导电材料形成并且可电连接到第二下绝缘层220中的多层布线图案。第二虚设凸点焊盘250可由导电材料形成并且设置在钝化层224的上表面上并且可电连接到或可不电连接到第二下绝缘层220中的多层布线图案。
UBM(未示出)可形成在第二真实凸点焊盘242和/或第二虚设凸点焊盘250的上表面上。第二真实凸点焊盘242和第二虚设凸点焊盘250可由与第一连接构件140的外部凸点焊盘142相同的材料或不同的材料形成,形成第二真实凸点焊盘242和第二虚设凸点焊盘250的方法可以与形成外部凸点焊盘142的方法相同或不同。
第一真实凸点244可形成在第二真实凸点焊盘242的上表面上。第一真实凸点244可由导电材料(例如,Cu、Al、Au、焊料等)形成,如同第一连接构件140的外部凸点144。然而,第一真实凸点244的材料不限于此。不同于第一芯片100,第二芯片200可以不具有穿透第二芯片主体210的硅穿通孔。第一桥接虚设凸点252可形成在第二芯片主体210的下表面上。第一桥接虚设凸点252可形成在第二虚设凸点焊盘250的上表面上。
第二芯片200可堆叠在第一芯片100的上表面上。第二芯片200可以以倒装芯片方式堆叠在第一芯片100的上表面上。在堆叠有第一芯片100和第二芯片200的堆叠结构中,第二芯片200的第二连接构件240(例如,第一真实凸点244)可电连接到第一芯片100的第一真实凸点焊盘170。因此,第二芯片200的多层布线图案可通过第二连接构件240和第一真实凸点焊盘170电连接到第一真实硅穿通孔130。
在堆叠有第一芯片100和第二芯片200的堆叠结构中,第一桥接虚设凸点252可物理连接到第一虚设凸点焊盘172。在图1中,第一桥接虚设凸点252可物理连接到两个第一虚设凸点焊盘172。因此,在执行以将第一芯片100的第一真实凸点焊盘170电连接到第二芯片200的第一真实凸点244的热压接合工艺和回流工艺期间,可通过使用第一桥接虚设凸点252控制第一芯片100和第二芯片200的弯曲。因此,可容易地堆叠第一芯片和第二芯片200。
当第二芯片200的第二连接构件240被布置成对应于第一芯片100的第一真实凸点焊盘170的布置时,第二芯片200可堆叠在第一芯片100的上表面上。第一芯片100和第二芯片200的类型可彼此相同或不同。
密封构件330可包括底部填料320和模制构件300。底部填料320可填充第一芯片100和第二芯片200之间的间隙。该间隙是指第一芯片100和第二芯片200之间的区域或空间,第一芯片100和第二芯片200连接于该区域或空间。例如,可在其中第一芯片100的第一真实凸点焊盘170和第一虚设凸点焊盘172分别连接到第二连接构件240和第一桥接虚设凸点252的区域或空间中设置间隙。底部填料320可由底部填料树脂(例如,环氧树脂)形成,并且可包括例如二氧化硅填料或熔剂(flux)。
模制构件300可形成在底部填料320的外部区域上。底部填料320可由与模制构件300相同的材料或不同的材料形成。模制构件300可由聚合物(例如,树脂)形成。例如,模制构件300可由环氧模塑料(EMC)形成。因此,模制构件300可密封底部填料320的侧面、第二芯片200和第一芯片100。
模制构件300的上表面可与第二芯片200的上表面在同一水平面。因此,第二芯片200的上表面可被暴露于外部。当第二芯片主体210中包括的集成电路层形成在硅基板的第一表面上并且第二芯片200以倒装芯片方式堆叠在第一芯片100上时,第二芯片200的上表面可以是与硅基板的第一表面相对的硅基板的第二表面。
在本示例实施例中,因为第一芯片100的第一连接构件140从中间绝缘层(金属间绝缘层)122突出并且通过钝化层124的下表面,所以第一连接构件140可连接到第一下绝缘层120中(例如,金属间绝缘层122中)的多层布线图案(未示出)并且从与钝化层124处于同一水平面的平面突出。例如,保护层160可只形成在第一芯片100的上表面上,并且被底部填料320和模制构件300密封。根据这个构造,保护层160可不被暴露于外部。
第一芯片100和第二芯片200中的每个的侧面可被密封构件300密封,从而没有被暴露于外部。例如,第一芯片100和第二芯片200中的每个的侧面内的硅可不被暴露于外部。当第一芯片100和第二芯片200中的每个的侧面内的硅没有被暴露于外部时,可防止或减轻施加到第一芯片100和第二芯片200的物理冲击。
图2是根据示例实施例的芯片堆叠半导体封装件1000a的剖视图。
例如,除了第一桥接虚设凸点252a和第一虚设硅穿通孔190以外,图2的芯片堆叠半导体封装件1000a可具有与图1的芯片堆叠半导体封装件1000类似的结构。因此,为了方便起见,将省略或简要提供已经参照图1提供的描述。
在芯片堆叠半导体封装件1000a中,第一虚设硅穿通孔190可形成在第一芯片100的虚设连接部分D1中。第一虚设硅穿通孔190可连接到第一虚设凸点焊盘172的下表面。第一虚设硅穿通孔190可有助于减轻或防止第一芯片100的卷曲。
第一虚设硅穿通孔190可穿透虚设连接部分D1的第一芯片主体110,而没有连接到第一下绝缘表面120中的多层布线图案(未示出)。因此,第一虚设硅穿通孔190可不电连接到第一连接构件140。
第一桥接虚设凸点252a可物理连接到四个第一虚设凸点焊盘172。因此,在被执行以将第一芯片100的第一真实凸点焊盘170电连接到第二芯片200的第一真实凸点244的回流过程期间,可通过第一桥接虚设凸点252a控制、防止或减轻第一芯片100和第二芯片200的卷曲。因此,第一芯片100和第二芯片200可容易堆叠。
图3是根据示例实施例的芯片堆叠半导体封装件1000b的剖视图。
例如,除了密封构件330a之外,芯片堆叠半导体封装件1000b可具有与图1和图2的芯片堆叠半导体封装件1000和1000a类似的结构。因此,为了方便起见,将省略或简要提供已经参照图1和图2提供的描述。
在本示例实施例的芯片堆叠半导体封装件1000b中,形成密封构件330a的模制构件300a可不仅覆盖第二芯片200的侧面,而且还可覆盖第二芯片200的上表面。也就是说,密封构件330a可覆盖第一芯片100的侧面和第二芯片200的侧面和上表面,而不覆盖第一芯片100和第二芯片200的下表面。当密封构件330a覆盖第一芯片100的侧面和第二芯片200的侧面和上表面时,相比于密封构件330a只覆盖第一芯片100和第二芯片200的侧面的情况,第一芯片100和第二芯片200可受到更好的保护。
可通过跳过针对密封构件330a的研磨过程或针对密封构件330a局部执行研磨过程以在第二芯片200的上表面上留下密封构件330a来实现上述结构。
图4是根据示例实施例的芯片堆叠半导体封装件1000c的剖视图。
例如,除了密封构件330b以外,芯片堆叠半导体封装件1000c可具有与图1和图2的芯片堆叠半导体封装件1000和1000a类似的结构。因此,为了方便起见,将省略或简要提供已经参照图1和图2提供的描述。
在芯片堆叠半导体封装件1000c中,构成密封构件330b的底部填料320a可覆盖第一芯片100和第二芯片200之间的间隙。该间隙是指第一芯片100和第二芯片200之间的区域或空间,第一芯片100和第二芯片200彼此连接于该区域或空间。另外,底部填料320a可覆盖第一芯片100的侧面。例如,底部填料320a的下表面可与形成在第一芯片100外部的模制构件300b的下表面处于同一水平面。
底部填料320a可具有其下部部分比其上部部分宽的形状,但底部填料320a的形状可变化。例如,底部填料320a具有其中上部部分和下部部分的大小相同的形状。
由于底部填料320a,导致模制构件300b可密封第二芯片200的侧面和底部填料320a的侧面。底部填料320a的下表面可与模制构件300b的下表面处于同一水平面。另外,底部填料320a和模制构件300b的下表面可与第一芯片100的钝化层124的下表面处于同一水平面。
图5是根据示例实施例的芯片堆叠半导体封装件1000d的剖视图。
例如,除了密封构件330c以外,芯片堆叠半导体封装件1000d可具有与图1和图2的芯片堆叠半导体封装件1000和1000a类似的结构。因此,为了方便起见,将省略或简要提供已经参照图1和图2提供的描述。
在芯片堆叠半导体封装件1000d中,构成密封构件330c的底部填料320b可覆盖第一芯片100和第二芯片200之间的间隙,并且可覆盖第一芯片100的侧面。该间隙是指第一芯片100和第二芯片200之间的区域或空间,第一芯片100和第二芯片200连接于该区域或空间。因此,底部填料320a可容易地密封第一芯片100的侧面。
此外,底部填料320b的侧面可被暴露于外部,并且底部填料320被暴露的侧面可与模制构件300c被暴露的侧面处于同一水平面。底部填料320b的下表面可被暴露于芯片堆叠半导体封装件1000d的外部。底部填料320b的下表面可与第一芯片100的钝化层124的下表面处于同一水平面。
图5的底部填料320b的下表面的宽度可大于图4的底部填料320a的下表面的宽度。因为底部填料320b被形成为暴露于外部,所以模制构件300c可覆盖第二芯片200的侧面,而没有完全覆盖第一芯片100的侧面。
图6是根据示例实施例的芯片堆叠半导体封装件1000e的剖视图。
例如,除了密封构件330d以外,芯片堆叠半导体封装件1000e可具有与图1和图2的芯片堆叠半导体封装件1000和1000a类似的结构。因此,为了方便起见,将省略或简要提供已经参照图1和图2提供的描述。
在芯片堆叠半导体封装件1000e中,构成密封构件330d的模制构件300d可覆盖第一芯片100和第二芯片200之间的间隙以及第一芯片100和第二芯片200中的每个的侧面。该间隙是指第一芯片100和第二芯片200之间的区域或空间,第一芯片100和第二芯片200彼此连接于该区域或空间。因此,模制构件300d可容易地密封第一芯片100和第二芯片200的侧面。
根据这个示例实施例,芯片堆叠半导体封装件1000e可没有底部填料。因此,可只使用密封构件330d密封第一芯片100和第二芯片200。因此,可用模制构件300d填充间隙(例如,第一芯片100和第二芯片200之间的区域或空间,第一芯片100和第二芯片200连接于该区域或空间)。可通过模制底部填充(MUF)过程,形成在不使用底部填料的情况下用模制构件300d密封第一芯片100和第二芯片200的芯片堆叠半导体封装件。
图7是根据示例实施例的芯片堆叠半导体封装件1000f的剖视图。
例如,除了密封构件330e以外,芯片堆叠半导体封装件1000f可具有与图1和图2的芯片堆叠半导体封装件1000和1000a类似的结构。因此,为了方便起见,将省略或简要提供已经参照图1和图2提供的描述。
在芯片堆叠半导体封装件1000f中,构成密封构件330e的底部填料320可只形成在第一芯片100和第二芯片200之间的间隙处。该间隙是指第一芯片100和第二芯片200之间的区域或空间,第一芯片100和第二芯片200彼此连接于该区域或空间。根据这个示例实施例,芯片堆叠半导体封装件1000f的密封构件330e可不包括模制构件。
密封构件330e可填充第一芯片100和第二芯片200之间的间隙,而不覆盖第一芯片100和第二芯片200的侧面。该间隙是指第一芯片100和第二芯片200之间的区域或空间,第一芯片100和第二芯片200连接于该区域或空间。例如,第一芯片100和第二芯片200之间的间隙可对应于第一芯片100的第一真实凸点焊盘170和第一虚设凸点焊盘172可在此处分别连接到第二连接构件240和第一桥接虚设凸点252a的区域或空间。由于密封构件330e没有形成在第一芯片100和第二芯片200的侧面上,所以第一芯片100和第二芯片200的侧面可被暴露于外部。因此,当芯片堆叠半导体封装件1000f被顺序安装在板基板上并且被进一步模制时,模制构件可被恰当接合和结合到第二芯片200的上表面和/或第一芯片100和第二芯片200的侧面。
图8是根据示例实施例的芯片堆叠半导体封装件1000a的剖视图。
例如,除了密封构件330f以外,芯片堆叠半导体封装件1000g可具有与图1和图2的芯片堆叠半导体封装件1000和1000a类似的结构。因此,为了方便起见,将省略或简要提供已经参照图1和图2提供的描述。
在芯片堆叠半导体封装件1000g中,形成密封构件330f的底部填料320c可填充第一芯片100和第二芯片200之间的间隙(例如,该间隙可以是指第一芯片100和第二芯片200在此处连接的区域或空间),并且延伸以覆盖第二芯片200的侧面。
密封构件330f可填充第一芯片100和第二芯片200之间的间隙。例如,在第一芯片100和第二芯片200之间的间隙中,第一芯片100的第一真实凸点焊盘170和第一虚设凸点焊盘172可分别连接到第二连接构件240和第一桥接虚设凸点252a。密封构件330f可填充间隙,同时覆盖第二芯片200的侧面。
覆盖第二芯片200的侧面的密封构件330f的侧面和第一芯片100的侧面可被形成为彼此齐平。因此,包括密封构件330f的第二芯片200的大小(例如,水平宽度)可与第一芯片100的大小(例如,水平宽度)基本上相同。
另外,因为密封构件300f没有形成在第一芯片100的侧面上,所以第一芯片100的侧面可被暴露于外部。因此,当芯片堆叠半导体封装件1000g被顺序安装在板基板上并且被进一步模制时,模制构件可被恰当接合和结合到第一芯片100的侧面。
图9是根据示例实施例的芯片堆叠半导体封装件1000h的剖视图。
例如,除了第二真实硅穿通孔130-1和第二虚设硅穿通孔190-1以外,芯片堆叠半导体封装件1000h可具有与图1至图3的芯片堆叠半导体封装件1000、1000a和1000b类似的结构。因此,为了方便起见,将省略或简要提供已经参照图1至图3提供的描述。
在芯片堆叠半导体封装件1000h中,可在第二芯片200的真实连接部分A2中形成第二真实硅穿通孔130-1。第二真实硅穿通孔130-1可防止或减轻第二芯片200的卷曲。
可穿过真实连接部分A2的第二芯片主体210形成第二真实硅穿通孔130-1。第二真实硅穿通孔130-1可电连接到第一连接构件140和第二连接构件240。
在芯片堆叠半导体封装件1000h中,可在第二芯片200的虚设连接部分D2中形成第二虚设硅穿通孔190-1。第二虚设硅穿通孔190-1可防止或减轻第二芯片200的卷曲。第二虚设硅穿通孔190-1可形成在第二芯片主体210中。第二虚设硅穿通孔190-1可穿透虚设连接部分D2的第二芯片主体210。第二虚设硅穿通孔190-1可以不电连接到第一连接构件140。
图10是根据示例实施例的芯片堆叠半导体封装件1000i的剖视图。
例如,可通过组合图1、图2、图4和图9的芯片堆叠半导体封装件1000、1000a、1000c和1000h的特征,形成芯片堆叠半导体封装件1000i。因此,为了方便起见,可省略或简要提供已经参照图1、图2、图4和图9提供的描述。
如图9中所示,在芯片堆叠半导体封装件1000i中,可在第二芯片200的真实连接部分A2中形成第二真实硅穿通孔130-1。第二真实硅穿通孔130-1可穿透真实连接部分A2的第二芯片主体210。第二真实硅穿通孔130-1可电连接到第一连接构件140和第二连接构件240。
如图9中所示,在芯片堆叠半导体封装件1000i中,可在第二芯片200的虚设连接部分D2中形成第二虚设硅穿通孔190-1。可以安装第二虚设硅穿通孔190-1以防止或减轻第二芯片200的卷曲。第二虚设硅穿通孔190-1可穿透虚设连接部分D2的第二芯片主体210。第二虚设硅穿通孔190-1可以不电连接到第一连接构件140。
如图10中所示,在芯片堆叠半导体封装件1000i中,形成密封构件330b的底部填料320a可覆盖其中第一芯片100和第二芯片200在此处连接的部分和第一芯片100。另外,底部填料320a可覆盖第一芯片100的侧面。例如,底部填料320a的下表面可以与形成在第一芯片100外部的模制构件300b的下表面处于同一水平面。
图11是根据示例实施例的芯片堆叠半导体封装件1000j的剖视图。
例如,芯片堆叠半导体封装件1000j可具有堆叠有四个芯片的结构,而芯片堆叠半导体封装件1000至1000i示出各由两个芯片堆叠而成的结构。因此,将省略或简要提供已经提供的描述。
芯片堆叠半导体封装件1000j可包括第一芯片100、第二芯片200、第三芯片500、第四芯片600和密封构件330。第三芯片500的真实连接部分A和虚设连接部分D可被分别称为A3和D3,第四芯片600的真实连接部分A和虚设连接部分D可被分别称为A4和D4。
除了芯片连接结构以外,第二芯片200、第三芯片500和第四芯片600可具有与参照图1和图2描述的第二芯片200类似的结构。第二芯片200和第三芯片500可具有真实连接部分A中的真实硅穿通孔130-1和130-2、真实凸点焊盘170-1和170-2和保护层160-1和160-2。在芯片100、200、500和600之间可存在连接构件240、240-1和240-2。真实硅穿通孔130-1和130-2可形成在第二芯片200的芯片主体210和第三芯片500的芯片主体210-1中。真实硅穿通孔可不形成在第四芯片600的芯片主体210-2中,第四芯片600设置在芯片堆叠半导体封装件1000j的最上层表面上。第三芯片500和第四芯片600可在虚设连接部分D中包括虚设凸点焊盘172-1和172-2和虚设桥接凸点252a-1和252a-2。
可用密封构件330密封第一芯片100、第二芯片200、第三芯片500和第四芯片600。密封构件可包括底部填料320和模制构件300a。底部填料320可填充第一芯片100、第二芯片200、第三芯片500和第四芯片600之间的间隙。模制构件300可形成在第一芯片100、第二芯片200、第三芯片500和第四芯片600中的每个的侧面上并且可设置在底部填料320外部。
图12是根据示例实施例的芯片堆叠半导体封装件1000k的剖视图。
例如,除了真实硅穿通孔130-3和虚设硅穿通孔190、190-1、190-2和190-3以外,芯片堆叠半导体封装件1000k可具有与芯片堆叠半导体封装件1000j类似的结构。因此,为了方便起见,将省略或简要提供已经参照图11提供的描述。
在芯片堆叠半导体封装件1000k中,真实硅穿通孔130-3可形成在第四芯片600的真实连接部分A4中的芯片主体210-2中。另外,虚设硅穿通孔190、190-1、190-2和190-3可分别形成在虚设连接部分D中的第一芯片100、第二芯片200、第三芯片500和第四芯片600上。
图13是根据示例实施例的芯片堆叠半导体封装件1000l的剖视图。
例如,除了彼此分开的多个真实连接部分A和彼此分开的多个虚设连接部分D以外,芯片堆叠半导体封装件1000l可具有与图11的芯片堆叠半导体封装件1000j类似的结构。因此,将省略或简要提供已经参照图11提供的描述。
在芯片堆叠半导体封装件1000l中,第二芯片200、第三芯片500、第四芯片600和第五芯片620可堆叠在第一芯片100上。第一芯片100、第二芯片200、第三芯片500、第四芯片600和第五芯片620均可被分成多个真实连接部分A和多个虚设连接部分D。第一芯片100的大小(例如,水平宽度或长度)S1可大于第二芯片200的大小(例如,水平宽度或长度)S2。
多个真实连接部分A可形成在芯片主体110、210、210-1、210-2和210-3的中心部分上。第一芯片100、第二芯片200、第三芯片500、第四芯片600和第五芯片620的多个真实连接部分A可被划分为第一真实连接组A1至A5和与第一真实连接组A1至A5分开的第二真实连接组A6至A10。
例如,当第一芯片100和第二芯片200堆叠并且多个真实连接部分A被划分为两组时,第一芯片100的第一真实连接部分可以是A1,第二芯片200的第二真实连接部分可以是A2。第一芯片100的第三真实连接部分可以是A6,第二芯片200的第四真实连接部分可以是A7。第三真实连接部分A6和第四真实连接部分A7可分别与第一真实连接部分A1和第二真实连接部分A2分开。
多个虚设连接部分D可与真实连接部分A分开并且可形成在芯片主体110、210、210-1、210-2和210-3的边缘上。第一芯片100、第二芯片200、第三芯片500、第四芯片600和第五芯片620的多个虚设连接部分D可被划分为第一虚设连接组D1至D5和与第一虚设连接组D1至D5分开的第二虚设连接组D6至D10。
例如,当第一芯片100和第二芯片200堆叠并且虚设连接部分D被划分为两组时,第一芯片100的第一虚设连接部分可以是D1,第二芯片200的第二虚设连接部分可以是D2。第一芯片100的第三虚设连接部分可以是D6,第二芯片200的第四虚设连接部分可以是D7。第三虚设连接部分D6和第四虚设连接部分D7可分别与第一虚设连接部分D1和第二虚设连接部分D2分开。
图14和图15是根据一些示例实施例的芯片堆叠半导体封装件的真实连接部分A的剖视图。
例如,将描述上述芯片堆叠半导体封装件的第一芯片100的真实连接部分A的结构。第一芯片100的真实连接部分A的结构可以以相同或类似的方式应用于第二芯片200、第三芯片500、第四芯片600和第五芯片620的真实连接部分。为了方便起见,将描述第一芯片100的真实连接部分A。
图14的真实硅穿通孔130可具有中间通孔结构。因此,图14的真实硅穿通孔130可穿透半导体基板102和层间绝缘层104,并且可连接到多层布线图案180。
图15的真实硅穿通孔130a可具有后通孔结构。因此,真实硅穿通孔130a穿透半导体基板102、层间绝缘层104、金属间绝缘层122和钝化层124,并且可直接连接到第一连接构件140a的凸点焊盘142a和凸点144。在图15中,附图标记135a可以是形成在沟槽中的分隔件绝缘层。
将参照图14详细描述真实硅穿通孔130。在真实连接部分A中,集成电路层150可形成在半导体基板102上(例如,在硅基板的第一表面F1上),层间绝缘层104可形成在半导体基板102的第一表面F1上以覆盖集成电路层150。半导体基板102和层间绝缘层104可形成第一芯片100的芯片主体100。集成电路层150可包括各种电路装置(例如,晶体管和/或电容器)。
沟槽形成在层间绝缘层104和半导体基板102上,分隔件绝缘层135和真实硅穿通孔130形成在沟槽中。可通过蚀刻工艺或激光钻孔工艺形成沟槽。在考虑到后续对半导体基板102的第二表面F2进行抛光的情况下,沟槽可被形成为没有完全穿透半导体基板102。分隔件绝缘层135可形成在沟槽中。分隔件绝缘层135可包括适当的绝缘层,例如,氧化物层和氮化物层,或者可包括聚合物或聚对二甲苯。可通过例如低温沉积、低温化学气相沉积(LTCVD)、聚合物喷射或物理气相沉积(PVD)形成分隔件绝缘层135。
真实硅穿通孔130可形成在分隔件绝缘层135中。可通过在设置在沟槽中的分隔件绝缘层135上形成屏障金属层134并且在屏障金属层134上形成布线金属层132来形成真实硅穿通孔130。屏障金属层134可包括从由钛(Ti)、钽(Ta)、氮化钛(TiN)和氮化钽(TaN)组成的组中选择的至少一种,或者可具有堆叠有Ti、Ta、TiN和TaN中的两种或更多种的结构。在形成真实硅穿通孔130之前或之后,可形成金属接触件152。
在层间绝缘层104上,可形成与真实硅穿通孔130和金属接触件152、金属间绝缘层122和钝化层124连接的多层布线图案180。例如,多层布线图案180可具有堆叠有布线181、185和189和垂直塞183和187的结构。金属间绝缘层122可根据多层布线图案180的结构而具有多层结构。
可通过沉积材料层或将材料层图案化或者通过镶嵌工艺(damascene process)来形成多层布线图案180。例如,当多层布线图案180包括铝(Al)和/或钨(W)时,可通过沉积材料层或将材料层图案化来形成多层布线图案180。当多层布线图案180包括铜(Cu)时,可通过镶嵌工艺形成多层布线图案180。
参照图15,多层布线图案180(例如,与第三布线189连接的第一连接构件140a)可形成在钝化层124中。另外,可在钝化层124上形成沟槽之后可形成第一连接构件140a,凸点焊盘142a(外部凸点焊盘)可被形成为填充沟槽,凸点144(外部凸点)可形成在凸点焊盘142上。
可通过从半导体基板102的第二表面F2去除半导体基板102的期望的厚度来暴露分隔件绝缘层135和真实硅穿通孔130(或130a)。因此,分隔件绝缘层135(或135a)和真实硅穿通孔130可从第二表面F2突出并且可被暴露于外部。可使用各向同性蚀刻或湿蚀刻来蚀刻半导体基板102,使得半导体基板102的第二表面F2相对于分隔件绝缘层135的底表面和真实硅穿通孔130凹陷。保护层160可形成在半导体基板102的第二表面F2上,与真实硅穿通孔130连接的真实凸点焊盘170可形成在保护层160上。
图16至图17是根据一些示例实施例的芯片堆叠半导体封装件中使用的单元芯片700的平面图。
例如,图16的单元芯片700可应用于上述半导体封装件1000至1000l。真实连接部分702和704可布置在单元芯片700的芯片主体701的中心上。可存在多个真实连接部分,这些真实连接部分包括第一真实连接部分702和与第一真实连接部分702分开的第二真实连接部分704。真实凸点焊盘706(或真实凸点)可布置在第一真实连接部分702和第二真实连接部分704中。例如,多个真实凸点焊盘706可设置在真实连接部分702和704中的任一个中。
虚设连接部分710a和710b可布置成包围真实连接部分702和704。存在多个虚设连接部分,这些虚设连接部分可彼此分开。这些虚设连接部分可包括多个第一虚设连接部分710a和多个第二虚设连接部分710b。第一虚设连接部分710a和第二虚设连接部分710b可按各种方式布置。第一虚设连接部分710a中的一些和/或第二虚设连接部分710b中的一些可布置在芯片主体701的一个或多个边缘上。虚设凸点焊盘712(或虚设凸点)可布置在第一虚设连接部分710a和第二虚设连接部分710b中。例如,多个虚设凸点焊盘712可设置在虚设连接部分710a和710b中的任一个中。
第一真实连接部分702和第二真实连接部分704中的真实凸点焊盘706(或真实凸点)的数量可大于虚设连接部分710a和710b中的虚设凸点焊盘706(或虚设凸点)的数量。例如,在真实连接部分702和704中可存在数千个真实凸点焊盘706(或真实凸点),在虚设连接部分710a、710b、710c和710d中可存在数十或数百个虚设凸点焊盘712(或虚设凸点)。
如图17中所示,虚设凸点焊盘712之间的节距可小于真实凸点焊盘706之间的节距P1。例如,虚设凸点焊盘712的节距P2可小于真实凸点焊盘706的节距P1的一半,使得形成在虚设凸点焊盘712上的虚设凸点可自然地彼此桥接。
图18至图19是根据一些示例实施例的芯片堆叠半导体封装件中使用的单元芯片700a和700b的平面图。
当将图18的单元芯片700a与图16的单元芯片700进行比较时,图18的单元芯片700a和图16的单元芯片700可以是相同的,除了虚设连接部分710a、710c和710e的布置之外。当将图19的单元芯片700b与图16的单元芯片700进行比较时,图19的单元芯片700b和图16的单元芯片700可以是相同的,除了真实连接部分702a和704a与虚设连接部分710f和710g的布置之外。因此,为了方便起见,将省略或简要提供已经参照图16和图17提供的描述。
在图18的单元芯片700a中,芯片主体701的虚设连接部分710c和710e可大于虚设连接部分710a。当将图18的单元芯片700a与图16的单元芯片700进行比较时,形成在芯片主体701的边缘上的图18的虚设连接部分710e的数量可小于图16的虚设连接部分710b的数量。
当将图19的单元芯片700b与图16的单元芯片700进行比较时,图19的真实连接部分702a和704a可布置在芯片主体701的边缘上。在单元芯片700b中,虚设连接部分(例如,虚设连接部分710f)中的一些可布置在芯片主体701的中心上。芯片主体701的虚设连接部分710f和710g的大小可大于图16的单元芯片700的虚设连接部分710a的大小。如上所述,芯片堆叠半导体封装件中的单元芯片上的真实连接部分和虚设连接部分可具有各种布置。
图20是根据示例实施例的芯片堆叠结构的堆叠芯片750的透视图,图21A至图22B是示出图20的凸点焊盘和凸点之间的堆叠和连接关系的剖视图。
例如,如图20中所示,堆叠芯片750可包括堆叠在下芯片700L上的上芯片700U。例如,可使用图16的单元芯片700作为下芯片700L和上芯片700U。在图20的下芯片700L和上芯片700U中,为了方便起见,没有示出真实凸点和虚设凸点。为了方便说明下芯片700L和上芯片700U,将省去或简要提供已经参照图16和图17提供的描述。可堆叠下芯片700L和上芯片700U,使得下芯片700L的真实连接部分702和704和上芯片700U的真实连接部分702和704可彼此对应。
图21A是其中下芯片700L和上芯片700U堆叠但仍然借助真实连接部分702和704以及A彼此连接的剖视图。图21B是其中下芯片700L和上芯片700U堆叠并且彼此连接的剖视图。如图21A至图22B中所示,上芯片700U的真实凸点焊盘706(图1的242)和真实凸点716(图1的244)可电连接到下芯片700L的真实凸点焊盘706(图1的170)。如图21B中所示,真实凸点716(图1的244)可彼此分开并且彼此连接。
可堆叠下芯片700L和上芯片700U,使得下芯片700L的虚设连接部分710a和710b和上芯片700U的虚设连接部分710a和710b可彼此对应。图22A是其中虚设连接部分710a和710b中的下芯片700L和上芯片700U没有彼此物理连接的剖视图。图22B是其中虚设连接部分710a和710b中的下芯片700L和上芯片700U彼此物理连接的剖视图。如图22B中所示,上芯片700U的虚设凸点焊盘712(图1的250)和虚设凸点720可堆叠在下芯片700L的虚设凸点焊盘712(图1的172)的上表面上,以形成通过将虚设凸点720中的一些合并在一起而形成的桥接虚设凸点722(图1的252)。
桥接虚设凸点722(图1的252)可连接到虚设凸点焊盘712(图1的172)。可通过将虚设凸点焊盘712(图1的250)之间的节距P2设计成小于真实凸点焊盘706(图1的242)之间的节距P1来形成桥接虚设凸点722(图1的252)。例如,虚设凸点焊盘712之间的节距P2可以是真实凸点焊盘712(图1的250)之间的节距P1的一半。
以下描述其中上芯片700U的真实凸点焊盘706(图1的242)和真实凸点716(图1的244)电连接到下芯片700L的真实凸点焊盘706(图1的170)并且其中虚设凸点焊盘712(图1的172)连接到桥接虚设凸点722(图1的252)的过程。
例如,可通过热压接合工艺将上芯片700U的真实凸点716(图1的244)接合到下芯片700L的真实凸点焊盘706(图1的170)。然后,可将上芯片700U的虚设凸点720接合到下芯片700L的虚设凸点焊盘712(图1的172)。根据一些示例实施例,虚设凸点720可与虚设凸点焊盘712组合,而虚设凸点中的一些被合并在一起,从而形成桥接虚设凸点722。
另外,通过执行回流工艺,可将上芯片700U的真实凸点716(图1的244)电连接到下芯片700L的真实凸点焊盘706(图1的170),使下芯片700L的虚设凸点焊盘712(图1的172)和上芯片700U的桥接虚设凸点722(图1的252)物理地形成一体并且相连。
可在大约200℃至大约300℃的温度范围内执行回流工艺。在堆叠了下芯片700L和上芯片700U之后,可通过执行热压接合工艺和回流工艺,形成桥接虚设凸点722。
图23至图31是根据示例实施例的制造芯片堆叠半导体封装件的方法的剖视图。
在图23至图31中,芯片的组件的附图标记可与图1至图13的芯片的组件的附图标记类似或相同,因此为了方便起见,将省略或简要提供已经提供的描述。制造图23至图31的芯片堆叠半导体封装件的方法涉及制造其中芯片堆叠在另一个芯片上的叠层芯片(COC)封装件的方法。
参照图23,可制备包括多个芯片100的基体晶圆10,这多个芯片100包括真实连接部分A和虚设连接部分D。可借助接合构件820将基体晶圆10接合到支承载体800。
支承载体800可由例如硅基板、锗基板、硅-锗基板、镓-砷(GaAs)基板、玻璃基板、塑料基板或陶瓷基板形成。接合构件820可由例如非导电膜(NCF)、各向异性导电膜(ACF)、速干胶、热固性粘合剂、激光硬化粘合剂、超声硬化粘合剂或非导电膏(NCP)形成。可通过支承载体800接合基体晶圆10,以面对第一连接构件140。
形成在基体晶圆10上的多个芯片100中的一个可包括真实连接部分A和虚设连接部分D。在真实连接部分A中,可形成第一真实硅穿通孔130和第一真实凸点焊盘170。在虚设连接部分D中,可形成第一虚设凸点焊盘172。
参照图24,可锯切基体晶圆10,并且可将其分成多个芯片。各芯片可对应于图1的芯片堆叠半导体封装件的第一芯片100。下文中,为了方便起见,可将与基体晶圆10分开的芯片称为“第一芯片”。在从基体晶圆10中分离第一芯片100使其成为个体第一芯片之后,可去除支承载体800和接合构件820。
可使用接合构件920将分离后的第一芯片100中的每个接合到支承载体900。可将第一芯片100接合到支承载体900,使得第一芯片100的第一连接构件140面对支承载体900。支承载体900可由例如硅基板、锗基板、硅-锗基板、GaAs基板、玻璃基板、塑料基板或陶瓷基板形成。在本示例实施例中,支承载体900可由例如硅基板或玻璃基板形成。接合构件920可由与接合构件820相同的材料形成。
可通过将第二芯片200堆叠在第一芯片100的上表面上,形成芯片堆叠结构1100。可通过分离基体晶圆中的任一个来获取第二芯片200,在第二芯片200中可不形成真实硅穿通孔。根据一些示例实施例,可在第二芯片200中形成真实硅穿通孔。例如,可从同一基体晶圆中分离出第一芯片100和第二芯片200。
在芯片堆叠结构1100中,构成第二芯片200的真实连接部分A的连接构件240的第一真实凸点244可连接到第一芯片100的真实凸点焊盘170。可通过执行热压接合工艺和/或回流工艺,将虚设连接部分D的第一桥接虚设凸点252连接到第一芯片100的虚设凸点焊盘172。
也就是说,通过执行热压接合工艺,可将第一真实凸点244堆叠在第一芯片100的真实凸点焊盘170上并且使它们相连。此外,可将第二芯片200的第一桥接虚设凸点252堆叠在第一芯片100的虚设凸点焊盘172上并且使它们相连。当形成第一桥接虚设凸点252时,可减轻或防止在将芯片堆叠结构移至后续回流工艺的同时第一芯片和/或第二芯片200的滑动。
然后,通过执行回流工艺,可将第一芯片100的真实凸点焊盘170电连接到第二芯片200的第一真实凸点244,可使第一芯片100的虚设凸点焊盘172和第二芯片200的第一桥接虚设凸点252物理地形成一体和/或相连。可在大约200℃至大约300℃的温度范围内执行回流工艺。
通过执行热压接合工艺和回流工艺,可将第二芯片200堆叠在第一芯片100上并且由于第一桥接虚设凸点252,可减轻或防止第一芯片100和第二芯片200之间发生滑动和/或芯片卷曲。另外,可将第一芯片100的真实凸点焊盘170和第二芯片200的真实凸点244彼此更有效地连接。
参照图25,可形成底部填料320,底部填料320填充芯片堆叠结构1100的第一芯片100和第二芯片200之间的间隙。该间隙是指第一芯片100和第二芯片200之间的区域或空间,第一芯片100和第二芯片200彼此连接于该区域或空间。底部填料320可只填充第一芯片100和第二芯片200之间的间隙。例如,底部填料320可填充第一芯片100和第二芯片200之间的间隙并且可覆盖第一芯片100的侧面。已经描述了底部填料320的各种形状,因此,将省略对其的描述。
在图31中,堆叠在第一芯片100上的芯片的数量是N,例如,三个。如图31中所示,真实凸点焊盘170-1和虚设凸点焊盘172-1可布置在第二芯片200中。第三芯片可堆叠在第二芯片200上并且可形成芯片堆叠结构。最上层芯片(例如,第N个芯片)中可不形成硅穿通孔。
参照图26,可形成模制构件300-1,模制构件300-1密封支承载体900上的芯片堆叠结构1100。模制构件300-1可模制第二芯片200的侧面和上表面以及第一芯片100的侧面。
如图27中所示,可研磨如图27中所示的模制构件300-1的上表面,以暴露第二芯片200的上表面。因此,暴露第二芯片200的上表面的模制构件300和底部填料320可形成密封构件330。当以倒装芯片方式将第二芯片200堆叠在第一芯片100上并且在第二芯片200中不形成硅穿通孔时,第二芯片200的上表面可以是半导体基板的第二表面,在所述第二表面上没有形成集成电路层,从而将半导体基板的第二表面中的硅暴露于外部。
可执行以上研磨工艺来减小最终芯片半导体封装件的厚度。然而,本发明构思的示例实施例不限于此。在一些情况下,可不执行研磨工艺。根据一些示例实施例,当执行研磨工艺时,可执行研磨工艺使得第二芯片200的上表面没有被暴露于外部。
参照图28,可从芯片堆叠结构1100去除支承载体900和接合构件920,以分离芯片堆叠结构1100。因此,芯片堆叠结构1100的第一芯片100的第一连接构件140可被暴露于外部。密封构件330的下表面可与第一芯片100的下表面处于同一水平面。因此,第一芯片100的第一连接构件140可在与第一芯片100的下表面垂直的方向上从芯片堆叠结构1100突出。
如图29中所示,可使用接合构件952将支承载体950接合到芯片堆叠结构1100的第二表面。第一表面是芯片堆叠结构1100的其上暴露第一芯片100的第一连接构件140的表面。第二表面是芯片堆叠结构1100与第一表面相对的表面。支承载体950可由例如硅基板、锗基板、硅-锗基板、GaAs基板、玻璃基板、塑料基板或陶瓷基板形成。接合构件952可由例如NCF、ACF、速干胶、热固性粘合剂、激光硬化粘合剂、超声硬化粘合剂或NCP形成。在本示例实施例中,支承载体950可由例如玻璃基板形成,接合构件952可由例如紫外(UV)膜形成。
通过使用支承载体950,可针对芯片堆叠结构1100中的各芯片进行电裸芯拣选(electrical die sorting,EDS)测试。可使用例如探针卡1500进行EDS测试。探针卡1500可包括主体部分1520和端接顶针1510。端接顶针1510可以是例如弹簧顶针。弹簧顶针可接触真实连接部分A的第一连接构件140,并且电信号可被施加到第一连接构件140。因此,可进行EDS测试。
可基于EDS测试来确定芯片堆叠结构1100是否有缺陷。可弃用有缺陷的芯片堆叠结构或有缺陷的芯片堆叠半导体封装件。因此,根据一些示例实施例的芯片堆叠半导体封装件可以是堆叠有通过了EDS测试的芯片的堆叠封装件。
参照图30,在进行了EDS测试之后,锯切芯片堆叠结构1100的密封构件330,以分离出个体的芯片堆叠半导体封装件1000。可只相对于密封构件330执行锯切。可在锯切密封构件330的同时锯切或去除接合构件952的一部分。当去除支承载体950和接合构件952时,完成芯片堆叠半导体封装件1000。
图32至图42是根据另一个示例实施例的制造芯片堆叠半导体封装件的方法的剖视图。
在图32至图42中,芯片的组件的附图标记可与图1至图13的芯片的组件的附图标记相同或类似。因此为了方便起见,将省略或简要提供已经提供的描述。制造图32至图42的芯片堆叠半导体封装件的方法涉及将芯片堆叠在晶圆上的晶圆上芯片(COW)方法。
参照图32,可制备包括多个芯片100的基体晶圆10a。在多个芯片中,可形成真实连接部分A的真实硅穿通孔130和虚设连接部分D的虚设硅穿通孔190。可同时以晶圆级形成包括真实硅穿通孔130和虚设硅穿通孔190的芯片100。
如图33中所示,可使用接合构件820将基体晶圆10a接合到支承载体800。可将基体晶圆10a接合到支承载体800,使得第一连接构件140面对支承载体800。
参照图34,可制备第二芯片200。可通过切割基体晶圆(例如,图32的基体晶圆10a)来获取第二芯片200。在第二芯片200中可不形成硅穿通孔。然而,本发明构思的示例实施例不限于此。在第二芯片200中可形成硅穿通孔。各第二芯片200可包括芯片主体210、下绝缘层220和第二连接构件240。
第二芯片200可分别堆叠在第一芯片100的上表面上,以形成芯片堆叠结构1100a。因此,形成在基体晶圆10上的芯片100可被称为第一芯片。在芯片堆叠结构1100a中,形成第二芯片200的真实连接部分A的第二连接构件240的第一真实凸点244可连接到第一芯片100的真实凸点焊盘170,可通过执行热压接合工艺和/或回流工艺,将虚设连接部分D的第一桥接虚设凸点252连接到第一芯片100的虚设凸点焊盘172。以上已经参照图24描述了连接方法。因此,将省略对其的描述。
参照图35至图42,可形成底部填料320-2,底部填料320-2填充芯片堆叠结构1100a的第一芯片100和第二芯片200之间的间隙。该间隙可以指芯片堆叠结构1100a的第一芯片100和第二芯片200在此处连接的区域或空间。底部填料320-2可填充第一芯片100和第二芯片200之间的间隙并且还可覆盖第二芯片200的侧面。已经描述了底部填料320-2的各种形状,因此,将省略对其的描述。
在图42中,堆叠在第一芯片100上的芯片的数量可以是N,例如,三个。如图42中所示,真实凸点焊盘170-1和虚设凸点焊盘172-1可布置在第二芯片200上。第三芯片可堆叠在第二芯片200上并且可形成芯片堆叠结构。最上层芯片(例如,第N个芯片)中可不形成硅穿通孔。
参照图36,可形成模制构件300-2,模制构件300-2模制与支承载体800接合的芯片堆叠结构1100a。模制构件300-2可由聚合物(例如,树脂)形成。例如,模制构件300-2可由环氧模塑料(EMC)形成。因此,芯片堆叠结构1100a可包括密封构件330-1,密封构件330-1包括底部填料320-2和模制构件300-2。密封构件330-1可密封各芯片堆叠结构1100a中的第一芯片100的侧面和第二芯片200的侧面和上表面。由于底部填料320-2,模制构件300-2可密封底部填料320-2的侧面。
参照图37,可研磨密封构件330-1的上表面,以暴露各芯片堆叠结构1100a的第二芯片的上表面。密封构件330-1的上表面可与第二芯片200的上表面处于同一水平面。当在第二芯片200中没有形成硅穿通孔并且以倒装芯片方式将第二芯片堆叠在第一芯片100上时,第二芯片200的上表面可以是半导体基板(例如,硅基板)的第二表面,在所述第二表面上没有形成集成电路层。因此,半导体基板的第二表面中的硅可被暴露于外部。
当研磨密封构件330-1的上表面时,也就是说,第二芯片200的上表面可被暴露。当随后将完成的芯片堆叠半导体封装件安装并模制到板基板上时,模制构件可被恰当连接和接合到第二芯片200的上表面。
参照图38,可将支承载体800与基体晶圆10a分开,可从基体晶圆10a去除接合构件820。因此,各芯片堆叠结构1100a的第一芯片100的第一连接构件140可被暴露于外部。
如图39中所示,在翻转了形成有芯片堆叠结构1100a的基体晶圆10a之后,可将支承载体900接合到基体晶圆10a。可使用接合构件920将支承载体900接合到第二芯片200的第二表面,第二芯片200的第二表面面对上面暴露第一芯片100的第一连接构件140的第一表面。支承载体900可由例如硅基板、锗基板、硅-锗基板、GaAs基板、玻璃基板、塑料基板或陶瓷基板形成,接合构件952可由例如NCF、ACF、UV膜、速干胶、热固性粘合剂、激光硬化粘合剂、超声硬化粘合剂或NCP形成。在本示例实施例中,支承载体900可由玻璃基板形成,接合构件920可由UV膜形成。
通过使用支承载体900,可针对各芯片堆叠结构1100a进行EDS测试。可使用例如探针卡1500进行EDS测试。探针卡1500可包括主体部分1520和端接顶针1510。端接顶针1510可以是例如弹簧顶针。弹簧顶针可接触对应的第一连接构件140,电信号可被施加到第一连接构件140。因此,可进行EDS测试。
可基于EDS测试的结果来确定芯片堆叠结构1100a是否有缺陷。在芯片堆叠结构1100a之中,可弃用有缺陷的那个。因此,根据本示例实施例的芯片堆叠半导体封装件可以是堆叠有通过了EDS测试的芯片的堆叠封装件。
参照图40和图41,在进行了EDS测试之后,可锯切基体晶圆10a和密封构件330-1,并且将其分离成芯片堆叠半导体封装件1000。可在锯切基体晶圆10a和密封构件330-1的同时去除接合构件920的一部分。
在图40中,可相对于第二芯片200的侧面(或可供选择地,沿着线S1)锯切基体晶圆10a和密封构件330-1。在图41中,可相对于设置在第二芯片200的侧面上的底部填料320-3的侧面(例如,沿着线S2)锯切基体晶圆10a和密封构件330-1。因此,密封构件330-1可形成或可不形成在芯片堆叠结构1100a中包括的第二芯片200的侧面上。
当去除支承载体900和接合构件920时,可完成各芯片堆叠半导体封装件1000。可顺序或同时地去除支承载体900和接合构件920。
图43至图46是根据一些示例实施例的芯片堆叠半导体封装件6000至6000c的剖视图。
参照图43,芯片堆叠半导体封装件6000可包括主芯片2000和上半导体封装件1000a和1000c。上半导体封装件1000a和1000c可与图1至图4的芯片堆叠半导体封装件1000至1000c相同。因此,将省略或简要提供关于上半导体封装件1000a和1000c中的每个的特征的描述。
主芯片2000的大小可大于上半导体封装件1000a和1000c中包括的第一芯片100和第二芯片200的大小。例如,主芯片2000的水平横截面的大小可与上半导体封装件1000a和1000c的整个水平横截面的大小(例如,包括密封构件330b的水平横截面的大小)相同。
可通过使用接合构件2400将上半导体封装件1000a和1000c安装在主芯片2000上。因此,可使用接合构件2400将上半导体封装件1000a和1000c的模制构件300b和底部填料320a的下表面接合到主芯片2000的靠外区域。
如同存储器芯片,主芯片2000可包括主体2100、下绝缘层2200、钝化层2300、硅穿通孔2500、第三连接构件2600、保护层2750和上焊盘2700。根据主芯片的类型,集成电路层、下绝缘层2200中形成的多层布线图案和钝化层2300可有所不同。主芯片2000可以是逻辑芯片,例如,中央处理单元(CPU)、控制器或专用集成电路(ASIC)。
硅穿通孔2500的数量和对应于硅穿通孔2500的上焊盘2700的数量可对应于堆叠在主芯片2000上的上半导体封装件1000a和1000c的第一连接构件140的数量。例如,硅穿通孔2500的数量可大于第一连接构件140的数量。
形成在主芯片2000的下表面上的第三连接构件2600可包括凸点焊盘2610和凸点2620,第三连接构件2600的数量可小于硅穿通孔2500的数量。因此,在硅穿通孔2500没有对应的第三连接构件2600的情况下,两个或更多个硅穿通孔2500可电组合成一个硅穿通孔2500并且组合后的硅穿通孔2500可连接到单个第三连接构件2600。
由于上面安装有主芯片2000的板基板(未示出)中形成的标准化的布线或者由于板基板(例如,塑料)的物理性质,导致会难以密集布置第三连接构件2600。因此,主芯片2000上形成的第三连接构件2600的大小可大于上半导体封装件1000a和1000c的第一连接构件140的大小。因此,硅穿通孔2500中的一些可不对应于第三连接构件2600。
图44的芯片堆叠半导体封装件6000a可具有与图43的芯片堆叠半导体封装件6000基本上相同或类似的结构,除了上半导体封装件1000a和1000c和密封构件330之外。因此,为了方便起见,将省略或简要提供已经参照图43提供的描述。
参照图44,在芯片堆叠半导体封装件6000a中,上半导体封装件1000和1000a可与图1和图2的芯片堆叠半导体封装件1000和1000a相同。因此,底部填料320可形成在第一芯片100和第二芯片200在此处连接的部分中。模制构件300可形成在第一芯片100和第二芯片200中的每个的侧面上,从而形成密封构件330。
图45的芯片堆叠半导体封装件6000b可具有与图43和图44的芯片堆叠半导体封装件6000和6000a基本上相同或类似的结构,除了上半导体封装件1000a和1000g以及密封构件330之外。因此,为了方便起见,将省略或简要提供已经参照图43和图44提供的描述。
参照图45,在芯片堆叠半导体封装件6000b中,上半导体封装件1000a和1000g可与图2和图8的芯片堆叠半导体封装件1000a和1000g相同。因此,底部填料320c可形成在第一芯片100和第二芯片200在此处连接的部分中和第二芯片200的侧面上,模制构件300可形成在底部填料320c和第一芯片100中的每个的侧面上,从而形成密封构件330。
图46的芯片堆叠半导体封装件6000c可具有与图44的芯片堆叠半导体封装件6000a类似的结构,除了上半导体封装件1000a连接到主芯片2000的部分之外。因此,为了方便起见,将省略或简要提供已经参照图44提供的描述。
参照图46,在芯片堆叠半导体封装件6000c中,底部填料2800可填充上半导体封装件1000a和主芯片2000之间的间隙。该间隙是指上半导体封装件1000a与主芯片2000在此处连接的区域或空间。当使用底部填料2800时,通过执行热压接合方法,例如,通过热压接合方法将第一芯片100的第一连接构件140堆叠在主芯片2000的上焊盘2700上,可将上半导体封装件1000a安装在主芯片2000上。
图47至图49是根据一些示例实施例的芯片堆叠半导体封装件6500a至6500c的剖视图。
例如,参照图47,图47的芯片堆叠半导体封装件6500a可包括板基板3000、主芯片2000、上半导体封装件1000a和1000g、底部填料4000和第二密封构件5000。上半导体封装件1000a和1000g和主芯片2000可分别与参照图45描述的以上的上半导体封装件1000a和1000g和主芯片2000相同。因此,将省略关于上半导体封装件1000a和1000g和主芯片2000的组件的详细描述。可使用第三连接构件2600将上半导体封装件1000a和1000g和主芯片2000安装在板基板3000上。
板基板3000可包括上保护层3200、下保护层3300、上焊盘3400和第四连接构件3500。多个布线图案可形成在主体3100中。上保护层3200和下保护层3300可保护主体3100并且可由例如阻焊剂形成。因为板基板3000被标准化,所以板基板3000的大小减小有限。
第二密封构件5000可密封上半导体封装件1000a和1000g和主芯片2000的侧面和上表面并且可接合到板基板3000的靠外区域。底部填料4000可填充主芯片2000和板基板3000之间的间隙。该间隙可以指的是主芯片2000和板基板3000在此处连接的区域或空间。在本示例实施例中,底部填料4000可形成在其中主芯片2000连接到板基板3000的区域中。然而,当通过MUF工艺形成第二密封构件5000时,可不形成底部填料4000。
图48和图49的芯片堆叠半导体封装件6500b和6500c可具有与图47的芯片堆叠半导体封装件6000a基本上相同或类似的结构,除了上半导体封装件1000a之外。因此,为了方便起见,将省略或简要提供已经参照图47提供的描述。
在图48的芯片堆叠半导体封装件6500b中,上半导体封装件1000a可以是图2的芯片堆叠半导体封装件1000a。因此,可通过芯片之间形成的底部填料320和芯片的侧面上形成的模制构件300来形成密封构件330。
在图49的芯片堆叠半导体封装件6500c中,上半导体封装件1000a可以是图2的芯片堆叠半导体封装件1000a和图4的芯片堆叠半导体封装件1000c。因此,可通过芯片和第一芯片100的侧面之间形成的底部填料320a和芯片的侧面上形成的模制构件300b来形成密封构件330。
图50是根据示例实施例的包括芯片堆叠半导体封装件的存储卡7000的示意性框图。
例如,在存储卡7000中,控制器7100和存储器7200可被布置成彼此交换电信号。例如,当控制器7100发出命令时,存储器7200可发送数据。控制器7100和/或存储器7200可包括根据本发明构思的一个或更多个示例实施例的芯片堆叠半导体封装件中的一个。存储器7200可包括存储器阵列(未示出)或存储器阵列背部(未示出)。
存储卡7000可用于包括各种类型的卡(例如,记忆棒卡、智能媒体卡(SM)、安全数字(SD)、迷你安全数字卡(迷你SD)或多媒体卡(MMC))的存储装置中。
图51是根据示例实施例的包括芯片堆叠半导体封装件的电子系统8000的示意性框图。
例如,电子系统8000可包括控制器8100、输入/输出装置8200、存储器8300和接口8400。电子系统8000可以是移动系统或发送或接收信息的系统。移动系统可以是例如个人数字助理(PDA)、便携式计算机、网络本、无线电话、移动电话、数字音乐播放器或存储卡。
控制器8100可执行程序和/或可控制电子系统8000。控制器8100可以是例如微处理器、数字信号处理器、微控制器等。输入/输出装置8200可用于输入或输出电子系统8000的数据。
电子系统8000可连接到外部装置(例如,个人计算机(PC)或网络)并且可通过使用输入/输出装置8200与外部装置交换数据。输入/输出装置8200可以是例如小型键盘、键盘或显示器。存储器8300可存储供控制器8100操作的代码和/或数据,和/或可存储由控制器8100处理的数据。控制器8100和存储器8300可包括根据本发明构思的一个或更多个示例实施例的芯片堆叠半导体封装件中的一个。接口8400可以是电子系统8000和外部装置之间的数据传输路径。控制器8100、输入/输出装置8200、存储器8300和接口8400可经由总线8500彼此通信。
电子系统8000可用于例如移动电话、MP3播放器、导航装置、便携式多媒体播放器(PMP)、固态盘(SSD)或家用电器。
图52是根据示例实施例的包括芯片堆叠半导体封装件的电子系统8000的透视图。
特别地,图52示出电子系统8000应用于移动电话9000的情况。另外,电子系统8000可用于例如便携式电脑、MP3播放器、导航装置、SSD、车辆或家用电器。
虽然已经参照一些示例实施例具体示出和描述了本发明构思,但应该理解,在不脱离随附权利要求书的精神和范围的情况下,可在其中进行形式和细节上的各种变化。
Claims (25)
1.一种芯片堆叠半导体封装件,所述芯片堆叠半导体封装件包括:
第一芯片,包括多个第一真实凸点焊盘和多个第一虚设凸点焊盘;
第二芯片,在第一芯片上,第二芯片包括多个真实凸点和多个桥接虚设凸点,所述多个真实凸点电连接到所述多个第一真实凸点焊盘,所述多个桥接虚设凸点中的每个物理连接到所述多个第一虚设凸点焊盘中的两个或更多个第一虚设凸点焊盘;
密封构件,密封第一芯片和第二芯片。
2.根据权利要求1所述的芯片堆叠半导体封装件,其中,第一芯片还包括第一芯片主体,
所述多个第一真实凸点焊盘在第一芯片主体的上表面上,
多个第一真实硅穿通孔在第一芯片主体中,并且电连接到所述多个第一真实凸点焊盘。
3.根据权利要求2所述的芯片堆叠半导体封装件,其中,所述多个第一虚设凸点焊盘在第一芯片主体的上表面上,
多个虚设硅穿通孔在第一芯片主体中并且电连接到所述多个第一虚设凸点焊盘。
4.根据权利要求2所述的芯片堆叠半导体封装件,其中,多个连接构件在第一芯片主体的下表面上,所述多个连接构件电连接到所述多个第一真实凸点焊盘和所述多个第一真实硅穿通孔。
5.根据权利要求1所述的芯片堆叠半导体封装件,其中,第二芯片还包括第二芯片主体和第二芯片主体的下表面上的多个第二真实凸点焊盘,
所述多个第二真实凸点焊盘电连接到所述多个真实凸点。
6.根据权利要求5所述的芯片堆叠半导体封装件,其中,第二芯片还包括位于其下表面上的多个第二虚设凸点焊盘,所述多个第二虚设凸点焊盘连接到所述多个桥接虚设凸点。
7.根据权利要求5所述的芯片堆叠半导体封装件,其中,第二芯片主体还包括多个第二真实硅穿通孔,所述多个第二真实硅穿通孔电连接到所述多个第二真实凸点焊盘。
8.根据权利要求6所述的芯片堆叠半导体封装件,其中,第二芯片主体还包括多个虚设硅穿通孔,所述多个虚设硅穿通孔连接到所述多个第二虚设凸点焊盘。
9.根据权利要求6所述的芯片堆叠半导体封装件,其中,所述多个第一虚设凸点焊盘之间的节距和所述多个第二虚设凸点焊盘之间的节距分别小于所述多个第一真实凸点焊盘之间的节距和所述多个第二真实凸点焊盘之间的节距。
10.根据权利要求1所述的芯片堆叠半导体封装件,其中,所述多个桥接虚设凸点彼此分开。
11.根据权利要求1所述的芯片堆叠半导体封装件,其中,密封构件包括底部填料,底部填料处于在第一芯片和第二芯片之间和在第二芯片的侧面上这两种情况中的至少一种。
12.根据权利要求1所述的芯片堆叠半导体封装件,其中,密封构件包括模制构件,模制构件处于第一芯片和第二芯片之间并且在第一芯片与第二芯片的侧面上或者处于第一芯片与第二芯片的侧面和第二芯片的上表面上。
13.根据权利要求1所述的芯片堆叠半导体封装件,其中,密封构件包括:
底部填料,在第一芯片和第二芯片之间并且在第一芯片的侧面上;
模制构件,覆盖底部填料以及第一芯片与第二芯片的侧面或者覆盖第一芯片与第二芯片的侧面以及第二芯片的上表面。
14.一种芯片堆叠半导体封装件,所述芯片堆叠半导体封装件包括:
第一芯片,包括第一真实连接部分和第一虚设连接部分,第一真实连接部分包括多个第一真实凸点焊盘,第一虚设连接部分包括多个第一虚设凸点焊盘并且与第一真实连接部分分开;
第二芯片,在第一芯片的上表面上,第二芯片包括第二真实连接部分和第二虚设连接部分,第二真实连接部分包括与所述多个第一真实凸点焊盘电连接的多个第一真实凸点,第二虚设连接部分与第二真实连接部分分开并且包括多个第一桥接虚设凸点,所述多个第一桥接虚设凸点中的每个物理连接到所述多个第一虚设凸点焊盘中的两个或更多个第一虚设凸点焊盘;
密封构件,密封第一芯片和第二芯片。
15.根据权利要求14所述的芯片堆叠半导体封装件,其中,第一芯片还包括第三真实连接部分,
第三真实连接部分与第一真实连接部分分开并且包括多个第三真实凸点焊盘,
第二芯片还包括第四真实连接部分,第四真实连接部分与第二真实连接部分分开并且包括多个第二真实凸点,所述多个第二真实凸点电连接到所述多个第三真实凸点焊盘。
16.根据权利要求15所述的芯片堆叠半导体封装件,其中,第一芯片还包括第三虚设连接部分,第三虚设连接部分与第一虚设连接部分分开并且包括多个第三虚设凸点焊盘,
第二芯片还包括第四虚设连接部分,第四虚设连接部分与第二虚设连接部分分开并且包括多个第二桥接虚设凸点,所述多个第二桥接虚设凸点连接到第三虚设凸点焊盘。
17.根据权利要求14所述的芯片堆叠半导体封装件,其中,第一芯片还包括第一芯片主体、第一芯片主体中的多个真实硅穿通孔和第一芯片主体的下表面上的多个连接构件,
所述多个真实硅穿通孔连接到所述多个第一真实凸点焊盘,
所述多个连接构件电连接到所述多个第一真实凸点焊盘和所述多个真实硅穿通孔。
18.根据权利要求14所述的芯片堆叠半导体封装件,其中,密封构件包括底部填料和模制构件,底部填料在第一芯片和第二芯片之间。
19.一种芯片堆叠半导体封装件,所述芯片堆叠半导体封装件包括:
第一芯片,包括多个第一真实连接焊盘和多个第一虚设连接焊盘,所述多个第一真实连接焊盘在第一芯片的中心,所述多个第一虚设连接焊盘在第一芯片的边缘;
第二芯片,在第一芯片上,第二芯片包括多个第二真实连接焊盘和多个第二虚设连接焊盘,所述多个第二真实连接焊盘在第二芯片的中心,所述多个第二虚设连接焊盘在第二芯片的边缘;
多个真实连接构件,连接所述多个第一真实连接焊盘和所述多个第二真实连接焊盘;
多个虚设连接构件,连接所述多个第一虚设连接焊盘和所述多个第二虚设连接焊盘,使得虚设连接构件中的每个提供所述多个第一虚设连接焊盘中的两个或更多个和所述多个第二虚设连接焊盘中对应的两个或更多个之间的物理连接;
密封构件,覆盖第一芯片和第二芯片的侧面。
20.根据权利要求19所述的芯片堆叠半导体封装件,其中,所述多个虚设连接构件比所述多个真实连接构件宽。
21.根据权利要求19所述的芯片堆叠半导体封装件,其中,第一芯片还包括与第一真实连接焊盘连接的多个真实硅穿通孔。
22.根据权利要求19所述的芯片堆叠半导体封装件,其中,所述多个第一虚设连接焊盘之间的节距和所述多个第二虚设连接焊盘之间的节距分别小于所述多个第一真实连接焊盘之间的节距和所述多个第二真实连接焊盘之间的节距。
23.根据权利要求19所述的芯片堆叠半导体封装件,其中,密封构件在第一芯片和第二芯片之间。
24.根据权利要求19所述的芯片堆叠半导体封装件,其中,密封构件包括底部填料和模制构件,底部填料在第一芯片和第二芯片之间,模制构件覆盖底部填料。
25.根据权利要求19所述的芯片堆叠半导体封装件,其中,密封构件包括底部填料和模制构件,底部填料部分地在第一芯片的侧面和第二芯片的侧面中的至少一个上,模制构件覆盖底部填料。
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