CN102194987A - 发光装置封装元件 - Google Patents

发光装置封装元件 Download PDF

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CN102194987A
CN102194987A CN201010243652XA CN201010243652A CN102194987A CN 102194987 A CN102194987 A CN 102194987A CN 201010243652X A CN201010243652X A CN 201010243652XA CN 201010243652 A CN201010243652 A CN 201010243652A CN 102194987 A CN102194987 A CN 102194987A
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chip
light
bond pad
emitting device
carrier
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CN102194987B (zh
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王忠裕
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Yuanxin Optoelectronics Co ltd
Epistar Corp
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58Optical field-shaping elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49107Connecting at different heights on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating

Abstract

本发明提供一种发光装置封装元件,该元件包括发光装置芯片与载体芯片。该载体芯片包括第一与第二接合焊盘,于该载体芯片的表面上;以及第三与第四接合焊盘,于该载体芯片的该表面上,并分别电性连接该第一与该第二接合焊盘。该第一、第二、第三与第四接合焊盘位于该载体芯片的相同表面上。该发光装置封装元件还包括第一与第二金属凸块,借由倒装芯片接合分别将该第一与第二接合焊盘接合于该发光装置芯片上;以及窗型模块基板,借由倒装芯片接合与该第三与第四接合焊盘接合。该窗型模块基板包括窗户,该发光装置芯片朝该窗户发射光。本发明的散热能力是高的,其改善优于传统热路径包含低热传导性材料的发光装置封装。

Description

发光装置封装元件
技术领域
本发明涉及一种发光装置(LED)封装元件,特别涉及一种包含基板穿孔(TSV)的发光装置(LED)封装元件。
背景技术
近年来,光学装置,例如发光二级管(LED)、激光二级管与紫外光(UV)光检测器的使用已愈来愈多。第三族氮化物化合物(Group-III nitridecompound),例如氮化镓(GaN)及其相关合金已知适合于光学装置的形成。第三族氮化物化合物的宽能隙(bandgap)与高电子饱和速率(electron saturationvelocity)也使其成为应用于高温与高速功率电子装置的极佳候选人。
由于在一般成长温度下氮的高平衡压力,致获得氮化镓(GaN)主体结晶极为困难。因此,氮化镓(GaN)层与各别发光二级管(LED)通常形成于其他可与氮化镓(GaN)特性匹配的基板上。蓝宝石(sapphire)(氧化铝(Al2O3))为一经常使用的基板材料。图1揭示一发光二级管(LED)封装元件的一剖面图。包括多层氮化镓(GaN)主体层的发光二级管(LED)2形成于蓝宝石基板4上。蓝宝石基板4进一步安装于导线架6上。电极8与10借由金导线12电性连接发光二级管(LED)2至导线架6。
蓝宝石具有一低热传导性,因此,发光二级管(LED)2产生的热无法有效地分散通过蓝宝石基板4。反而,这些热大部分分散通过发光二级管(LED)2的顶端并通过金导线12。然而,金导线12延伸至导线架6的必要长度使得热分散效率下降。此外,电极10占据芯片面积,降低可利用于发光二级管(LED)光输出的总芯片面积。
发明内容
为克服上述现有技术的缺陷,根据本发明一观点,提供一种发光装置封装元件,包括一发光装置芯片与一载体芯片。该载体芯片包括一第一接合焊盘与一第二接合焊盘,于该载体芯片的一表面上;以及一第三接合焊盘与一第四接合焊盘,于该载体芯片的该表面上,并分别电性连接该第一接合焊盘与该第二接合焊盘。该第一接合焊盘、该第二接合焊盘、该第三接合焊盘与该第四接合焊盘位于该载体芯片的相同表面上。该发光装置封装元件还包括一第一金属凸块与一第二金属凸块,借由倒装芯片接合分别将该第一接合焊盘与该第二接合焊盘接合于该发光装置芯片上;以及一窗型模块基板,借由倒装芯片接合与该第三接合焊盘与该第四接合焊盘接合。该窗型模块基板包括一窗户,该发光装置芯片朝该窗户发射光。
本发明也揭示其他实施例。
本发明发光装置封装元件的散热能力是高的,其改善优于传统热路径包含低热传导性材料的发光装置封装。此外,借由发光装置芯片产生的光经由透明材料构成的基板发射出去,并未为任何导线或接合焊盘所阻拦。因此,光输出效率改善优于传统光可能部分为封装元件阻拦的发光装置封装。
为让本发明的上述目的、特征及优点能还明显易懂,下文特举一优选实施例,并配合附图,作详细说明如下:
附图说明
图1为一传统形成于一蓝宝石基板上的发光装置(LED)封装结构的一剖面示意图;
图2~图7是根据本发明不同实施例,一包含一发光装置(LED)的封装元件工艺于中间阶段的剖面示意图;
其中,附图标记说明如下:
公知图1
2~发光二级管;
4~蓝宝石基板;
6~导线架;
8、10~电极;
12~金导线。
本发明图2~图7
20、62~基板;
22~发光装置;
24~未掺杂氮化镓层;
26~n型氮化镓层;
28~多重量子阱;
30~p型氮化镓层;
32~反射器;
34~上电极(接合焊盘);
36、40、70~焊锡凸块;
36_1~伪焊锡凸块;
36_2~活性焊锡凸块;
38、66、66_3、82~接合焊盘;
42~斜面切口;
44~发光装置芯片;
60~载体晶片;
60’~载体芯片;
63~切割道;
64~(热)基板穿孔;
66_1~伪接合焊盘;
66_2~活性接合焊盘;
68~(欧姆)导线;
72、84~填胶;
74~硅透镜;
76~封装元件(结构);
78~窗型模块基板;
80~窗户;
86~热界面材料;
88~散热片。
具体实施方式
本发明提供一种新颖的发光装置(light-emitting device,LED)封装元件(package component)及其形成方法。此处,揭示一工艺中间阶段的实施例,随后并讨论不同实施例。于不同观点与说明实施例中,类似的数字用来标明类似元件。
图2揭示晶片100,其包括形成于基板20上的发光装置(LED)22。在一实施例中,基板20由蓝宝石(sapphire)(透明的氧化铝(Al2O3))所形成,其也可由其他接近发光装置(LED)22中各层特性的材料所形成(可包括第三与第五族元素或已知的三-五族化合物半导体材料)。基板20也可为一碳化硅基板、一具有一碳化硅层于其上的硅基板、一硅锗(silicon germanium)基板或其他可应用的半导体基板。
在一实施例中,未掺杂的氮化镓(u-GaN)层24形成于基板20上并可与其接触。在一实施例中,未掺杂的氮化镓(u-GaN)层24大体上不含镓(Ga)与氮(N)以外的其他元素。发光装置(LED)22形成于未掺杂的氮化镓(u-GaN)层24上并可与其接触。发光装置(LED)22可包括多层。在一实施例中,每一发光装置(LED)22包括n型氮化镓(n-GaN)层(以一n型杂质掺杂氮化镓(GaN))26、多重量子阱(multiple quantum well,MQW)28、p型氮化镓(p-GaN)层(以一p型杂质掺杂氮化镓(GaN))30、反射器32与上电极(也为接合焊盘)34。反射器32可由一金属所形成,例如铝或铜。多重量子阱(MQW)28可由例如氮化铟镓(InGaN)所形成,作为发射光线的活性层。上述各层26、28、30、32与34的形成为已知技术,其细节不在此重赘。在一实施例中,n型氮化镓(n-GaN)层26、多重量子阱(MQW)28与p型氮化镓(p-GaN)层30的形成方法包括外延成长(epitaxial growth)。发光装置(LED)22可具有多种设计,图2仅显示许多可用变化型式中的一典型例子。例如每一n型氮化镓(n-GaN)层26、多重量子阱(MQW)28与p型氮化镓(p-GaN)层30的材料可不同于上述讨论的材料,可包括三元素(ternary)的三-五族化合物半导体材料,例如磷化镓砷(GaAsP)、氮化镓磷(GaPN)、砷化铝铟镓(AlInGaAs)、氮化镓砷磷(GaAsPN)、砷化铝镓(AlGaAs)与其类似物。此外,n型氮化镓(n-GaN)层26与p型氮化镓(p-GaN)层30的位置也可交换。
每一发光装置(LED)22还包括接合焊盘38,用来连接n型氮化镓(n-GaN)层26。因此,接合焊盘34与38用来施予一电压至各别的发光装置(LED)22,以使各别的发光装置(LED)22活化发出光线。在一实施例中,每一发光装置(LED)22中,至少其中之一电极34在使用(发光)发光装置(LED)22的过程中有一电流流经,而一或多个电极34为伪电极(dummy electrode),当施予电压时,并无任何电流流经。
焊锡凸块(solder bump)36(包括活性焊锡凸块36_2与伪焊锡凸块36_1)与40形成于发光装置(LED)22上。焊锡凸块36与40可由一般使用的焊锡材料所形成,例如无铅焊锡(lead-free solder)、共晶焊锡(eutectic solder)或其类似物。于焊锡凸块36与40形成后,晶片100切割成多个发光装置(LED)芯片44,每一发光装置(LED)芯片44包括一或多个发光装置(LED)22。在一实施例中,每一发光装置(LED)芯片44包括一个以上的发光装置(LED)22于一相同基板20上。于相同发光装置(LED)芯片中的发光装置(LED)22称为发光装置(LED)单元。于发光装置(LED)芯片44自晶片100切下后,斜面切口(bevel cut)42(未于图2中显示,请参阅图4)可形成于发光装置(LED)芯片44边缘。因此,各别边缘与各别基板20的表面形成一斜角(不等于90度)。斜面切口42可减少最终封装结构中的应力。
请参阅图3,提供载体晶片60。载体晶片60包括基板62。基板62可为一例如一硅基板的半导体基板或一介电基板。基板穿孔(through-substratevia,TSV)64形成于基板62中,并可电性连接基板62相对侧上的结构。基板穿孔(TSV)64可由铜或其他金属所形成,例如钨或其合金。接合焊盘66(包括接合焊盘66_1、接合焊盘66_2与接合焊盘66_3)形成于载体晶片60的一侧并与基板穿孔(TSV)64连接。
虽在操作过程中施予电压,然伪基板穿孔(TSV)64仅分散热而不用来传导电流。说明书中,伪基板穿孔(TSV)64可称为热基板穿孔(TSV)。在发光装置(LED)操作过程中,设计成有电流流经的接合焊盘66称为活性接合焊盘(active bond pad)66_2,而在发光装置(LED)操作过程中,无电流流经的接合焊盘66,则称为伪接合焊盘(dummy bond pad)66_1。选择性的导线68形成于载体晶片60中或载体晶片60上,以连接接合焊盘。导线68可为殴姆导线或具有可忽略电阻的金属导线。
焊锡凸块(solder bump)70形成于部分接合焊盘66(以下称为接合焊盘66_3)上。接合焊盘66_3借由导线68连接至活性接合焊盘66_2。
请参阅图4,多个自晶片100切下的发光装置(LED)芯片44借由倒装芯片接合接合至载体晶片60上。在接合的过程中,焊锡凸块36与40回焊(re-flowed)。两焊锡凸块36与40与不同的接合焊盘66与34/38接触。图中可看出,较高的焊锡凸块70邻近发光装置(LED)芯片44,且借由例如欧姆导线68电性连接活性接合焊盘66_2。焊锡凸块70的顶端延伸超过基板20的背表面。填胶72可选择性地填入发光装置(LED)芯片44与载体晶片60之间的空隙。斜面切口42有利于减少填胶72。
载体晶片60随后可沿切割道63切开分成多个封装元件76,每一封装元件76包括一个载体芯片60’(如图5A所示),且每一载体芯片60’接合上至少一发光装置(LED)芯片44。请参阅图5A,硅透镜74铸造于发光装置(LED)芯片44上,以形成封装结构76。硅透镜74与其模具为已知技术,遂细节不在此重赘。硅透镜74可覆盖发光装置(LED)芯片44。在无使用填胶(underfill)72的实施例中,硅将填入发光装置(LED)芯片44与载体芯片60’之间的空隙,因此,以硅代替实施填胶(underfill)72的功能。在一特定实施例中,焊锡凸块70不为硅透镜74所覆盖而曝露在外。
请参阅图5A,封装结构76借由倒装芯片接合(flip-chup bonding)接合于窗型模块基板78上。窗型模块基板78可由FR4、一强化金属核心基板(metalcore-enhanced substrate)、一陶瓷基板或一有机基板所形成。窗型模块基板78包括窗户80,其尺寸符合硅透镜74的尺寸。因此,硅透镜74延伸进入窗户80且包括窗型模块基板78相对侧上的部分。接合焊盘82形成于窗型模块基板78上。于焊锡凸块70回焊后,接合焊盘82借由焊锡凸块70接合于接合焊盘66_3上。制作进一步电性连接(未图示)至接合焊盘82,以施予一电压至发光装置(LED)芯片44,一电流将流经电性连接、接合焊盘82与焊锡凸块70。图5B为图5A所示结构的一仰视图,其中图5A为图5B沿剖面线5A-5A所得的剖面图。
请参阅图6,填胶84填入封装结构76与窗型模块基板78之间的空隙,以保护焊锡凸块70。接着,如图7所示,散热片(heat sink)88安装于载体芯片60’上,并设计成与输入/输出电流电性隔绝。在一实施例中,散热片88借由热界面材料(thermal interface material,TIM)86与载体芯片60’连接,热界面材料(TIM)86可由一具有一高热传导性的介电材料所形成。热界面材料(TIM)86可由一可分散于载体芯片60’上的有机膏(organic paste)或纯合金或金属所形成。于散热片88安装于载体芯片60’后,进行热回焊(thermalre-flowed)或烘烤。于发光装置(LED)芯片44中产生的热可分散至载体芯片60’,的后再散至散热片88。由图中可看出,自发光装置(LED)芯片44至散热片88,并无低热传导性的材料。因此,发光装置(LED)芯片44与散热片88之间路径中的热阻是低的,使得所述结构可达到高的热分散效率(heat-dissipating efficiency)。因此,本发明封装结构适合用于热分散对其最适元件操作来说极为重要的高功率发光装置(LED)元件。
当一电压施予发光装置(LED)芯片44至发光时,伪焊锡凸块36_1并未有任何电流流经。然而,伪焊锡凸块36_1可帮助传导发光装置(LED)芯片44中产生的热通过载体芯片60’至散热片88。
由于发光装置(LED)芯片44先借由倒装芯片接合(flip-chipbonding)接合至载体芯片60’,得到的封装元件再进一步接合至其他电路元件,例如借由一额外的倒装芯片接合再接合至窗型模块基板78,因此,图7所示结构称为一双倒装芯片封装元件(double flip-chippackage component)。此种接合方式可使光以一方向(例如朝向图7的底部)发射,而热则朝其相反方向散失,因此,可同时提升发光与散热效率。例如发光装置(LED)芯片44中产生的热可借由多个伪焊锡凸块36_1、热基板穿孔(TSV)64与载体芯片60’分散进入散热片88。因此,根据不同实施例,本发明发光装置(LED)封装元件的散热能力是高的,其改善优于传统热路径包含低热传导性材料的发光装置(LED)封装。此外,借由发光装置(LED)芯片44产生的光经由透明材料构成的基板20发射出去,并未为任何导线或接合焊盘所阻拦。因此,光输出效率改善优于传统光可能部分为封装元件阻拦的发光装置(LED)封装。
虽然本发明已以优选实施例揭示如上,然而其并非用以限定本发明,任何本领域技术人员,在不脱离本发明的精神和范围内,当可作还动与润饰,因此本发明的保护范围当视随附的权利要求所界定的范围为准。

Claims (10)

1.一种发光装置封装元件,包括:
一发光装置芯片;
一载体芯片,包括:
一第一接合焊盘与一第二接合焊盘,于该载体芯片的一表面上;以及
一第三接合焊盘与一第四接合焊盘,于该载体芯片的该表面上,并分别电性连接该第一接合焊盘与该第二接合焊盘,其中该第一接合焊盘、该第二接合焊盘、该第三接合焊盘与该第四接合焊盘位于该载体芯片的相同表面上;
一第一金属凸块与一第二金属凸块,借由倒装芯片接合分别将该第一接合焊盘与该第二接合焊盘接合于该发光装置芯片上;以及
一窗型模块基板,借由倒装芯片接合与该第三接合焊盘与该第四接合焊盘接合,其中该窗型模块基板包括一窗户,该发光装置芯片朝该窗户发射光。
2.如权利要求1所述的发光装置封装元件,其中该发光装置芯片包括两电极,电性连接该第一接合焊盘与该第二接合焊盘。
3.如权利要求1所述的发光装置封装元件,还包括一伪基板穿孔,于该载体芯片中,其中该伪基板穿孔电性连接该第一金属凸块,当该发光装置芯片发射光时,该伪基板穿孔未通过任何电流。
4.如权利要求1所述的发光装置封装元件,还包括一散热片与一热界面材料,该热界面材料邻近与位于该散热片与该载体芯片之间。
5.一种发光装置封装元件,包括:
一窗型模块基板,包括:
一窗户;以及
一第一接合焊盘与一第二接合焊盘,于该窗型模块基板的一表面上,邻近该窗户;
一载体芯片,包括:
一第三接合焊盘与一第四接合焊盘,于该载体芯片的一第一侧上;以及
一伪基板穿孔,于该载体芯片中;
一第一焊锡凸块与一第二焊锡凸块,借由倒装芯片接合分别将该窗型模块基板的该第一接合焊盘与该第二接合焊盘接合于该载体芯片的该第三接合焊盘与该第四接合焊盘;以及
一发光装置芯片,借由倒装芯片接合与该载体芯片接合,其中该发光装置芯片位于该载体芯片的该第一侧上并重迭至少一部分的该窗户。
6.如权利要求5所述的发光装置封装元件,其中该发光装置芯片包括两电极,电性连接该载体芯片的该第三接合焊盘与该第四接合焊盘。
7.如权利要求5所述的发光装置封装元件,还包括一散热片与一热界面材料,该散热片位于该载体芯片的一第二侧上,该第二侧相对于该第一侧,该热界面材料邻近与位于该散热片与该载体芯片之间。
8.如权利要求5所述的发光装置封装元件,还包括一伪焊锡凸块,电性连接该伪基板穿孔至该发光装置芯片的一电极,其中当一电压施予该窗型模块基板的该第一接合焊盘与该第二接合焊盘时,该伪焊锡凸块未通过任何电流。
9.一种发光装置封装元件,包括:
一载体芯片,包括:
一伪基板穿孔,自该载体芯片的一主要侧延伸至该载体芯片的一相对侧;以及
一第一接合焊盘与一第二接合焊盘,于该载体芯片的该主要侧上,彼此电性连接;
一窗型模块基板,借由倒装芯片接合与该载体芯片的该第一接合焊盘接合,其中该窗型模块基板包括一窗户;以及
一发光装置芯片,借由倒装芯片接合与该载体芯片的该第二接合焊盘接合。
10.如权利要求9所述的发光装置封装元件,还包括一散热片与一热界面材料,该热界面材料邻近与位于该散热片与该载体芯片之间。
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