TWI535075B - 發光裝置封裝元件 - Google Patents

發光裝置封裝元件 Download PDF

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TWI535075B
TWI535075B TW099124661A TW99124661A TWI535075B TW I535075 B TWI535075 B TW I535075B TW 099124661 A TW099124661 A TW 099124661A TW 99124661 A TW99124661 A TW 99124661A TW I535075 B TWI535075 B TW I535075B
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bonding pad
carrier wafer
emitting device
wafer
bonding
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TW201131830A (en
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王忠裕
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晶元光電股份有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58Optical field-shaping elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49107Connecting at different heights on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Description

發光裝置封裝元件
本發明係有關於一種發光裝置(LED)封裝元件,特別是有關於一種包含基板穿孔(TSV)之發光裝置(LED)封裝元件。
近年來,光學裝置,例如發光二極體(LED)、雷射二極體與紫外光(UV)光偵測器的使用已愈來愈多。第三族氮化物化合物(Group-III nitride compound),例如氮化鎵(GaN)及其相關合金已知適合於光學裝置的形成。第三族氮化物化合物的寬能隙(bandgap)與高電子飽和速率(electron saturation velocity)亦使其成為應用於高溫與高速功率電子裝置的極佳候選人。
由於在一般成長溫度下氮的高平衡壓力,致獲得氮化鎵(GaN)主體結晶極為困難。因此,氮化鎵(GaN)層與各別發光二極體(LED)通常形成於其他可與氮化鎵(GaN)特性匹配的基板上。藍寶石(sapphire)(氧化鋁(Al2O3))為一經常使用的基板材料。第1圖揭露一發光二極體(LED)封裝元件的一剖面圖。包括複數層氮化鎵(GaN)主體層的發光二極體(LED) 2形成於藍寶石基板4上。藍寶石基板4進一步安裝於導線架6上。電極8與10藉由金導線12電性連接發光二極體(LED) 2至導線架6。
藍寶石具有一低熱傳導性,因此,發光二極體(LED) 2產生的熱無法有效地分散通過藍寶石基板4。反而,這些熱大部分分散通過發光二極體(LED) 2的頂端並通過金導線12。然而,金導線12延伸至導線架6的必要長度使得熱分散效率下降。此外,電極10佔據晶片面積,降低可利用於發光二極體(LED)光輸出的總晶片面積。
根據本發明一觀點,提供一種發光裝置封裝元件,包括一發光裝置晶片與一載體晶片。該載體晶片包括一第一接合墊與一第二接合墊,於該載體晶片之一表面上;以及一第三接合墊與一第四接合墊,於該載體晶片之該表面上,並分別電性連接該第一接合墊與該第二接合墊。該第一接合墊、該第二接合墊、該第三接合墊與該第四接合墊位於該載體晶片之相同表面上。該發光裝置封裝元件更包括一第一金屬凸塊與一第二金屬凸塊,藉由覆晶接合分別將該第一接合墊與該第二接合墊接合於該發光裝置晶片上;以及一窗型模組基板,藉由覆晶接合與該第三接合墊與該第四接合墊接合。該窗型模組基板包括一窗戶,該發光裝置晶片朝該窗戶發射光。
本發明亦揭露其他實施例。
為讓本發明之上述目的、特徵及優點能更明顯易懂,下文特舉一較佳實施例,並配合所附圖式,作詳細說明如下:
本發明提供一種新穎的發光裝置(light-emitting device,LED)封裝元件(package component)及其形成方法。此處,揭露一製程中間階段的實施例,隨後並討論不同實施例。於不同觀點與說明實施例中,類似的數字用來標明類似元件。
第2圖揭露晶圓100,其包括形成於基板20上的發光裝置(LED) 22。在一實施例中,基板20由藍寶石(sapphire)(透明的氧化鋁(Al2O3))所形成,其亦可由其他接近發光裝置(LED) 22中各層特性的材料所形成(可包括第三與第五族元素或已知的三-五族化合物半導體材料)。基板20亦可為一碳化矽基板、一具有一碳化矽層於其上的矽基板、一矽鍺(silicon germanium)基板或其他可應用的半導體基板。
在一實施例中,未摻雜的氮化鎵(u-GaN)層24形成於基板20上並可與其接觸。在一實施例中,未摻雜的氮化鎵(u-GaN)層24大體上不含鎵(Ga)與氮(N)以外的其他元素。發光裝置(LED) 22形成於未摻雜的氮化鎵(u-GaN)層24上並可與其接觸。發光裝置(LED) 22可包括複數層。在一實施例中,每一發光裝置(LED) 22包括n型氮化鎵(n-GaN)層(以一n型雜質摻雜氮化鎵(GaN)) 26、多重量子井(multiple quantum well,MQW) 28、p型氮化鎵(p-GaN)層(以一p型雜質摻雜氮化鎵(GaN)) 30、反射器32與上電極(亦為接合墊) 34。反射器32可由一金屬所形成,例如鋁或銅。多重量子井(MQW) 28可由例如氮化銦鎵(InGaN)所形成,作為發射光線的活性層。上述各層26、28、30、32與34的形成為已知技術,其細節不在此重贅。在一實施例中,n型氮化鎵(n-GaN)層26、多重量子井(MQW) 28與p型氮化鎵(p-GaN)層30的形成方法包括磊晶成長(epitaxial growth)。發光裝置(LED) 22可具有多種設計,第2圖僅顯示許多可用變化型式中的一典型例子。例如每一n型氮化鎵(n-GaN)層26、多重量子井(MQW) 28與p型氮化鎵(p-GaN)層30的材料可不同於上述討論的材料,可包括三元素(ternary)的三-五族化合物半導體材料,例如磷化鎵砷(GaAsP)、氮化鎵磷(GaPN)、砷化鋁銦鎵(AlInGaAs)、氮化鎵砷磷(GaAsPN)、砷化鋁鎵(AlGaAs)與其類似物。此外,n型氮化鎵(n-GaN)層26與p型氮化鎵(p-GaN)層30的位置亦可交換。
每一發光裝置(LED) 22更包括接合墊38,用來連接n型氮化鎵(n-GaN)層26。因此,接合墊34與38用來施予一電壓至各別的發光裝置(LED) 22,以使各別的發光裝置(LED) 22活化發出光線。在一實施例中,每一發光裝置(LED) 22中,至少其中之一電極34在使用(發光)發光裝置(LED) 22的過程中有一電流流經,而一或多個電極34為偽電極(dummy electrode),當施予電壓時,並無任何電流流經。
銲錫凸塊(solder bump) 36(包括活性銲錫凸塊36_2與偽銲錫凸塊36_1)與40形成於發光裝置(LED) 22上。銲錫凸塊36與40可由一般使用的銲錫材料所形成,例如無鉛銲錫(lead-free solder)、共晶銲錫(eutectic solder)或其類似物。於銲錫凸塊36與40形成後,晶圓100切割成複數個發光裝置(LED)晶片44,每一發光裝置(LED)晶片44包括一或多個發光裝置(LED) 22。在一實施例中,每一發光裝置(LED)晶片44包括一個以上的發光裝置(LED) 22於一相同基板20上。於相同發光裝置(LED)晶片中的發光裝置(LED) 22稱為發光裝置(LED)單元。於發光裝置(LED)晶片44自晶圓100切下後,斜面切口(bevel cut) 42(未於第2圖中顯示,請參閱第4圖)可形成於發光裝置(LED)晶片44邊緣。因此,各別邊緣與各別基板20的表面形成一斜角(不等於90度)。斜面切口42可減少最終封裝結構中的應力。
請參閱第3圖,提供載體晶圓60。載體晶圓60包括基板62。基板62可為一例如一矽基板的半導體基板或一介電基板。基板穿孔(through-substrate via,TSV) 64形成於基板62中,並可電性連接基板62相對側上的結構。基板穿孔(TSV) 64可由銅或其他金屬所形成,例如鎢或其合金。接合墊66(包括接合墊66_1、接合墊66_2與接合墊66_3)形成於載體晶圓60的一側並與基板穿孔(TSV)64連接。
雖在操作過程中施予電壓,然偽基板穿孔(TSV) 64僅分散熱而不用來傳導電流。說明書中,偽基板穿孔(TSV) 64可稱為熱基板穿孔(TSV)。在發光裝置(LED)操作過程中,設計成有電流流經的接合墊66稱為活性接合墊(active bond pad) 66_2,而在發光裝置(LED)操作過程中,無電流流經的接合墊66,則稱為偽接合墊(dummy bond pad) 66_1。選擇性的導線68形成於載體晶圓60中或載體晶圓60上,以連接接合墊。導線68可為毆姆導線或具有可忽略電阻的金屬導線。
銲錫凸塊(solder bump) 70形成於部分接合墊66(以下稱為接合墊66_3)上。接合墊66_3藉由導線68連接至活性接合墊66_2。
請參閱第4圖,複數個自晶圓100切下的發光裝置(LED)晶片44藉由覆晶接合接合至載體晶圓60上。在接合的過程中,銲錫凸塊36與40迴銲(re-flowed)。兩銲錫凸塊36與40與不同的接合墊66與34/38接觸。圖中可看出,較高的銲錫凸塊70鄰近發光裝置(LED)晶片44,且藉由例如歐姆導線68電性連接活性接合墊66_2。銲錫凸塊70的頂端延伸超過基板20的背表面。填膠72可選擇性地填入發光裝置(LED)晶片44與載體晶圓60之間的空隙。斜面切口42有利於減少填膠72。
載體晶圓60隨後可沿切割道63切開分成複數個封裝元件76,每一封裝元件76包括一個載體晶片60’(如第5A圖所示),且每一載體晶片60’接合上至少一發光裝置(LED)晶片44。請參閱第5A圖,矽透鏡74鑄造於發光裝置(LED)晶片44上,以形成封裝結構76。矽透鏡74與其模具為已知技術,遂細節不在此重贅。矽透鏡74可覆蓋發光裝置(LED)晶片44。在無使用填膠(underfill) 72的實施例中,矽將填入發光裝置(LED)晶片44與載體晶片60’之間的空隙,因此,以矽代替實施填膠(underfill) 72的功能。在一特定實施例中,銲錫凸塊70不為矽透鏡74所覆蓋而曝露在外。
請參閱第5A圖,封裝結構76藉由覆晶接合(flip-chup bonding)接合於窗型模組基板78上。窗型模組基板78可由FR4、一強化金屬核心基板(metal core-enhanced substrate)、一陶瓷基板或一有機基板所形成。窗型模組基板78包括窗戶80,其尺寸符合矽透鏡74的尺寸。因此,矽透鏡74延伸進入窗戶80且包括窗型模組基板78相對側上的部分。接合墊82形成於窗型模組基板78上。於銲錫凸塊70迴銲後,接合墊82藉由銲錫凸塊70接合於接合墊66_3上。製作進一步電性連接(未圖示)至接合墊82,以施予一電壓至發光裝置(LED)晶片44,一電流將流經電性連接、接合墊82與銲錫凸塊70。第5B圖為第5A圖所示結構的一下視圖,其中第5A圖為第5B圖沿剖面線5A-5A所得的剖面圖。
請參閱第6圖,填膠84填入封裝結構76與窗型模組基板78之間的空隙,以保護銲錫凸塊70。接著,如第7圖所示,散熱片(heat sink) 88安裝於載體晶片60’上,並設計成與輸入/輸出電流電性隔絕。在一實施例中,散熱片88藉由熱介面材料(thermal interface material,TIM)86與載體晶片60’連接,熱介面材料(TIM) 86可由一具有一高熱傳導性的介電材料所形成。熱介面材料(TIM) 86可由一可分散於載體晶片60’上的有機膏(organic paste)或純合金或金屬所形成。於散熱片88安裝於載體晶片60’後,進行熱迴銲(thermal re-flowed)或烘烤。於發光裝置(LED)晶片44中產生的熱可分散至載體晶片60’,之後再散至散熱片88。由圖中可看出,自發光裝置(LED)晶片44至散熱片88,並無低熱傳導性的材料。因此,發光裝置(LED)晶片44與散熱片88之間路徑中的熱阻是低的,使得所述結構可達到高的熱分散效率(heat-dissipating efficiency)。因此,本發明封裝結構適合用於熱分散對其最適元件操作來說極為重要的高功率發光裝置(LED)元件。
當一電壓施予發光裝置(LED)晶片44至發光時,偽銲錫凸塊36_1並未有任何電流流經。然而,偽銲錫凸塊36_1可幫助傳導發光裝置(LED)晶片44中產生的熱通過載體晶片60’至散熱片88。
由於發光裝置(LED)晶片44先藉由覆晶接合(flip-chip bonding)接合至載體晶片60’,得到的封裝元件再進一步接合至其他電路元件,例如藉由一額外的覆晶接合再接合至窗型模組基板78,因此,第7圖所示結構稱為一雙覆晶封裝元件(double flip-chip package component)。此種接合方式可使光以一方向(例如朝向第7圖的底部)發射,而熱則朝其相反方向散失,因此,可同時提升發光與散熱效率。例如發光裝置(LED)晶片44中產生的熱可藉由多個偽銲錫凸塊36_1、熱基板穿孔(TSV) 64與載體晶片60’分散進入散熱片88。因此,根據不同實施例,本發明發光裝置(LED)封裝元件的散熱能力是高的,其改善優於傳統熱路徑包含低熱傳導性材料的發光裝置(LED)封裝。此外,藉由發光裝置(LED)晶片44產生的光經由透明材料構成的基板20發射出去,並未為任何導線或接合墊所阻攔。因此,光輸出效率改善優於傳統光可能部分為封裝元件阻攔的發光裝置(LED)封裝。
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此項技藝者,在不脫離本發明之精神和範圍內,當可作更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
習知第1圖
2...發光二極體
4...藍寶石基板
6...導線架
8、10...電極
12...金導線
本發明第2~7圖
20、62...基板
22...發光裝置
24...未摻雜氮化鎵層
26...n型氮化鎵層
28...多重量子井
30...p型氮化鎵層
32...反射器
34...上電極(接合墊)
36、40、70...銲錫凸塊
36_1...偽銲錫凸塊
36_2...活性銲錫凸塊
38、66、66_3、82...接合墊
42...斜面切口
44...發光裝置晶片
60...載體晶圓
60’...載體晶片
63...切割道
64...(熱)基板穿孔
66_1...偽接合墊
66_2...活性接合墊
68...(歐姆)導線
72、84...填膠
74...矽透鏡
76...封裝元件(結構)
78...窗型模組基板
80...窗戶
86...熱介面材料
88...散熱片
第1圖係為一傳統形成於一藍寶石基板上的發光裝置(LED)封裝結構的一剖面示意圖;
第2~5A、5B、6、7圖係根據本發明不同實施例,一包含一發光裝置(LED)的封裝元件製程於中間階段的剖面示意圖。
36_1...偽銲錫凸塊
44...發光裝置晶片
60’...載體晶片
64...(熱)基板穿孔
68...(歐姆)導線
70...銲錫凸塊
74...矽透鏡
76...封裝元件(結構)
78...窗型模組基板
82...接合墊
84...填膠
86...熱介面材料
88...散熱片

Claims (10)

  1. 一種發光裝置封裝元件,包括:一發光裝置晶片,具有一斜面切口,形成於該發光裝置晶片之邊緣;一載體晶片,包括:一第一接合墊與一第二接合墊,於該載體晶片之一表面上;以及一第三接合墊與一第四接合墊,於該載體晶片之該表面上,並分別電性連接該第一接合墊與該第二接合墊,其中該第一接合墊、該第二接合墊、該第三接合墊與該第四接合墊位於該載體晶片之相同表面上;一歐姆導線,電性連接該第一接合墊與該第三接合墊;一第一金屬凸塊與一第二金屬凸塊,藉由覆晶接合分別將該第一接合墊與該第二接合墊接合於該發光裝置晶片上;以及一窗型模組基板,藉由覆晶接合與該第三接合墊與該第四接合墊接合,其中該窗型模組基板包括一窗戶,該發光裝置晶片朝該窗戶發射光。
  2. 如申請專利範圍第1項所述之發光裝置封裝元件,其中該發光裝置晶片包括兩電極,電性連接該第一接合墊與該第二接合墊。
  3. 如申請專利範圍第1項所述之發光裝置封裝元件,更包括一偽基板穿孔,於該載體晶片中,其中該偽基板穿孔電性連接該第一金屬凸塊,當該發光裝置晶片 發射光時,該偽基板穿孔未通過任何電流。
  4. 如申請專利範圍第1項所述之發光裝置封裝元件,更包括一散熱片與一熱介面材料,該熱介面材料鄰近與位於該散熱片與該載體晶片之間。
  5. 一種發光裝置封裝元件,包括:一窗型模組基板,包括:一窗戶;以及一第一接合墊與一第二接合墊,於該窗型模組基板之一表面上,鄰近該窗戶;一載體晶片,包括:一第三接合墊與一第四接合墊,於該載體晶片之一第一側上;以及一偽基板穿孔,於該載體晶片中;一歐姆導線,電性連接該第三接合墊;一第一銲錫凸塊與一第二銲錫凸塊,藉由覆晶接合分別將該窗型模組基板之該第一接合墊與該第二接合墊接合於該載體晶片之該第三接合墊與該第四接合墊;以及一發光裝置晶片,具有一斜面切口,形成於該發光裝置晶片之邊緣,藉由覆晶接合與該載體晶片接合,其中該發光裝置晶片位於該載體晶片之該第一側上並重疊至少一部分之該窗戶。
  6. 如申請專利範圍第5項所述之發光裝置封裝元件,其中該發光裝置晶片包括兩電極,電性連接該載體晶片之該第三接合墊與該第四接合墊。
  7. 如申請專利範圍第5項所述之發光裝置封裝元件,更包括一散熱片與一熱介面材料,該散熱片位於該載體晶片之一第二側上,該第二側相對於該第一側,該熱介面材料鄰近與位於該散熱片與該載體晶片之間。
  8. 如申請專利範圍第5項所述之發光裝置封裝元件,更包括一偽銲錫凸塊,電性連接該偽基板穿孔至該發光裝置晶片之一電極,其中當一電壓施予該窗型模組基板之該第一接合墊與該第二接合墊時,該偽銲錫凸塊未通過任何電流。
  9. 一種發光裝置封裝元件,包括:一載體晶片,包括:一偽基板穿孔,自該載體晶片之一主要側延伸至該載體晶片之一相對側;以及一第一接合墊與一第二接合墊,於該載體晶片之該主要側上,彼此電性連接;一歐姆導線,電性連接該第一接合墊與該第二接合墊;一窗型模組基板,藉由覆晶接合與該載體晶片之該第一接合墊接合,其中該窗型模組基板包括一窗戶;以及一發光裝置晶片,具有一斜面切口,形成於該發光裝置晶片之邊緣,藉由覆晶接合與該載體晶片之該第二接合墊接合。
  10. 如申請專利範圍第9項所述之發光裝置封裝元件,更包括一散熱片與一熱介面材料,該熱介面材料鄰 近與位於該散熱片與該載體晶片之間。
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CN102194987A (zh) 2011-09-21
US8183578B2 (en) 2012-05-22
US20110215354A1 (en) 2011-09-08
TW201131830A (en) 2011-09-16
CN102194987B (zh) 2013-06-12

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