JP7201771B2 - semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

In this specification, the term "semiconductor device" refers to all devices that can function by utilizing semiconductor characteristics, and electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices.

A technique for forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.

For example, disclosed is a transistor using an amorphous oxide containing indium (In), gallium (Ga), and zinc (Zn) with an electron carrier concentration of less than 10 ¹⁸ /cm ³ as an active layer of the transistor. (See Patent Document 1.).

A transistor using an oxide semiconductor operates faster than a transistor using amorphous silicon and is easier to manufacture than a transistor using polycrystalline silicon.
A known problem is that the electrical characteristics tend to fluctuate and the reliability is low. For example, the threshold voltage of a transistor fluctuates after a bias-thermal stress test (BT test). Note that in this specification, a threshold voltage refers to a gate voltage required to turn on a transistor. The gate voltage is a potential difference between the source potential and the gate potential.

JP 2006-165528 A

Fluctuation in threshold voltage of a transistor including an oxide semiconductor in a BT test significantly reduces reliability of the transistor including an oxide semiconductor. An object of one embodiment of the present invention is to improve reliability of a semiconductor device including an oxide semiconductor.

In one embodiment of the present invention, an insulating layer that releases oxygen by heating is used as an insulating layer in contact with a channel region of an oxide semiconductor layer, and an insulating layer in contact with a source region and a drain region of an oxide semiconductor layer has an amount of oxygen released. is a semiconductor device or a method of manufacturing a semiconductor device based on the technical idea of using an insulating layer less than the insulating layer in contact with the channel region.

One embodiment of the present invention includes an insulating layer having a first region and a second region;
and an oxide semiconductor layer having a channel region, a source region, and a drain region provided in contact with the region of the oxide semiconductor layer, wherein the channel region of the oxide semiconductor layer is provided in contact with the first region, the oxide semiconductor The source region and the drain region of the layer are provided in contact with the second region, the first region is an insulating layer that releases oxygen by heating, and the second region has the first oxygen release amount. A semiconductor device or method of making a semiconductor device with fewer insulating layers.

"Releasing oxygen by heating" means TDS (Thermal Desorption
Spectroscopy (temperature-programmed desorption spectroscopy) analysis shows that the amount of oxygen released in terms of oxygen atoms is 1×10 ¹⁸ atoms/cm ³ or more, preferably 3×10 ²⁰ atoms/cm3.
cm ³ or more.

By supplying oxygen to the channel region from the first region, which is an insulating layer in contact with the channel region, the interface state density between the channel region and the first region can be reduced. As a result, it is possible to sufficiently suppress trapping of charges and the like, which may be caused by the operation of the semiconductor device, at the interface between the first region and the channel region.

Furthermore, charges may be generated due to oxygen vacancies in the channel region. In general, oxygen vacancies in the channel region partially become donors and generate electrons that are carriers. As a result, the threshold voltage of the transistor shifts in the negative direction. Oxygen is sufficiently released from the first region, which is an insulating layer in contact with the channel region, to the channel region, so that oxygen vacancies in the channel region, which is a factor causing the threshold voltage to shift in the negative direction, can be compensated for. .

That is, when oxygen vacancies occur in the channel region, it becomes difficult to suppress charge trapping at the interface between the channel region and the first region, which is an insulating layer in contact with the channel region. By providing the insulating layer that releases oxygen, the interface state density between the channel region and the first region and oxygen vacancies in the channel region are reduced, and charge trapping at the interface between the channel region and the first region is reduced. can reduce the impact.

Further, the source region and the drain region are provided in contact with the second region that releases less oxygen than the first region, so that oxygen is not supplied to the source region and the drain region. This structure focuses on the fact that part of the oxygen vacancies in the oxide semiconductor layer serves as a source of electrons, which are carriers. In other words, it is based on the technical idea that the supply of oxygen reduces oxygen vacancies and suppresses an increase in the resistance of the source region and the drain region. For example, as the second region in contact with the source region and the drain region, TDS
An insulating layer that releases less than 1×10 ¹⁸ atoms/cm ³ of oxygen by analysis can be used.

Thus, the effect of one embodiment of the present invention is due to the insulating layer that releases oxygen by heating and the insulating layer that releases less oxygen than the insulating layer.

The effect of suppressing the capture of charges at the interface of the channel region of the oxide semiconductor layer and suppressing the increase in the resistance of the source region and the drain region causes the source region and the drain region to have a high resistance. In addition, it is possible to suppress the problem that the on-current of the transistor is lowered due to the contribution of the decrease in the current flowing through the drain region. Further, defects such as an increase in off-state current and a change in threshold voltage of a transistor including an oxide semiconductor can be suppressed. In addition, reliability of the semiconductor device can be improved.

Note that the insulating layer from which oxygen is released by heating preferably has a sufficient thickness with respect to the oxide semiconductor layer. This is because when the insulating layer that releases oxygen by heating is thinner than the oxide semiconductor layer, oxygen supply to the oxide semiconductor layer may be insufficient.

One embodiment of the present invention includes an insulating layer having a first region and a second region;
an oxide semiconductor layer provided in contact with a region of and having a channel region, a source region, and a drain region; a gate insulating layer provided in contact with the oxide semiconductor layer; and a gate electrode provided in contact with the gate insulating layer and a channel region of the oxide semiconductor layer is provided in contact with the first region; a source region and a drain region of the oxide semiconductor layer are provided in contact with the second region; The region is an insulating layer that releases oxygen by heating, and the second region is an insulating layer that releases less oxygen than the first region, or a method for manufacturing a semiconductor device. In the first region and the second region, a material having the same constituent elements, a material having two or more constituent elements that are the same, or materials having different constituent elements may be used.

In the above structure, the insulating layer that releases oxygen when heated is made of oxygen-excess silicon oxide (
SiO _X (X>2)). Silicon oxide with excess oxygen (SiO _X (X>2)
) contains more than twice as many oxygen atoms as silicon atoms per unit volume. The number of silicon atoms and the number of oxygen atoms per unit volume are values measured by the Rutherford backscattering method.

In the above structure, silicon oxide, silicon oxynitride, or aluminum oxide may be used for the insulating layer from which oxygen is released by heating. Silicon oxide, silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum nitride, or aluminum oxynitride may be used for the insulating layer that releases less oxygen than the first region. Alternatively, materials having different constituent elements may be used for the first region and the second region. For example, silicon oxide is used for the insulating layer that releases oxygen by heating, and silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum nitride, or silicon oxide is used for the insulating layer that releases less oxygen than the first region. Aluminum oxynitride may also be used. For example, when silicon oxide is used for the first region, aluminum oxide, which has a lower diffusion coefficient of oxygen than silicon oxide at an arbitrary temperature, is preferably used for the second region. By providing the second region having an oxygen diffusion coefficient lower than that of the first region, the amount of oxygen released in the first region diffusing into the second region can be reduced.

Here, silicon oxynitride refers to a composition in which the content of oxygen is higher than that of nitrogen.
atomic % or less, 25 atomic % or more and 35 atomic % or less of silicon, 0 atomic % or more and 10 atomic % of hydrogen
It refers to what is included in the following range. Further, silicon oxynitride indicates a composition in which the content of nitrogen is higher than that of oxygen.
It contains 20 atomic % to 55 atomic % of nitrogen, 25 atomic % to 35 atomic % of silicon, and 10 atomic % to 25 atomic % of hydrogen. However, the above range is the Rutherford Backscattering method (RBS: Rutherford Backscattering
Spectrometry) and hydrogen forward scattering method (HFS: Hydrogen Forw
It is the one when measured using Hard Scattering. Moreover, the total content of the constituent elements does not exceed 100 atomic %. What is aluminum oxynitride
It indicates that the composition contains more oxygen than nitrogen.

Moreover, in the above structure, it is preferable that the surface of the first region and the surface of the second region are aligned. In other words, the thickness of the first region and the thickness of the second region are preferably the same.
Alternatively, it is preferable that the surface of the first region and the surface of the second region are formed continuously near the boundary between the first region and the second region.

Further, in the above structure, it is possible to adopt a structure in which the second region is not provided. In this case, a first insulating layer may be selectively provided over the substrate, and the first insulating layer may be used as an insulating layer that releases oxygen by heating. Alternatively, a second insulating layer may be provided over a substrate, a first insulating layer may be selectively provided over the second insulating layer, and the first insulating layer may be used as an insulating layer that releases oxygen by heating. .

That is, in one embodiment of the present invention, a first insulating layer selectively provided over a substrate or a second insulating layer provided over the substrate, the substrate or the second insulating layer, and the first insulating layer An oxide semiconductor layer provided in contact with an insulating layer and having a channel region, a source region, and a drain region, a gate insulating layer provided in contact with the oxide semiconductor layer, and a gate electrode provided in contact with the gate insulating layer and a channel region of the oxide semiconductor layer is provided in contact with the first insulating layer, and a source region and a drain region of the oxide semiconductor layer are provided in contact with the substrate or the second insulating layer. ,
The first insulating layer is an insulating layer from which oxygen is released by heating, or a method for manufacturing a semiconductor device.

In the above structure, the insulating layer that releases oxygen when heated is made of oxygen-excess silicon oxide (
SiO _X (X>2)). Silicon oxide with excess oxygen (SiO _X (X>2)
) contains more than twice as many oxygen atoms as silicon atoms per unit volume. The number of silicon atoms and the number of oxygen atoms per unit volume are values measured by the Rutherford backscattering method.

In the above structure, silicon oxide, silicon oxynitride, or aluminum oxide may be used for the insulating layer from which oxygen is released by heating.

In the above structure, the substrate or the second insulating layer preferably releases less oxygen than the first insulating layer.

In the above structure, silicon oxide, silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum nitride, or aluminum oxynitride may be used for the second insulating layer.

In the above structure, an insulating layer that releases oxygen by heating is preferably used as the gate insulating layer. Alternatively, it is preferable to use silicon oxide containing more oxygen atoms than twice the number of silicon atoms per unit volume as the gate insulating layer.

The above structure may further include an interlayer insulating layer provided over the gate electrode, and a wiring provided over the interlayer insulating layer and in contact with the oxide semiconductor layer through an opening provided in the interlayer insulating layer. good.

In the above structure, the source region and the drain region are regions in which the resistance of the oxide semiconductor layer is lowered. That is, the source region and the drain region are formed by subjecting part of the oxide semiconductor layer to treatment to reduce resistance. At the same time, a channel region is formed in the oxide semiconductor layer.

In the above structure, the insulating layer from which oxygen is released by heating is preferably formed by a sputtering method. Alternatively, the insulating layer from which oxygen is released by heating is preferably formed by a sputtering method using oxygen or a mixed gas of oxygen and argon.

In the above structure, the oxide semiconductor layer is preferably formed by a sputtering method.

In the above structure, heat treatment is preferably performed at 100° C. to 650° C. after the oxide semiconductor layer is formed.

In the above structure, the source region and the drain region may be formed by performing low-resistance treatment on part of the oxide semiconductor layer using the gate electrode as a mask. In that case, a channel region is formed in a portion of the oxide semiconductor layer that is masked by the gate electrode.

Note that in the above structure, the channel length L of the transistor can be 10 nm or more and 10 μm or less, for example, 0.1 μm to 0.5 μm. Of course, the channel length L is 1
It may be 0 μm or more. Also, the channel width W can be set to 10 μm or more.

According to one embodiment of the present invention, an insulating layer that releases oxygen by heating is provided as an insulating layer in contact with a channel region of an oxide semiconductor layer, and an insulating layer that is in contact with a source region and a drain region of an oxide semiconductor layer releases oxygen from the channel. By providing an insulating layer whose number is smaller than that of the insulating layer in contact with the region, a transistor with small off-state current, small variation in threshold voltage, large on-state current, and stable electrical characteristics can be provided.

Alternatively, one embodiment of the present invention provides a semiconductor device including a transistor with favorable electrical characteristics and high reliability.

1A and 1B are cross-sectional views each illustrating one mode of a semiconductor device; 4A to 4C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device; 4A to 4C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device; 4A to 4C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device; 4A to 4C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device; 1A and 1B are cross-sectional views each illustrating one mode of a semiconductor device; 1A and 1B illustrate one mode of a semiconductor device; 1A and 1B are diagrams each showing an electronic device as a semiconductor device; 1A and 1B are a top view and a cross-sectional view of one embodiment of a semiconductor device;

Embodiments of the present invention will be described in detail below with reference to the drawings. However, those skilled in the art will easily understand that the present invention is not limited to the following description, and that the forms and details thereof can be variously changed. Moreover, the present invention should not be construed as being limited to the description of the embodiments shown below. In describing the configuration of the invention with reference to the drawings, the same reference numerals are commonly used between different drawings. When referring to similar items, the same hatch pattern may be used and no particular reference numerals may be attached.

Note that the ordinal numbers given as first and second are used for convenience and do not indicate the order of steps or the order of stacking. Moreover, in this specification, specific names are not shown as matters for specifying the invention.

(Embodiment 1)
In this embodiment, one mode of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS.

FIG. 1 illustrates a cross-sectional view of a coplanar transistor 155, which is one mode of a top-gate transistor, as an example of a semiconductor device of one embodiment of the present invention.

A transistor 155 illustrated in FIG. 1A includes the insulating layer 103 , the oxide semiconductor layer 106 , the gate insulating layer 112 , and the gate electrode 114 over the substrate 100 . The insulating layer 103 has a first region 101 and a second region 102 . The transistor 155 includes a channel region 126, a source region 122a, and a drain region 122b in the oxide semiconductor layer 106. The channel region 126, source region 122a and drain region 122b are provided in the same layer.

The oxide semiconductor layer 106 is provided in contact with the first region 101 and the second region 102, the channel region 126 of the oxide semiconductor layer 106 is provided in contact with the first region 101, and is provided in contact with the oxide semiconductor. Source region 122a and drain region 122b of layer 106 are second region 1
02. The gate insulating layer 112 is provided in contact with the oxide semiconductor layer 106 , and the gate electrode 114 is provided in contact with the gate insulating layer 112 . gate electrode 11
4, an interlayer insulating layer 124 is provided. The wiring 108a and the wiring 108b are respectively connected to the source region 122a and the drain region 122b with the interlayer insulating layer 124 interposed therebetween.
are electrically connected. The wirings 108a and 108b function as source and drain electrodes. Note that FIG. 1A shows that the gate insulating layer 112 and the gate electrode 114 have the same width; however, the present invention is not limited to this. Fig. 1(B)
3 , the gate insulating layer 113 may be provided over the insulating layer 103 and the oxide semiconductor layer 106 instead of the gate insulating layer 112 . Note that the gate insulating layer 113 may be formed using a method and a material similar to those of the gate insulating film 112, and the gate insulating layer 112 in this specification can be replaced with the gate insulating film 113 as appropriate.

As a material for the first region 101, silicon oxide, silicon oxynitride, aluminum oxide, a mixed material thereof, or the like may be used. The first region 101 is characterized by releasing oxygen upon heating. "Releasing oxygen by heating" means TDS (Thermal D
In esorption Spectroscopy (thermal desorption spectroscopy) analysis, the amount of oxygen released in terms of oxygen atoms is 1 × 10 ¹⁸ atoms / cm ³ or more, preferably 3 ×
It means 10 ²⁰ atoms/cm ³ or more. Alternatively, oxygen-excess silicon oxide (SiO _X (X>2)) may be used as the material of the first region 101 . Oxygen-excess silicon oxide (SiO _x (X>2)) includes more than twice as many oxygen atoms as silicon atoms per unit volume. The number of silicon atoms and the number of oxygen atoms per unit volume are values measured by the Rutherford backscattering method.

As a material for the second region 102, silicon oxide, silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum nitride, or aluminum oxynitride may be used. The second region 102 is characterized by being an insulating layer that releases less oxygen than the first region 101 . Note that the first region 101 and the second region 102 may use materials having the same constituent elements, materials having two or more constituent elements the same, or materials having different constituent elements. When the first region 101 and the second region 102 use a material having the same constituent element or two or more constituent elements having the same constituent element, the material of the second region 102 has a number of oxygen atoms per unit volume. Less material than the first region 101 may be used. For example, the first region 10
Silicon oxide (SiO _x (X>2)) containing more oxygen atoms per unit volume than twice the number of silicon atoms is used as the material of 1 , and the material of the second region 102 is Silicon oxide (SiO _x (X≦2)) having a smaller number of oxygen atoms than the first region 101 may be used. Alternatively, silicon oxynitride having a smaller number of oxygen atoms per unit volume than the first region 101 may be used as the material of the second region 102 . As the material of the second region 102, an organic insulating material that can be formed by a wet method, such as acrylic resin, polyimide, benzocyclobutene resin, polyamide, or epoxy resin, may be used. In addition to the above organic insulating materials, inorganic insulating materials that can be formed by a wet method such as low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphorus glass), and BPSG (phosphor boron glass) are used. good too. Moreover, the second region 102 has a temperature higher than that of the first region 101 (for example, a range of 100° C. to 650° C.).
It is preferable that the diffusion coefficient of oxygen in is low. By doing so, the first region 10
The amount of oxygen released in 1 that diffuses into the second region 102 can be reduced.

Further, the insulating layer 103 having the first region 101 and the second region 102 includes the above material and silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, or any of these materials. You may laminate|stack and use the mixed material of. In the case where the insulating layer 103 is formed to have a stacked-layer structure, the material for the first region 101 and the material for the second region 102 are preferably used for the side in contact with the oxide semiconductor layer 106 . Note that the insulating layer 103 functions as a base layer of the transistor 155 .

As a material used for the oxide semiconductor layer 106, In—Sn—G, which is a quaternary metal oxide, is used.
a-Zn-O-based materials, In-Ga-Zn-O-based materials that are ternary metal oxides, In
-Sn--Zn--O based materials, In--Al--Zn--O based materials, Sn--Ga--Zn--O based materials, Al--Ga--Zn--O based materials, Sn--Al--Zn--O system materials, binary metal oxides such as In--Zn--O-based materials, Sn--Zn--O-based materials, Al--Zn--O-based materials, Zn--Mg--O-based materials, and Sn -Mg-O-based material, In-Mg-O-based material, In-
Ga--O-based materials, In--O-based materials, Sn--O-based materials, Zn--O-based materials, and the like can be used. Further, silicon oxide may be included in the above materials. Here, for example, In--Ga--Zn--O based materials include indium (In), gallium (Ga), zinc (
Zn), and the composition ratio thereof is not particularly limited. In addition, elements other than In, Ga, and Zn may be included.

When an In—Zn—O-based material is used for the oxide semiconductor layer 106, the atomic ratio is In
/Zn=0.5 to 50, preferably In/Zn=1 to 20, more preferably In/Zn=1.5 to 15. By setting the atomic number ratio of Zn within the above range,
The field effect mobility of the transistor can be improved. Here, when the atomic ratio of the compound is In:Zn:O=X:Y:Z, it is preferable to satisfy Z>1.5X+Y.

Alternatively, the oxide semiconductor layer 106 can be formed using a thin film using a material represented by the chemical formula, InMO ₃ (ZnO) _m (m>0). Here, M represents one or more metal elements selected from Ga, Al, Mn and Co. For example, M can be Ga, Ga and A
1, Ga and Mn or Ga and Co and the like can be used.

Since the channel region 126 and the first region 101 are in contact with each other, the interface state density between the first region 101 and the channel region 126 and oxygen vacancies in the channel region 126 can be reduced.
As a result, it is possible to sufficiently suppress trapping of charges and the like that may be generated due to the operation of the semiconductor device at the interface between the first region 101 and the channel region 126 .

In addition, charges may be generated due to oxygen vacancies in channel region 126 . In general, oxygen vacancies in the channel region partially become donors and generate electrons that are carriers. As a result, the threshold voltage of the transistor shifts in the negative direction. channel region 126
Oxygen is sufficiently released from the first region 101, which is an insulating layer in contact with the channel region 126, to the channel region 126, which causes the threshold voltage to shift in the negative direction.
It can make up for the oxygen deficiency inside.

That is, when oxygen vacancies occur in the channel region 126, it becomes difficult to suppress charge trapping at the interface between the channel region 126 and the first region 101, which is an insulating layer in contact with the channel region 126. By providing an insulating layer that releases oxygen by heating as the region 101, the interface state density between the channel region 126 and the first region 101 and the channel region 1
26 can be reduced, and the effect of charge trapping at the interface between the channel region 126 and the first region 101 can be reduced.

In addition, the source region 122a and the drain region 122b and the region 10 having the first oxygen release amount
The contact with less than one second region 102 prevents oxygen from being supplied to the source region 122a and the drain region 122b. This is because some of the oxygen vacancies in the oxide semiconductor layer serve as a source of electrons that are carriers. In other words, it is based on the technical idea that the supply of oxygen reduces oxygen vacancies and prevents the source region 122a and the drain region 122b from increasing in resistance. For example, as the second region 102 in contact with the source region 122a and the drain region 122b, an insulating layer that releases less than 1×10 ¹⁸ atoms/cm ³ of oxygen by TDS analysis can be used.

Due to the effect of suppressing charge trapping at the interface of the channel region 126 of the oxide semiconductor layer and suppressing the increase in resistance of the source region 122a and the drain region 122b, if the source region 122a and the drain region 122b have a high resistance By doing so, the source region 122
It is possible to suppress the problem that the on-state current of the transistor 155 is decreased due to the decrease in the current flowing through the a and the drain region 122b. In addition, problems such as an increase in off-state current and a change in threshold voltage of the transistor 155 including an oxide semiconductor can be suppressed. In addition, reliability of the semiconductor device can be improved.

The gate insulating layer 112 may have the same structure (for example, the same material) as the first region 101 . That is, the gate insulating layer 112 may be an insulating layer that releases oxygen by heating. Alternatively, a material with a high dielectric constant, such as hafnium oxide or aluminum oxide, may be used in consideration of functioning as a gate insulating layer of a transistor. In addition, considering the gate breakdown voltage and the state of the interface with the oxide semiconductor, a material having a high dielectric constant such as hafnium oxide or aluminum oxide may be laminated on silicon oxide, silicon oxynitride, or silicon nitride.

The gate electrode 114 is made of molybdenum, titanium, tantalum, tungsten, aluminum,
It can be formed using metal materials such as copper, neodymium, and scandium, nitrides thereof, or alloy materials containing these as main components. Note that the gate electrode 114 may have a single-layer structure or a stacked-layer structure.

An interlayer insulating layer 124 may be further provided over the transistor 155 . The interlayer insulating layer 124 may have the same configuration (for example, the same material) as the second region 102 . Further, openings may be formed in the interlayer insulating layer 124 to electrically connect the wirings 108a and 108b.

Examples of conductive layers used for the wirings 108a and 108b include Al, Cr, Cu,
A metal layer containing an element selected from Ta, Ti, Mo, and W, or a metal nitride layer (titanium nitride layer, molybdenum nitride layer, tungsten nitride layer) containing the above elements as components can be used. In addition, Ti, M is added to one or both of the lower side and the upper side of the metal layer such as Al and Cu.
A structure in which refractory metal layers such as o and W or metal nitride layers thereof (titanium nitride layer, molybdenum nitride layer, tungsten nitride layer) are laminated may be used.

Further, the transistor 155 may have a second gate electrode below the oxide semiconductor layer 106 . Note that the oxide semiconductor layer 106 is preferably processed into an island shape;
It does not have to be processed into an island shape.

An example of a manufacturing process of the transistor 155 illustrated in FIG. 1A is described below with reference to FIGS.

First, using FIGS. 2(A) to 2(D) and FIGS. 3(A) to 3(D), FIG.
An example of a manufacturing process of the transistor 155 illustrated in FIG.

A first insulating layer 131 is formed over the substrate 100 (see FIG. 2A), and the first insulating layer 13 is formed.
1 is processed by a method such as photolithography to form an island-shaped first region 101 (see FIG. 2B). As a photomask used for forming the first region 101, the same photomask as used for forming the gate electrode can be used. The first region 101 is characterized by releasing oxygen upon heating. Alternatively, oxygen-excess silicon oxide (SiO _X (X>2)) may be used as the material of the first region 101 .

There is no particular limitation on the material of the substrate 100, but at least the substrate 100 must have heat resistance enough to withstand heat treatment performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used as the substrate 100 . Further, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be used, and semiconductor elements are provided over any of these substrates. may be used as the substrate 100.

Alternatively, a flexible substrate may be used as the substrate 100 . In the case of providing a transistor over a flexible substrate, the transistor may be formed directly over the flexible substrate, or after the transistor is formed over another substrate, this substrate is peeled off and a flexible substrate which is the substrate 100 is formed. You can transpose. Note that a separation layer is preferably formed between the other substrate and the transistor in order to separate the transistor and transfer it to a flexible substrate.

As a method for forming the first insulating layer 131 to be the first region 101, for example, a plasma CVD method, a sputtering method, or the like can be used. A sputtering method is preferably used for forming the insulating layer which releases oxygen by heating.

When oxygen or a mixed gas of oxygen and a rare gas (such as argon) is used as a deposition gas to form an insulating layer that releases oxygen by heating by a sputtering method, the mixture ratio of oxygen and the rare gas is is preferably formed with an increased proportion of oxygen. For example, the concentration of oxygen in the total gas should be 6% or more and less than 100%.

Silicon oxide, silicon oxynitride, aluminum oxide, a mixed material thereof, or the like may be used as a material for the first insulating layer 131 which serves as the first region 101 .

For example, for the first insulating layer 131, quartz (preferably synthetic quartz) is used as a target, the substrate temperature is 30° C. to 450° C. (preferably 70° C. to 200° C.), and oxygen or oxygen and oxygen are used as a deposition gas. Argon was used, and the O ₂ /(O ₂ +Ar) ratio in the deposition gas was 1.
% to 100% (preferably 6% to 100%), silicon oxide is formed by an RF sputtering method.

The thicknesses of the first insulating layer 131 and the first region 101 are preferably 50 nm or more, more preferably 200 nm or more. By forming the first insulating layer 131 and the first region 101 thick, the amount of oxygen released from the first region 101 can be increased.

Next, a second insulating layer 132 is formed on the substrate 100 and the first region 101 (FIG. 2 (
C) See. ). After that, the second insulating layer 132 is processed until the surface of the first region 101 is exposed to form the insulating layer 103 having the second region 102 in contact with the first region 101 (
See FIG. 2(D). ). The second region 102 is characterized by being an insulating layer that releases less oxygen than the first region 101 . Note that when processing the second insulating layer 132, the surface of the first region 101 may be processed and part of the first region 101 may be removed at the same time.

As a method for forming the second insulating layer 132, for example, a plasma CVD method, a sputtering method, or the like can be used.

As a material for the second insulating layer 132, silicon oxide, silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum nitride, or aluminum oxynitride may be used.

For example, silicon nitride is formed as the second insulating layer 132 by a plasma CVD method. Alternatively, silicon oxide may be formed as the second insulating layer 132 by a plasma CVD method.

It is preferable that the surface of the first region 101 and the surface of the second region 102 are aligned after the above steps. For example, until the surface of the first region 101 is exposed, the second insulating layer 13 is
2 is subjected to a polishing treatment such as CMP (chemical mechanical polishing) or an etching treatment, so that the first
has a second region 102 in contact with the region 101 of, and the surface of the first region 101 and the second
Insulating layer 103 having an even surface in region 102 can be formed. By aligning the surface of the first region 101 and the surface of the second region 102, discontinuity of the oxide semiconductor layer formed thereover can be prevented. This effect is remarkable when the oxide semiconductor layer is thin. By preventing disconnection of the oxide semiconductor layer, disconnection of the source region and the drain region can be prevented, and a decrease in on-current can be suppressed. Further, disconnection of the gate insulating layer formed over the oxide semiconductor layer can be prevented. By preventing discontinuity of the gate insulating layer, an increase in leakage current and a decrease in breakdown voltage can be suppressed.

Note that the film thickness of the second region 102 , that is, the film thickness of the insulating layer 103 is the same as the film thicknesses of the first insulating layer 131 and the first region 101 . Specifically, the film thickness of the second region 102, that is, the film thickness of the insulating layer 103 is preferably 50 nm or more, more preferably 200 nm or more. However, the thickness of the first insulating layer 131 may become thinner than the thickness at the time of formation by performing polishing treatment or etching treatment.

Further, the insulating layer 103 having the first region 101 and the second region 102 includes the above material and silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, or any of these materials. You may laminate|stack and use the mixed material of. In the case where the insulating layer 103 is formed to have a stacked-layer structure, the material for the first region 101 and the material for the second region 102 are preferably used for the side in contact with the oxide semiconductor layer 106 . Note that the insulating layer 103 functions as a base layer of the transistor 155 .

Although an example in which the second region 102 is formed after forming the first region 101 is shown here, the order of forming the first region 101 and the second region 102 is reversed, and the second region 102 is formed. The first region 101 may be formed after forming the . In that case, optionally the second region 1
02, a first insulating layer 131 is formed on the entire surface, and the first insulating layer 131 is polished or etched until the surface of the second region 102 is exposed, whereby the first region 1 is formed.
An insulating layer 103 can be formed having a second region 102 contacting the 01.

Next, an oxide semiconductor layer is formed over the insulating layer 103 and processed to form an island-shaped oxide semiconductor layer 106 (see FIG. 3A). The oxide semiconductor layer 106 is
It is formed in contact with the first region 101 and the second region 102 .

The oxide semiconductor layer 106 can be formed using, for example, a sputtering method, a vacuum evaporation method, a pulse laser deposition method, a CVD method, or the like. Further, the thickness of the oxide semiconductor layer 106 is preferably 3 nm or more and 50 nm or less. This is because if the oxide semiconductor layer 106 is too thick (for example, the thickness is 100 nm or more), the influence of the short-channel effect is increased, and a small-sized transistor may be normally on. Here, "normally on" means a state in which a channel exists even if no voltage is applied to the gate electrode and current flows through the transistor.

In this embodiment, the oxide semiconductor layer 106 is formed by a sputtering method using an In--Ga--Zn--O-based oxide target.

As an In—Ga—Zn—O-based oxide target, for example, In ₂
An oxide target of O ₃ :Ga ₂ O ₃ :ZnO=1:1:1 [molar ratio] can be used. Note that the material and composition of the target need not be limited to those described above. For example, an oxide target having a composition ratio of In ₂ O ₃ :Ga ₂ O ₃ :ZnO=1:1:2 [molar ratio] can also be used.

The relative density of the oxide target is 90% to 100%, preferably 95% to 10%.
0% or less. This is because a dense oxide semiconductor layer can be formed by using a metal oxide target with a high relative density.

The film formation atmosphere may be a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen. In addition, hydrogen, water, hydroxyl group,
In order to prevent hydrides and the like from being mixed, it is preferable to use an atmosphere using a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, and hydrides are sufficiently removed.

For example, the oxide semiconductor layer 106 can be formed as follows.

As an example of film formation conditions, the distance between the substrate and the target is 60 mm, and the pressure is 0.4 Pa.
, a direct current (DC) power supply of 0.5 kW, and a film forming atmosphere of argon and oxygen mixed atmosphere (oxygen flow rate ratio of 33%). Note that a pulsed DC sputtering method is preferable because powdery substances (also referred to as particles or dust) generated during film formation can be reduced and the thickness distribution can be uniform.

At this time, by setting the substrate temperature to 100° C. to 450° C., preferably 150° C. to 250° C., oxygen is released from the first region 101 and the portion of the oxide semiconductor layer 106 which is in contact with the first region 101 is released. Oxygen vacancies can be reduced in (the portion to be the channel region 126), and the interface state density between the oxide semiconductor layer 106 and the first region 101 can be reduced.

A portion of the oxide semiconductor layer 106 not in contact with the first region 101 (the source region 122 a
and the drain region 122b) is in contact with the second region 102 that releases less oxygen than the first region 101, whereby the resistance of the oxide semiconductor layer 106 in this portion can be suppressed from increasing. .

Note that, before the oxide semiconductor layer 106 is formed by a sputtering method, reverse sputtering may be performed by introducing argon gas to generate plasma to remove deposits on the formation surface (for example, the surface of the insulating layer 103). good. Here, the reverse sputtering refers to a method of modifying the surface by bombarding the surface to be treated with ions instead of bombarding the sputter target with ions in normal sputtering. As a method for bombarding the surface to be treated with ions, there is a method of applying a high-frequency voltage to the surface to be treated in a rare gas atmosphere to generate plasma in the vicinity of the object to be treated. Note that an atmosphere of nitrogen, oxygen, or the like may be used instead of the rare gas atmosphere.

The oxide semiconductor layer 106 can be processed by forming a mask having a desired shape over the oxide semiconductor layer and then etching the oxide semiconductor layer. The mask described above can be formed using a method such as photolithography. Alternatively, the mask may be formed using a method such as an inkjet method.

Note that the etching of the oxide semiconductor layer may be either dry etching or wet etching. Of course, these may be used in combination.

After that, heat treatment (first heat treatment) is preferably performed on the oxide semiconductor layer 106 . Excess hydrogen (including water and hydroxyl groups) in the oxide semiconductor layer 106 can be removed by this first heat treatment. The temperature of the first heat treatment is 100° C. or higher and 650° C. or lower or lower than the strain point of the substrate, preferably 250° C. or higher and 600° C. or lower. The atmosphere of the first heat treatment is an oxidizing gas atmosphere or an inert gas atmosphere.

Note that the inert gas preferably contains nitrogen or a rare gas (such as helium, neon, or argon) as a main component and does not contain water, hydrogen, or the like. For example, the purity of nitrogen and rare gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more,
It is preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). An inert gas atmosphere is an atmosphere containing an inert gas as a main component and containing less than 10 ppm of a reactive gas.

The oxidizing gas is oxygen, ozone, nitrogen dioxide, or the like, and preferably does not contain water, hydrogen, or the like. For example, the purity of oxygen, ozone, and nitrogen dioxide introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm below). For the oxidizing gas atmosphere, an oxidizing gas may be mixed with an inert gas, and at least 10% of the oxidizing gas may be used.
ppm or higher.

Oxygen is released from the first region 101 by this first heat treatment, and the first region 101
and the portion of the oxide semiconductor layer 106 that is in contact with the first region 101 (the portion that will be the channel region 126), and the oxide semiconductor in the portion that is in contact with the first region 101 can be reduced. Oxygen vacancies in layer 106 can be reduced. By reducing the interface state density, the threshold voltage fluctuation after the BT test can be reduced. Further, it is generally known that part of the oxygen vacancies in the oxide semiconductor layer serve as donors and generate electrons, which are carriers. When electrons are generated in the oxide semiconductor layer 106, the threshold voltage of the transistor 155 shifts in the negative direction and the transistor 155 tends to be normally on. oxide semiconductor layer 10
By filling the oxygen vacancies in 6, the amount of shift of the threshold voltage in the negative direction can be reduced.

A portion of the oxide semiconductor layer 106 not in contact with the first region 101 (the source region 122 a
and the drain region 122b) is in contact with the second region 102 that releases less oxygen than the first region 101, whereby the resistance of the oxide semiconductor layer 106 in this portion can be suppressed from increasing. .

The heat treatment can be performed, for example, by introducing the object to be treated into an electric furnace using a resistance heating element or the like, and performing the conditions at 350° C. for 1 hour in a nitrogen atmosphere. During this time, the oxide semiconductor layer is not exposed to the air so that water and hydrogen are not mixed.

The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats an object to be treated by heat conduction or heat radiation from a medium such as heated gas may be used. For example, GRTA (Gas Rap
id Thermal Anneal) device, LRTA (Lamp Rapid The
RTA (Rapid Thermal Anneal) equipment such as
l) the device can be used; An LRTA apparatus is an apparatus that heats an object by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, and high pressure mercury lamps. The GRTA apparatus is an apparatus that performs heat treatment using high-temperature gas. As the gas, a rare gas such as argon or an inert gas such as nitrogen that does not react with the object to be processed by heat treatment is used.

For example, as the first heat treatment, a GRTA treatment may be performed in which an object to be processed is placed in a heated inert gas atmosphere, heated for several minutes, and then removed from the inert gas atmosphere. The use of the GRTA treatment enables high-temperature heat treatment in a short period of time. In addition, it can be applied even under temperature conditions exceeding the heat resistance temperature of the object to be processed. Note that the inert gas atmosphere may be switched to an atmosphere containing an oxidizing gas during the treatment. In an atmosphere containing an oxidizing gas, the first
This is because the heat treatment can fill oxygen vacancies in the oxide semiconductor layer 106 and can reduce the defect level in the energy gap caused by the oxygen vacancies.

By the way, since the heat treatment described above (the first heat treatment) has the effect of removing hydrogen, water, and the like, the heat treatment can also be called a dehydration treatment, a dehydrogenation treatment, or the like. In addition, since there is an effect of supplying oxygen from an insulating layer, a heat treatment atmosphere, or the like, this treatment can also be referred to as oxygenation treatment. The dehydration treatment, dehydrogenation treatment, and oxygenation treatment can be performed, for example, after the oxide semiconductor layer is processed into an island shape. Moreover, such dehydration treatment, dehydrogenation treatment, and oxygenation treatment may be performed not only once but also multiple times.

Note that although the structure in which the first heat treatment is performed after the oxide semiconductor layer 106 is processed into an island shape is described here, the present invention is not limited thereto, and the oxide semiconductor layer 106 is processed after the first heat treatment. may be processed.

Next, an insulating layer is formed in contact with the oxide semiconductor layer 106, a conductive layer is formed in contact with the insulating layer, and the insulating layer and the conductive layer are processed into similar patterns by photolithography to form the gate insulating layer 112 and the conductive layer. A gate electrode 114 is formed (see FIG. 3B). That is, the gate electrode 1
14 and the gate insulating layer 112 can be processed using the same mask. or,
The gate electrode 114 is processed, and then the gate insulating layer 11 is formed using the gate electrode 114 as a mask.
2 can be processed.

The gate insulating layer 112 may have the same structure (for example, the same material) as the first region 101 . Alternatively, a material with a high dielectric constant, such as hafnium oxide or aluminum oxide, may be used in consideration of functioning as a gate insulating layer of a transistor. In addition, considering the gate breakdown voltage and the state of the interface with the oxide semiconductor, a material having a high dielectric constant such as hafnium oxide or aluminum oxide may be laminated on silicon oxide, silicon oxynitride, or silicon nitride.
The total thickness of the gate insulating layers 112 is preferably 1 nm to 300 nm, more preferably 5 nm to 50 nm. The thicker the gate insulating layer, the more pronounced the short channel effect, and the more the threshold voltage tends to shift to the negative side. In addition, the gate insulating layer is 5n
It is known that leakage due to tunnel current increases when the distance is m or less.

Second heat treatment is preferably performed after the gate insulating layer 112 is formed. The temperature of the second heat treatment is 100° C. or higher and 650° C. or lower or lower than the strain point of the substrate, preferably 250° C. or higher6.
00° C. or less or less than the strain point of the substrate.

The second heat treatment may be performed in an oxidizing gas atmosphere or an inert gas atmosphere, but the atmosphere preferably does not contain water, hydrogen, or the like. Further, the purity of the gas introduced into the heat treatment apparatus is preferably 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). .

In the second heat treatment, heating is performed while the oxide semiconductor layer 106 is in contact with the first region 101 and the gate insulating layer 112 . Therefore, oxygen, which is one of the main components of the oxide semiconductor, can be supplied from the first region 101 containing oxygen and the gate insulating layer 112 to the oxide semiconductor layer 106 . Thereby, oxygen vacancies in the oxide semiconductor layer 106,
The interface state density between the first region 101 and the oxide semiconductor layer 106 and the interface state density between the oxide semiconductor layer and the gate insulating layer 112 can be reduced. At the same time, gate insulating layer 11
2 can also be reduced.

Note that the timing of the second heat treatment is not particularly limited as long as it is after the gate insulating layer 112 is formed. In addition, the second heat treatment may be performed multiple times.

The gate electrode 114 is made of molybdenum, titanium, tantalum, tungsten, aluminum,
It can be formed using metal materials such as copper, neodymium, and scandium, nitrides thereof, or alloy materials containing these as main components. Note that the gate electrode 114 may have a single-layer structure or a stacked-layer structure.

Next, the gate electrode 114 is used as a mask to lower the resistance of the oxide semiconductor layer 106 to form the source region 122a and the drain region 122b. Gate electrode 114 not reduced in resistance
The lower region becomes the channel region 126 (see FIG. 3C). As a method of low resistance,
Examples include argon plasma treatment, hydrogen plasma treatment, ammonia plasma treatment, and the like. At this time, the width of the gate electrode 114 determines the channel length L of the transistor. In this way, by patterning using the gate electrode 114 as a mask,
Since the gate electrode 114 does not overlap with the source region 122a and the drain region 122b, and parasitic capacitance does not occur in this region, the transistor operation can be speeded up.

Next, an interlayer insulating layer 124 is formed, and openings are provided in portions of the interlayer insulating layer 124 that overlap with the source region 122a and the drain region 122b. Then, a conductive layer is formed and processed to form the wiring 108a and the wiring 108b (see FIG. 3D).

Examples of conductive layers used for the wirings 108a and 108b include Al, Cr, Cu,
A metal layer containing an element selected from Ta, Ti, Mo, and W, or a metal nitride layer (titanium nitride layer, molybdenum nitride layer, tungsten nitride layer) containing the above elements as components can be used. In addition, Ti, M is added to one or both of the lower side and the upper side of the metal layer such as Al and Cu.
A structure in which refractory metal layers such as o and W or metal nitride layers thereof (titanium nitride layer, molybdenum nitride layer, tungsten nitride layer) are laminated may be used.

Alternatively, the conductive layer used for the wirings 108a and 108b may be formed using a conductive metal oxide. Examples of conductive metal oxides include indium oxide (In ₂ O ₃ etc.), tin oxide (S
_{nO2 ,} etc.) _, zinc oxide ₍ ZnO, etc.), indium tin oxide ₍ In2O3--SnO2, etc., abbreviated as ITO), indium zinc oxide ₍ In2O3--ZnO, etc.), or metal oxides thereof A material containing silicon oxide can be used.

The conductive layer can be processed by etching using a resist mask. UV light, KrF laser light, ArF laser light, and UV light are used for exposure when forming a resist mask used for the etching.
A laser beam or the like may be used.

Through the above steps, the transistor 155 is manufactured.

Next, an example of a manufacturing process of the insulating layer 103 is described with reference to FIGS. 2A to 2C, the first region 101 is formed over the substrate 100, and the second insulating layer 132 is formed over the substrate 100 and the first region 101. (See FIG. 4(A).). Next, a third insulating layer 133 is formed on the second insulating layer 132 (
See FIG. 4(B). ). A planarization insulating layer can be used for the third insulating layer 133 . For example, the material of the third insulating layer 133 can be an organic insulating material that can be formed by a wet method, such as acrylic resin, polyimide, benzocyclobutene resin, polyamide, or epoxy resin. In addition to the above organic insulating materials, inorganic insulating materials that can be formed by a wet method, such as low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphorus glass), and BPSG (phosphor boron glass), can be used. can be done.

The method for forming the third insulating layer 133 is spin coating, dipping, spray coating, droplet discharge (inkjet, screen printing, offset printing, etc.), roll coating, curtain coating, knife coating, etc., depending on the material. A coating or the like can be used.

Next, the third insulating layer 133 and the second insulating layer 132 are etched. The etchant used for the etching treatment has an etching selection ratio of 1:1 or its vicinity between the third insulating layer 133 and the second insulating layer 132 . As a result, the third insulating layer 133 and the second
The etching rate of the insulating layer 132 can be approximately the same (see FIG. 4C).
). Note that the etching of the third insulating layer 133 and the second insulating layer 132 may be dry etching or wet etching.

Then, by etching the third insulating layer 133 and the second insulating layer 132 until the surface of the first region 101 is exposed, the second region 102 is in contact with the first region 101, and , an insulating layer 103 in which the surface of the first region 101 and the surface of the second region 102 are aligned can be formed (see FIG. 4D). The surface of the first region 101 and the second region 10
By aligning the surfaces of 2, the oxide semiconductor layer formed thereon can be prevented from being disconnected. This effect is remarkable when the thickness of the oxide semiconductor layer 106 is thin. By preventing disconnection of the oxide semiconductor layer 106, disconnection of the source region 122a and the drain region 122b can be prevented, and a decrease in on-current can be suppressed. Further, disconnection of the gate insulating layer 112 formed over the oxide semiconductor layer 106 can be prevented. By preventing disconnection of the gate insulating layer 112, an increase in leakage current and a decrease in breakdown voltage can be suppressed.

Although an example in which the second region 102 is formed after forming the first region 101 is shown here, the order of forming the first region 101 and the second region 102 is reversed, and the second region 102 is formed. The first region 101 may be formed after forming the . In that case, optionally the second region 1
02, a first insulating layer 131 is formed on the entire surface, and a third insulating layer 131 is formed on the first insulating layer 131.
of the insulating layer 133 is formed. Then, by etching the third insulating layer 133 and the first insulating layer 131 until the surface of the second region 102 is exposed, the second region 102 is in contact with the first region 101, and , the insulating layer 103 in which the surface of the first region 101 and the surface of the second region 102 are aligned can be formed. Also in this case, the etching of the third insulating layer 133 and the first insulating layer 131 may be either dry etching or wet etching.

Further, although an example of forming the second insulating layer 132 and the third insulating layer 133 is shown here,
The second insulating layer 132 having a flat surface may be formed by forming the second insulating layer 132 using the same material and the same method as those of the third insulating layer 133 . That is, as shown in FIG. 5(A),
A second insulating layer 132 having a flat surface is formed over the substrate 100 and the first region 101 by using the same material and the same method as those of the third insulating layer 133 . good too. By etching the second insulating layer 132 having a flat surface until the surface of the first region 101 is exposed, the second region 102 can be formed as shown in FIG. 5B.
As a result, the insulating layer 103 in which the surface of the first region 101 and the surface of the second region 102 are aligned can be formed. Also in this case, the material used for the second region 102 is characterized by being an insulating layer that releases less oxygen than the first region 101 . According to the manufacturing method shown in FIGS. 5A and 5B, the number of film formations for forming the insulating layer 103 is reduced and processing is facilitated as compared with the manufacturing method shown in FIGS.

Subsequent steps can be the same as those in FIGS.

According to this embodiment, the first region 101 that releases oxygen by heating is provided as an insulating layer in contact with the channel region 126 of the oxide semiconductor layer 106, and the insulating layer is in contact with the source region 122a and the drain region 122b of the oxide semiconductor layer 106. Region 10 with first oxygen release rate as layer
By providing less than 1 second region 102, a transistor with stable electrical characteristics such as small off-state current, small variation in threshold voltage, and large on-state current can be provided.

Alternatively, according to this embodiment, a semiconductor device including a transistor with favorable electrical characteristics and high reliability is provided.

The structures, methods, and the like described in this embodiment can be combined as appropriate with the structures, methods, and the like described in other embodiments.

(Embodiment 2)
In this embodiment, one mode of a semiconductor device will be described with reference to FIGS. Figure 6 shows Figure 1 (
A) shows a cross-sectional structure of a transistor 156 having a structure different from that of the transistor 155 shown in FIG.
A transistor 156 in FIG. 6 has a structure in which the second region 102 is not provided in the transistor 155 in FIG.

A transistor 156 illustrated in FIG. 6 includes a first insulating layer 104 , an oxide semiconductor layer 106 , a gate insulating layer 112 , and a gate electrode 114 over the substrate 100 . The transistor 156 includes a channel region 126, a source region 122a, and a drain region 12 in the oxide semiconductor layer 106.
2b. Channel region 126, source region 122a and drain region 122b are
provided in the same layer.

A second insulating layer 105 may be provided under the transistor 156 . The second insulating layer 105 functions as a base layer for the transistor 156 .

A first insulating layer 104 is selectively provided over the substrate 100 or the second insulating layer 105 provided over the substrate 100 . An oxide semiconductor layer 106 is provided over the first insulating layer 104 . The oxide semiconductor layer 106 is provided in contact with the substrate 100 or the second insulating layer 105 provided over the substrate 100 and the first insulating layer 104, and the channel region 126 of the oxide semiconductor layer 106 is The source region 122a and the drain region 122b of the oxide semiconductor layer 106 which are provided in contact with the first insulating layer 104 are the substrate 100 or the substrate 100
It is provided in contact with the second insulating layer 105 provided thereon.

The gate insulating layer 112 is provided in contact with the oxide semiconductor layer 106 , and the gate electrode 114 is provided in contact with the gate insulating layer 112 . An interlayer insulating layer 124 is provided on the gate electrode 114 . A wiring 108a and a wiring 108b are electrically connected to the source region 122a and the drain region 122b through an interlayer insulating layer 124, respectively.
The wirings 108a and 108b function as source and drain electrodes.

The material of the first insulating layer 104 can have a structure similar to that of the material of the first region 101 described in Embodiment 1. FIG. That is, silicon oxide, silicon oxynitride, aluminum oxide, a mixed material thereof, or the like may be used as the material of the first insulating layer 104 . The first insulating layer 104 is characterized by releasing oxygen by heating. "Releasing oxygen by heating"
means that the amount of oxygen released in terms of oxygen atoms is 1×10 ¹⁸ atoms in TDS (Thermal Desorption Spectrocopy) analysis.
/cm ³ or more, preferably 3×10 ²⁰ atoms/cm ³ or more. Alternatively, the material of the first insulating layer 104 is oxygen-excess silicon oxide (SiO _X (X>2)).
may be used. Oxygen-excess silicon oxide (SiO _x (X>2)) includes more than twice as many oxygen atoms as silicon atoms per unit volume. The number of silicon atoms and the number of oxygen atoms per unit volume are values measured by the Rutherford backscattering method.

In the case where the second insulating layer 105 is provided, the material of the second insulating layer 105 can be similar to the material of the second region 102 described in Embodiment Mode 1. FIG. That is, the second insulating layer 1
05 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride,
Aluminum oxide, aluminum nitride, aluminum oxynitride, or the like may be used.
The second insulating layer 105 is characterized by being an insulating layer that releases less oxygen than the first insulating layer 104 .

In the first insulating layer 104 and/or the second insulating layer 105, the above material and silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, or any of these materials are used. A mixed material or the like may be laminated and used. When the first insulating layer 104 and/or the second insulating layer 105 are formed to have a stacked-layer structure, the side in contact with the oxide semiconductor layer 106 is the first insulating layer 104 or the second insulating layer 105 described above.
It should be used as a material for

Since the channel region 126 and the first insulating layer 104 are in contact with each other, the interface state density between the first insulating layer 104 and the channel region 126 and oxygen vacancies in the channel region 126 can be reduced. By reducing the interface state density, it is possible to reduce the negative shift of the threshold voltage after the BT test. Alternatively, since generation of carriers can be suppressed, a normally-off characteristic can be obtained.

In addition, since the source region 122a and the drain region 122b are in contact with the substrate 100 or the second insulating layer 105, an increase in resistance of the source region 122a and the drain region 122b is suppressed, and electrical characteristics are favorable and reliability is high. A semiconductor device including the transistor 156 can be provided.

There is no particular limitation on the material of the substrate 100, but at least the substrate 100 must have heat resistance enough to withstand heat treatment performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used as the substrate 100 . Further, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be used, and semiconductor elements are provided over any of these substrates. may be used as the substrate 100.

Alternatively, a flexible substrate may be used as the substrate 100 . In the case of providing a transistor over a flexible substrate, the transistor may be formed directly over the flexible substrate, or after the transistor is formed over another substrate, this substrate is peeled off and a flexible substrate which is the substrate 100 is formed. You can transpose. Note that a separation layer is preferably formed between the other substrate and the transistor in order to separate the transistor and transfer it to a flexible substrate.

Note that when the second insulating layer 105 is not provided, it is preferable to use a substrate made of a material that releases less oxygen than the first insulating layer 104 as the substrate 100 . For example, when the second insulating layer 105 is not provided, it is preferable to use a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, an SOI substrate, or the like as the substrate 100 .

A manufacturing process of the transistor 156 is described. A second insulating layer 105 is formed on the entire surface of the substrate 100 and a first insulating layer 104 is selectively formed on the second insulating layer 105 . first
The insulating layer 104 is characterized in that oxygen is released by heating. Alternatively, the first insulating layer 1
04 may be oxygen-excess silicon oxide (SiO _x (X>2)). Note that in order to improve coverage with the oxide semiconductor layer 106 to be formed later, the first insulating layer 10
The ends of 4 are preferably formed so as to have a slope. Further, the same photomask as used for forming the gate electrode 114 can be used as the photomask for forming the first insulating layer 104 .

The subsequent manufacturing steps can be the same as the manufacturing steps described in Embodiment Mode 1. FIG.

The transistor 156 described in this embodiment can omit the step of aligning the surfaces of the insulating layers, and the transistor 156 can be provided with high throughput using a simple method at low cost.

According to this embodiment, the first insulating layer 104 that releases oxygen by heating is provided as an insulating layer in contact with the channel region 126 of the oxide semiconductor layer 106 and is in contact with the source region 122 a and the drain region 122 b of the oxide semiconductor layer 106 . By providing the substrate 100 or the second insulating layer 105 that releases less oxygen than the first insulating layer 104 as the substrate or the insulating layer, the off-state current is small, the variation in the threshold voltage is small, and the on-state current is large. A transistor having stable electrical characteristics is provided.

Alternatively, according to this embodiment, a semiconductor device including a transistor with favorable electrical characteristics and high reliability is provided.

The structures, methods, and the like described in this embodiment can be combined as appropriate with the structures, methods, and the like described in other embodiments.

(Embodiment 3)
In this embodiment, one mode of a semiconductor device will be described with reference to FIGS. In FIG. 9(A),
1 shows a top view of a transistor; FIG. FIG. 9B shows a cross-sectional structure corresponding to the dashed-dotted line AB shown in FIG. 9A.

The transistor illustrated in FIG. 9B includes the insulating layer 103 and the oxide semiconductor layer 1 over the substrate 100 .
36, gate insulating layer 112, gate electrode 114, sidewall insulating layer 130, source electrode 116a
, including the drain electrode 116b. The insulating layer 103 is formed between the first region 101 and the second region 102
have The transistor illustrated in FIG. 9B has a channel region 1 in the oxide semiconductor layer 136 .
26, a source region 122a, a drain region 122b, an offset region 123a and an offset region 123b. Channel region 126, source region 122a, drain region 122b, offset region 123a and offset region 123b are provided in the same layer.

The offset region 123a and the offset region 123b have lower resistance than the channel region 126 and higher resistance than the source region 122a and the drain region 122b.
The width of the offset region 123a or the offset region 123b is also called Loff, and is shown in FIG.
A) shows the width. The short-channel effect of a transistor is reduced by having Loff.
A structure (also referred to as a Loff structure) shown in FIG. 9B is preferable. Further, with the Loff structure, deterioration of the transistor such as deterioration of hot carriers can be reduced.

The oxide semiconductor layer 136 is provided in contact with the first region 101 and the second region 102, the channel region 126 of the oxide semiconductor layer 136 is provided in contact with the first region 101, and is provided in contact with the oxide semiconductor. Source region 122 a , drain region 122 b , offset region 123 a and offset region 123 b of layer 136 are provided in contact with second region 102 . Offset region 123a and offset region 123b are located closer to channel region 126 than source region 122a and drain region 122b.

Gate insulating layer 112 is provided in contact with channel region 126 , offset region 123 a and offset region 123 b , and sidewall insulating layer 130 is provided around gate electrode 114 . A gate electrode 114 and a sidewall insulating layer 130 are provided in contact with the gate insulating layer 112 . An interlayer insulating layer 124 is provided on gate electrode 114 and sidewall insulating layer 130 . A source electrode 116a and a drain electrode 116b are provided in contact with the source region 122a and the drain region 122b, respectively. It is connected to the.

As the conductive layer used for the source electrode 116a and the drain electrode 116b, for example, A
A metal layer containing an element selected from l, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride layer (titanium nitride layer, molybdenum nitride layer, tungsten nitride layer) containing the above elements as a component
etc. can be used. In addition, a high-melting-point metal layer such as Ti, Mo, W or a metal nitride layer thereof (titanium nitride layer, molybdenum nitride layer, tungsten nitride layer) is provided on one or both of the lower side and the upper side of the metal layer such as Al and Cu. may be used.

In addition, the offset regions 123a and 123b are in contact with the second region 102 that releases less oxygen than the first region 101, so that oxygen is not supplied to the offset regions 123a and 123b. .

The offset region 123a and the offset region 123b are distinguished from the channel region 126 by the region in contact with the insulating layer 103, not by the region with a reduced resistance. That is, the offset region 123a and the offset region 123b are regions of the oxide semiconductor layer 136 that are not in contact with the insulating layer that releases oxygen by heating.

Since the transistor described in this embodiment has an offset region, a transistor with better electric characteristics and high reliability can be provided.

However, it is not always necessary to provide the offset area. For example, in FIG.
The transistor shown in C) has a structure different from that in FIG. 9B in that an offset region is not provided.

Alternatively, according to this embodiment, a semiconductor device including a transistor with favorable electrical characteristics and high reliability is provided.

The structures, methods, and the like described in this embodiment can be combined as appropriate with the structures, methods, and the like described in other embodiments.

(Embodiment 4)
A semiconductor device having a display function (also referred to as a display device) can be manufactured using the transistors described in Embodiments 1, 2, and 3. FIG. Further, part or all of a driver circuit including a transistor can be formed over the same substrate as a pixel portion, so that a system-on-panel can be formed.

In FIG. 7A, a sealant 205 is provided so as to surround a pixel portion 202 provided over a first substrate 201 and sealed with a second substrate 206 . 7A, a single crystal semiconductor layer or a polycrystalline semiconductor layer is formed over a separately prepared substrate in a region different from the region surrounded by the sealant 205 over the first substrate 201. In FIG. A scanning line driving circuit 204 and a signal line driving circuit 203 are mounted. Further, various signals and potentials applied to the signal line driver circuit 203 formed separately, the scanning line driver circuit 204, or the pixel portion 202 are FPCs (flexible printed circuits) 218 a and 218 .
supplied by b.

7B and 7C, a sealant 205 is provided so as to surround the pixel portion 202 provided over the first substrate 201 and the scanning line driver circuit 204 . A second substrate 206 is provided over the pixel portion 202 and the scanning line driver circuit 204 . Therefore, the pixel portion 202 and the scanning line driver circuit 204 are composed of the first substrate 201, the sealing material 205, and the second substrate.
It is sealed together with the display element by the substrate 206 of . 7B and 7C, a single crystal semiconductor layer or a polycrystalline layer is formed over a separately prepared substrate in a region different from the region surrounded by the sealant 205 over the first substrate 201 . A signal line driver circuit 203 formed of a semiconductor layer is mounted. 7B and 7C, various signals and potentials are supplied from the FPC 218 to the separately formed signal line driver circuit 203 and the scanning line driver circuit 204 or the pixel portion 202 .

7B and 7C, the signal line driver circuit 203 is separately formed and the first
Although an example of mounting on the substrate 201 is shown, the configuration is not limited to this. The scanning line driver circuit may be separately formed and mounted, or only part of the signal line driver circuit or part of the scanning line driver circuit may be separately formed and mounted.

Note that the connection method of the separately formed drive circuit is not particularly limited, and COG (C
hip On Glass) method, wire bonding method, or TAB (Tape
Automated Bonding) method or the like can be used. FIG. 7(A) shows
This is an example of mounting the signal line driver circuit 203 and the scanning line driver circuit 204 by the COG method. FIG. 7B is an example of mounting the signal line driver circuit 203 by the COG method, and FIG. This is an example of mounting the signal line driving circuit 203 by the TAB method.

Further, the display device includes a panel in which a display element is sealed, and a module in which an IC including a controller is mounted on the panel.

Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Also, a module with a connector such as FPC or TAB tape or TCP attached, a module with a printed wiring board provided at the tip of TAB tape or TCP, or a module with an IC (integrated circuit) directly mounted on a display element by the COG method. shall be included in the display device.

In addition, the pixel portion and the scan line driver circuit provided over the first substrate 201 include a plurality of transistors, and the transistors whose examples are shown in Embodiments 1, 2, and 3 are applied. can do.

As a display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. Light-emitting elements include elements whose luminance is controlled by current or voltage.
luminescence), organic EL, and the like. In addition, a display medium such as electronic ink whose contrast is changed by an electrical action can also be applied.

When a liquid crystal element is used as the display element, thermotropic liquid crystal, low-molecular liquid crystal, polymer liquid crystal, polymer-dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, or the like can be used. Depending on the conditions, these liquid crystal materials have a cholesteric phase, a smectic phase, a cubic phase,
Shows chiral nematic phase, isotropic phase, etc.

Alternatively, a liquid crystal exhibiting a blue phase may be used for which an alignment layer is not required. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the cholesteric phase transitions to the isotropic phase when the temperature of the cholesteric liquid crystal is increased. Since the blue phase is expressed only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less, is optically isotropic, does not require alignment treatment, and has low viewing angle dependency. In addition, rubbing treatment is not required because an alignment layer is not required, so that electrostatic breakdown caused by rubbing treatment can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. . Therefore, it becomes possible to improve the productivity of the liquid crystal display device.

In addition, the specific resistivity of the liquid crystal material is 1×10 ⁹ Ω·cm or more, preferably 1×10 Ω·cm or more.
It is ¹¹ Ω·cm or more, more preferably 1×10 ¹² Ω·cm or more. It should be noted that the value of specific resistivity in this specification is the value measured at 20°C.

The size of the storage capacitor provided in the liquid crystal display device is set in consideration of the leak current of the transistor arranged in the pixel portion so that the charge can be stored for a predetermined period. By using a transistor including a highly purified oxide semiconductor layer, it is sufficient to provide a storage capacitor having a capacitance that is ⅓ or less, preferably ⅕ or less, of the liquid crystal capacitance of each pixel. .

A transistor including an oxide semiconductor layer used in this embodiment can have a low current value in an off state (off-state current value). Therefore, the holding time of an electric signal such as an image signal can be lengthened, and the writing interval can be set long in the power-on state. Therefore, the frequency of the refresh operation can be reduced, which has the effect of suppressing power consumption.

In addition, since the transistor including an oxide semiconductor layer used in this embodiment can have relatively high field-effect mobility, it can be driven at high speed. Therefore, by using the above transistor in a pixel portion of a liquid crystal display device, a high-quality image can be provided. In addition, since the transistor can be separately formed in the driver circuit portion and the pixel portion over the same substrate, the number of components of the liquid crystal display device can be reduced.

Liquid crystal display devices include TN (Twisted Nematic) mode, IPS (In-
Plane-Switching) mode, FFS (Fringe Field Switch
tching) mode, ASM (Axially Symmetrically aligned
Micro-cell) mode, OCB (Optical Compensated)
Birefringence) mode, FLC (Ferroelectric Liquid)
id Crystal) mode, AFLC (AntiFerroelectric Li
Quid Crystal) mode or the like can be used.

Alternatively, a normally black liquid crystal display device, for example, a transmissive liquid crystal display device employing a vertical alignment (VA) mode may be used. Here, the vertical alignment mode is a type of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel, and is a method in which the liquid crystal molecules are oriented perpendicularly to the panel surface when no voltage is applied. Some examples of the vertical alignment mode include MVA (Multi-Domain Vertical Alignment).
ent) mode, PVA (Patterned Vertical Alignment
) mode, ASV mode, etc. can be used. Also, a method called multi-domain formation or multi-domain design, in which a pixel is divided into several regions (sub-pixels) and molecules are tilted in different directions, can be used.

In the display device, optical members (optical substrates) such as a black matrix (light shielding layer), a polarizing member, a retardation member, and an antireflection member are provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Moreover, a backlight, a sidelight, or the like may be used as the light source.

It is also possible to use a plurality of light-emitting diodes (LEDs) as a backlight to perform a time-division display method (field sequential driving method). By applying the field sequential driving method, color display can be performed without using a color filter.

Further, as a display method in the pixel portion, a progressive method, an interlace method, or the like can be used. RGB (
R represents red, G represents green, and B represents blue). For example, RGBW (where W represents white), or RGB plus one or more colors such as yellow, cyan, and magenta. Note that the size of the display area may be different for each dot of the color element. However, the present invention is not limited to a color display device, and can also be applied to a monochrome display device.

A light-emitting element utilizing electroluminescence can be used as a display element included in the display device. Light-emitting elements utilizing electroluminescence are classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

In the organic EL element, when a voltage is applied to the light-emitting element, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, and current flows. Then, recombination of these carriers (electrons and holes) causes the light-emitting organic compound to form an excited state, and light is emitted when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is called a current-excited light-emitting element.

Inorganic EL elements are classified into dispersion type inorganic EL elements and thin film type inorganic EL elements according to the element structure. A dispersion-type inorganic EL device has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder.
This is acceptor recombination type emission. A thin-film inorganic EL device has a structure in which a light-emitting layer is sandwiched between dielectric layers, which are further sandwiched between electrodes, and the light-emitting mechanism is localized light emission utilizing inner-shell electronic transition of metal ions. Note that an organic EL element is used as a light-emitting element in this description.

At least one of the pair of electrodes of the light-emitting element should be transparent in order to emit light. Then, a transistor and a light-emitting element are formed on a substrate, and top emission for extracting light from the surface opposite to the substrate, bottom emission for extracting light from the surface on the substrate side, and the surface on the side of the substrate and the surface opposite to the substrate. There is a light emitting element with a double emission structure in which light is emitted from a double-sided emission structure, and any light emitting element with an emission structure can be applied.

It is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display device (electrophoretic display).
It has the advantage of being as easy to read as paper, consumes less power than other display devices, and can be made thin and light.

Various forms of electrophoretic display devices can be conceived, and a plurality of microcapsules containing positively charged first particles and negatively charged second particles are dispersed in a solvent or solute. By applying an electric field to the microcapsules, the particles in the microcapsules are moved in opposite directions to display only the color of the particles gathered on one side. The first particles or the second particles contain a dye and do not move in the absence of an electric field. Also, the color of the first particles and the color of the second particles are different (including colorless).

Thus, the electrophoretic display device is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region.

A dispersion of the microcapsules in a solvent is called electronic ink,
This electronic ink can be printed on surfaces such as glass, plastic, cloth, and paper. Color display is also possible by using a color filter or pigment-containing particles.

In addition, the first particles and the second particles in the microcapsules are a conductor material, an insulator material,
A material selected from a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof may be used.

A display device using a twist ball display method can also be used as the electronic paper. In the twist ball display method, spherical particles separately painted in white and black are arranged between a first electrode layer and a second electrode layer, which are electrode layers used in a display element, and the first electrode layer and the second electrode layer are arranged. 2
In this method, display is performed by controlling the orientation of spherical particles by generating a potential difference between the electrode layers.

A display device performs display by transmitting light from a light source or a display element. Therefore, thin films such as a substrate, an insulating layer, and a conductive layer provided in a pixel portion through which light is transmitted are all translucent to light in the visible wavelength range.

A first electrode layer and a second electrode layer (pixel electrode layer, common electrode layer,
Also referred to as a counter electrode layer), translucency and reflectivity may be selected depending on the direction of light to be extracted, the location where the electrode layer is provided, and the pattern structure of the electrode layer.

By using the transistor described in Embodiment 1, 2, or 3 as described above, a highly reliable semiconductor device can be provided. Note that the transistors exemplified in Embodiments 1, 2, and 3 are not limited to the above semiconductor devices having a display function; It can be applied to a semiconductor device having various functions such as a semiconductor device having an image sensor function for reading information on an object.

The structures, methods, and the like described in this embodiment can be combined as appropriate with the structures, methods, and the like described in other embodiments.

(Embodiment 5)
A semiconductor device which is one embodiment of the present invention can be applied to various electronic devices (including game machines). Examples of electronic devices include television devices (also referred to as televisions or television receivers), monitors for computers, cameras such as digital cameras and digital video cameras, digital photo frames, mobile phones (mobile phones, mobile phone devices ), portable game machines, personal digital assistants, sound reproduction devices, and large game machines such as pachinko machines. Examples of electronic devices each including the semiconductor device described in the above embodiment will be described.

FIG. 8A shows a notebook personal computer including a main body 301, a housing 302,
It is composed of a display unit 303, a keyboard 304, and the like. By applying the semiconductor device described in any one of Embodiments 1 to 4, a highly reliable laptop personal computer can be obtained.

FIG. 8B shows a personal digital assistant (PDA) in which a main body 311 is provided with a display portion 313, an external interface 315, operation buttons 314, and the like. Also, there is a stylus 312 as an accessory for operation. By applying the semiconductor device described in any one of Embodiments 1 to 3, a more reliable personal digital assistant (PDA) can be obtained.

FIG. 8C shows an example of an electronic book. For example, the electronic book 320 has a housing 321
and a housing 322 . The housing 321 and the housing 322 are connected to the shaft portion 32
5, and can be opened and closed with the shaft portion 325 as an axis. With such a configuration, it is possible to operate like a paper book.

A display unit 323 is incorporated in the housing 321 and a display unit 324 is incorporated in the housing 322 . The display unit 323 and the display unit 324 may be configured to display a continuation screen, or may be configured to display different screens. By configuring to display different screens, for example, text is displayed on the right display unit (display unit 323 in FIG. 8(C)) and text is displayed on the left display unit (FIG. 8(C)
) can display an image on the display unit 324). By using the semiconductor device described in any one of Embodiments 1 to 4, the e-book reader can have high reliability.

FIG. 8C shows an example in which the housing 321 is provided with an operation unit and the like. For example, a housing 321 includes a power source 326, operation keys 327, a speaker 328, and the like.
An operation key 327 can be used to turn pages. Note that a keyboard, a pointing device, and the like may be provided on the same surface of the housing as the display unit. In addition, a configuration may be adopted in which external connection terminals (earphone terminal, USB terminal, etc.), a recording medium insertion section, and the like are provided on the rear surface or side surface of the housing. Furthermore, the electronic book 320 may be configured to have a function as an electronic dictionary.

Further, the electronic book 320 may be configured to transmit and receive information wirelessly. wirelessly,
It is also possible to purchase and download desired book data from an electronic book server.

FIG. 8D shows a portable information terminal including two housings, a housing 330 and a housing 331 . A housing 331 includes a display panel 332 , a speaker 333 , a microphone 3
34, a pointing device 336, a camera lens 337, an external connection terminal 338, and the like. The housing 330 also includes a solar battery cell 340 for charging the portable information terminal.
, an external memory slot 341, and the like. Also, the antenna is built inside the housing 331 . By applying the semiconductor device shown in any one of Embodiments 1 to 4,
A highly reliable portable information terminal can be obtained.

The display panel 332 has a touch panel, and a plurality of operation keys 335 displayed as images are indicated by dotted lines in FIG. 8D. A booster circuit is also mounted for boosting the voltage output from the photovoltaic cell 340 to a voltage required for each circuit.

The display direction of the display panel 332 is appropriately changed according to the usage pattern. In addition, since the camera lens 337 is provided on the same plane as the display panel 332, a videophone call is possible.
The speaker 333 and the microphone 334 can be used not only for voice calls, but also for video calls, recording, playback, and the like. Furthermore, the housing 330 and the housing 331 can be slid from the unfolded state shown in FIG.

The external connection terminal 338 can be connected to various cables such as an AC adapter and a USB cable, allowing charging and data communication with a personal computer or the like. Also, by inserting a recording medium into the external memory slot 341, it is possible to store and transfer a larger amount of data.

Moreover, in addition to the above functions, an infrared communication function, a television reception function, and the like may be provided.

FIG. 8E shows a digital video camera, which includes a main body 351, a display portion (A) 357, an eyepiece portion 353, operation switches 354, a display portion (B) 355, a battery 356, and the like. By using the semiconductor device described in any one of Embodiments 1 to 4, a highly reliable digital video camera can be obtained.

FIG. 8F shows an example of a television device. A display unit 363 is incorporated in a housing 361 of the television device 360 . A video can be displayed on the display unit 363 . Also, here, a configuration in which the housing 361 is supported by a stand 365 is shown. By using the semiconductor device described in any one of Embodiments 1 to 4, the television device 360 can have high reliability.

The television apparatus 360 can be operated by operating switches provided on the housing 361 or a separate remote controller. Further, the remote controller may be provided with a display section for displaying information output from the remote controller.

Note that the television device 360 is configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts, and by connecting to a wired or wireless communication network via a modem, it can be unidirectional (from the sender to the receiver) or bidirectional (from the sender to the receiver). It is also possible to communicate information between recipients, or between recipients, etc.).

The structures, methods, and the like described in this embodiment can be combined as appropriate with the structures, methods, and the like described in other embodiments.

100 substrate 101 first region 102 second region 103 insulating layer 104 first insulating layer 105 second insulating layer 106 oxide semiconductor layer 108a wiring 108b wiring 112 gate insulating layer 113 gate insulating layer 114 gate electrode 116a source electrode 116b drain electrode 122a source region 122b drain region 123a offset region 123b offset region 124 interlayer insulating layer 126 channel region 130 sidewall insulating layer 131 first insulating layer 132 second insulating layer 133 third insulating layer 136 oxide semiconductor layer 155 Transistor 156 Transistor 201 Substrate 202 Pixel portion 203 Signal line driver circuit 204 Scanning line driver circuit 205 Sealing material 206 Substrate 218 FPC
218a FPC
218b FPC
301 main body 302 housing 303 display section 304 keyboard 311 main body 312 stylus 313 display section 314 operation buttons 315 external interface 320 electronic book 321 housing 322 housing 323 display section 324 display section 325 shaft section 326 power supply 327 operation keys 328 speaker 330 housing Body 331 Housing 332 Display Panel 333 Speaker 334 Microphone 335 Operation Keys 336 Pointing Device 337 Camera Lens 338 External Connection Terminal 340 Solar Cell 341 External Memory Slot 351 Main Body 353 Eyepiece 354 Operation Switch 355 Display (B)
356 Battery 357 Display (A)
360 television device 361 housing 363 display unit 365 stand

Claims (2)

an insulating layer having a first region and a second region;
an oxide semiconductor layer provided in contact with the first region and the second region;
a gate insulating layer provided in contact with the oxide semiconductor layer, a source electrode, and a drain electrode;
a gate electrode provided in contact with the gate insulating layer;
the gate insulating layer is in contact with a side surface of the source electrode and a side surface of the drain electrode;
the oxide semiconductor layer has a channel region, a source region and a drain region;
the channel region is in contact with the first region ;
the source region and the drain region are in contact with the second region ;
The first region has silicon oxide,
The semiconductor device, wherein the second region includes silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum nitride, or aluminum oxynitride. In claim 1,
The semiconductor device, wherein the oxide semiconductor layer has a region overlapping with the gate insulating layer and not overlapping with the gate electrode.

Images