JP5322530B2 - Thin film field effect transistor manufacturing method and thin film field effect transistor manufactured by the manufacturing method - Google Patents

Description

  The present invention relates to a method for manufacturing a thin film field effect transistor using an oxide semiconductor in an active layer. In particular, the present invention relates to a method for manufacturing a thin film field effect transistor excellent in driving stability. Furthermore, the present invention relates to a thin film field effect transistor manufactured by the manufacturing method.

2. Description of the Related Art In recent years, flat and thin image display devices (Flat Panel Displays: FPD) have been put into practical use due to advances in liquid crystal and electroluminescence (EL) technologies. In particular, an organic electroluminescent device using a thin film material that emits light when excited by passing an electric current (hereinafter sometimes referred to as “organic EL device”) can emit light with high luminance at a low voltage. Device thinning, lightening, miniaturization, and power saving are expected in a wide range of fields including mobile phone displays, personal digital assistants (PDAs), computer displays, automobile information displays, TV monitors, or general lighting. ing.
These FPDs are active field-effect thin film transistors (hereinafter referred to as “Thin Film Transistor” or “TFT”) that use an amorphous silicon thin film or a polycrystalline silicon thin film provided on a glass substrate as an active layer. It is driven by a matrix circuit.

On the other hand, in order to further reduce the thickness, weight, and breakage resistance of these FPDs, an attempt has been made to use a lightweight and flexible resin substrate instead of a glass substrate.
However, the manufacture of the transistor using the above-described silicon thin film requires a relatively high temperature thermal process and is generally difficult to form directly on a resin substrate having low heat resistance.
Therefore, an oxide semiconductor that can be formed at a low temperature, for example, a TFT using InGaZnO can be formed at room temperature and can be formed on a film. Yes. In particular, since an oxide semiconductor can obtain high mobility, it is expected as a pixel driving TFT of an organic EL element (see, for example, Patent Document 1).

  As a method for manufacturing a TFT using an oxide semiconductor as an active layer, a predetermined region of the oxide semiconductor is irradiated with energy rays to change the conductivity of the oxide semiconductor, and the region is used as a source electrode and a drain electrode. (For example, refer to Patent Document 2).

On the other hand, problems with TFTs using an oxide semiconductor as an active layer have been pointed out.
For example, there is a problem of causing unstable operation due to change in atmosphere, and a protective film is formed on the TFT element by a metal oxide film, a silicon nitride film, a silicon carbide film, an organic material, or a laminated film of an organic material and a metal film. Is disclosed (for example, see Patent Document 3).

In addition, when an active layer using an oxide semiconductor is in contact with a general non-fluorinated resin (such as an epoxy resin or an acrylic resin), the threshold value in the voltage-current curve of the TFT fluctuates by about -30 V due to driving. It is disclosed that a fluorinated resin is installed as a protective film (see, for example, Patent Document 4).
JP 2006-165529 A JP 2007-73699 A JP 2007-73705 A JP 2007-299913 A

  An object of the present invention is to provide a method for manufacturing a thin film field effect transistor using an oxide semiconductor having a high ON / OFF ratio and excellent operational stability. In particular, an object of the present invention is to provide a method for manufacturing a high-performance thin-film field effect transistor that can be fabricated on a flexible resin substrate. Furthermore, it is providing the thin film field effect transistor manufactured by this manufacturing method.

The above-described problems of the present invention have been solved by the following means.
<1> At least on an insulating substrate,
(1) forming a gate electrode;
(2) forming a gate insulating film by covering the gate electrode;
(3) forming an active layer made of an oxide semiconductor in contact with the gate insulating film;
(4) A step of forming a resistance layer in contact with the active layer and having an electrical conductivity of 10 ⁻⁹ Scm ⁻¹ or less made of an oxide semiconductor having a lower electrical conductivity than the active layer,
(5) A part of the resistance layer is subjected to a low resistance process such as a UV process or a plasma process using oxygen so that the electric conductivity is 10 ⁻⁸ Scm ⁻¹ or more, and at least 2 at a predetermined interval. A low resistance treatment step for forming two low resistance regions, and a region between the two low resistance regions that has not been subjected to the low resistance treatment (non-low resistance region) And (6) a thin film field effect comprising a source / drain electrode forming step of forming a source electrode in contact with one of the two low resistance regions and a drain electrode in contact with the other. Type transistor manufacturing method.
<2> The method for producing a thin film field effect transistor according to <1>, wherein the electric conductivity of the active layer is 10 ⁻⁶ Scm ⁻¹ or more and less than 10 ² Scm ⁻¹ .
< 3 > The method for manufacturing a thin film field effect transistor according to <1> or <2>, wherein the thickness of the resistance layer is larger than the thickness of the active layer.
<4> the method of manufacturing a thin film field effect transistor according to any one of <1> to <3>, wherein the oxide semiconductor is an amorphous oxide semiconductor.
< 5 > The method for producing a thin film field effect transistor according to < 4 >, wherein the oxygen concentration of the active layer is lower than the oxygen concentration of the resistance layer.
< 6 > The thin film field effect transistor according to < 4 > or < 5 >, wherein the oxide semiconductor includes at least one selected from the group consisting of In, Ga, and Zn, or a composite oxide thereof. Manufacturing method.
< 7 > The oxide semiconductor contains the In and Zn, and the composition ratio of Zn and In (represented by the ratio of Zn to In, Zn / In) of the resistance layer is larger than the composition ratio Zn / In of the active layer < 6 > The method for producing a thin-film field effect transistor according to < 6 >.
<8> method of manufacturing a thin film field effect transistor according to any one of <1> to <7>, wherein the substrate is a flexible resin substrate.
<9> <1> to thin film field effect transistor manufactured by the manufacturing method according to any one of <8>.

  According to the present invention, it is possible to provide a method of manufacturing a thin film field effect transistor that exhibits a high ON / OFF ratio and excellent driving stability, and a thin film field effect transistor using the same. In particular, a method of manufacturing a thin film field effect transistor useful as a film (flexible) TFT using a flexible substrate and a thin film field effect transistor using the same can be provided.

1. Thin Film Field Effect Transistor A thin film field effect transistor according to the present invention includes at least a step of forming a gate electrode on an insulating substrate, a step of covering the gate electrode to form a gate insulating film, and contacting the gate insulating film. A step of forming an active layer made of an oxide semiconductor, and forming a resistance layer in contact with the active layer and having an electric conductivity of 10 ⁻⁹ Scm ⁻¹ or less made of an oxide semiconductor having a lower electric conductivity than the active layer A step of reducing the resistance of a part of the resistance layer by a UV treatment or a plasma treatment with oxygen so that the electric conductivity becomes 10 ⁻⁸ Scm ⁻¹ or more. Is a low resistance treatment process for forming two low resistance regions, and a region between the two low resistance regions that has not been subjected to the low resistance treatment (non-low resistance region) A thin film field effect transistor is formed by a source / drain electrode forming step formed inside a gate electrode and having a source electrode in contact with one of the two low resistance regions and a drain electrode in contact with the other. Is done.

  The resistance layer in the present invention functions as a protective layer for the active layer, prevents fluctuations in the operation of the TFT due to changes in the atmosphere, or is in direct contact with a non-fluorinated resin used for protecting a thin film field effect transistor. Function to prevent threshold fluctuations. On the other hand, the electric conductivity of the region of the resistance layer that contacts the source electrode and the drain electrode is increased by the resistance reduction process, and the active layer has sufficient electric conductivity between the source electrode and the drain electrode.

  Furthermore, according to the present invention, even when the oxide semiconductor of the active layer has high mobility, it is possible to provide a TFT having a high ON / OFF ratio while suppressing the OFF current.

  According to the manufacturing method of the present invention, there is no need to provide a new protective layer as disclosed in JP 2007-73705 A or JP 2007-299913 A, and the manufacturing process is simple.

  In addition, as a result of investigations by the present inventors, it has been found that the oxide semiconductor layer can be increased in electrical conductivity by plasma irradiation or UV ozone treatment, and the low resistance treatment process is industrially highly productive. It has been found that it can be realized.

The electric conductivity of the non-resistance region of the resistance layer is 10 ⁻⁹ Scm ⁻¹ or less, more preferably 10 ⁻¹⁰ Scm ⁻¹ or less.
The low resistance Koka treatment, electrical conductivity after resistance reduction processing steps is increased to ¹⁰ -8 ^{Scm -1} or higher. More preferably, it is 10 < ^-6 > Scm < ^-1 > or more, More preferably, it is 10 < ⁰ > Scm < ^-1 > or more.
A lower resistance is more preferable because the contact resistance between the active layer and the source and drain electrodes is reduced.

Preferably, the electric conductivity of the active layer is 10 ⁻⁶ Scm ⁻¹ or more and less than 10 ² Scm ⁻¹ , more preferably 10 ⁻⁴ Scm ⁻¹ or more and less than 10 ² Scm ⁻¹ , and even more preferably 10 ^{− 1} Scm ⁻¹ or more and less than 10 ² Scm ⁻¹ .
It is not preferable because not operate as a TFT in the electric conductivity of the active layer is less than ¹⁰ -6 ^{Scm -1,} undesirable since the conductor at 10 2 ^{Scm -1} or more.

The positional relationship on the plane of the non-low resistance region and the gate electrode in the present invention is represented by the relative positional relationship between the width of the non-low resistance region and the gate electrode in the schematic sectional view (for example, FIG. 1), respectively. The “The unreduced region is formed on the plane and inside the gate electrode” means that the width of the unreduced region is the same as or narrower than the width of the gate electrode on the schematic cross-sectional view. , Which is formed immediately above the gate electrode, and means that the end portion of the non-low resistance region coincides with or is located inside the end portion of the gate electrode.
The difference between the width of the unreduced resistance region and the gate electrode (represented by (d + d ′) in FIG. 1) is preferably 0 μm to 50 μm, more preferably 0 μm to 20 μm, and still more preferably 0 μm to 5 μm. It is.
If the non-low resistance region extends beyond the gate electrode surface to a region where the gate electrode does not exist, it is not preferable because the ON current during TFT operation becomes low or cannot be operated.

Preferably, the resistance layer is thicker than the active layer.
Preferably, the oxide semiconductor is an amorphous oxide semiconductor.
Preferably, the oxygen concentration of the active layer is lower than the oxygen concentration of the resistance layer.
Preferably, the oxide semiconductor includes at least one selected from the group consisting of In, Ga, and Zn, or a composite oxide thereof. More preferably, the oxide semiconductor contains In and Zn, and the composition ratio of Zn and In (represented by the ratio of Zn to In, Zn / In) of the resistance layer is larger than the composition ratio Zn / In of the active layer.
Preferably, the substrate is a flexible resin substrate.

1) Structure Next, the structure of the thin film field effect transistor according to the present invention and the manufacturing method thereof will be described in detail with reference to the drawings.
FIG. 1 is a schematic view showing an example of an inverted staggered structure, which is a thin film field effect transistor obtained by the manufacturing method of the present invention. When the insulating substrate 1 is a flexible substrate such as a plastic film, an insulating substrate having an insulating layer disposed on one surface of the substrate is used. A gate electrode 2, a gate insulating film 3, an active layer 4, and a resistance layer 6 are provided on the insulating layer. Regions of the resistance layer 6 that are in contact with the source electrode and the drain electrode are subjected to a resistance reduction treatment to form the resistance reduction layers 7-1 and 7-2. The width of the non-low resistance region 6-2 not subjected to the low resistance treatment is narrower than the width of the gate electrode 2 (gap d, d ′: (gate electrode width) − (width of the non-low resistance region). )> 0), arranged in the gate electrode plane.

A source electrode 5-2 and a drain electrode 5-1 are disposed on the low resistance layers 7-1 and 7-2. The protective film 8 covers the entire surface of the obtained laminate except for the electrical connection portion of the source electrode 5-2. The surface of the active layer 4 is disconnected from the protective film 6 directly by the resistance layer 6. Further, the active layer 4 and the source electrode 5-2 and the drain electrode 5-1 are electrically connected by the low resistance layers 7-1 and 7-2.
Therefore, according to this configuration, even if a sealing resin such as an epoxy resin or an acrylic resin is used for the protective film, the threshold fluctuation of the TFT operation can be kept small.
Further, by using an oxide semiconductor disclosed in JP-A-2006-165529, for example, an In—Ga—Zn—O-based oxide semiconductor for the active layer, high electron mobility can be obtained. According to the stacked structure of the active layer and the resistance layer in the present invention, the active layer serving as a channel has a large electric conductivity when the thin film field effect transistor is in an ON state where a voltage is applied to the gate electrode. The field effect mobility of the transistor is increased, and a high ON current can be obtained. Since the electric resistance of the resistance layer is small in the OFF state and the resistance of the resistance layer is high, the OFF current is kept low, so that the ON / OFF ratio characteristics are improved.

2 to 9 are schematic views showing an example of a manufacturing process of a thin film field effect transistor according to the present invention.
The gate electrode 2 is patterned and installed on the insulating surface of the insulating substrate 1 (FIG. 3). On top of this, a gate insulating film 3, an active layer 4, and a resistance layer 6 are sequentially provided (FIGS. 4 to 6). Subsequently, a mask made of a resist film is formed by photolithography. Through the mask, a resistance reduction process such as oxygen plasma radiation or UV ozone irradiation is performed (FIG. 7). When the resistance reduction treatment process is performed, the electrical resistance of the portion exposed to the irradiation is lowered, and the resistance reduction regions 7-1 and 7-2 are formed. A region (unreduced resistance region 6-2) that is protected by the resist and not subjected to the resistance reduction treatment is formed between the resistance reduction regions 7-1 and 7-2. The rate of decrease in resistance in the low resistance region can be controlled by the irradiation energy intensity and the irradiation time (FIG. 8). In the present invention, electric resistance is the reciprocal of electric conductivity, and a decrease in resistance means an increase in electric conductivity, and a reduction in resistance can be quantitatively expressed by the value of electric conductivity.

  After the low resistance process, the drain electrode 5-1 and the source electrode 5-2 are provided in contact with the low resistance region. In the present invention, the drain electrode 5-1 and the source electrode 5-2 may be at least partially in contact with the low resistance region.

  10 to 13 are schematic views showing a manufacturing process by a resistance reduction process according to another aspect of the present invention. 2 to 6 are the same as those in the first aspect. After the resistance layer 6 is formed, a resist pattern in which only a region where the source electrode and the drain electrode are provided is formed by photolithography (FIG. 10). Using the resist pattern as a mask, a resistance reduction process such as oxygen plasma radiation or UV ozone irradiation is performed (FIG. 10). The electrical resistance of the location exposed to the irradiation decreases (FIG. 11). Then, an electrode layer for forming a source electrode and a drain electrode is formed on the entire surface (FIG. 12). Thereafter, when the resist film is peeled off by the lift-off method, the electrode layer formed on the resist is removed together with the resist, so that the electrode layer remains only in the portion subjected to the resistance reduction treatment, and the drain electrode 15-1, A source electrode 15-2 is formed (FIG. 13).

FIG. 14 shows a thin film field effect transistor according to another embodiment obtained by the manufacturing method of the present invention. Although the structure is the same as that in FIG. 1, the gate electrode and the non-low resistance region overlap on a plane (gap d, d ′ = 0; (gate electrode width) − (non-low resistance region width)) = 0).
FIG. 15 shows a thin film field effect transistor according to a comparative example. 1 has the same configuration, but the width of the unreduced region is wider than the width of the gate electrode surface (gap d, d ′: (gate electrode width) − (unreduced region width)) <0. ).

2) Electric conductivity The electric conductivity of the active layer and the resistance layer in the present invention will be described.
The electrical conductivity is a physical property value indicating the ease of electrical conduction of a substance. When the carrier concentration n of the substance is e, the elementary charge is e, and the carrier mobility is μ, the electrical conductivity σ of the substance is expressed by the following equation. expressed.
σ = neμ
When the active layer or the resistance layer is an n-type semiconductor, the carriers are electrons, the carrier concentration indicates the electron carrier concentration, and the carrier mobility indicates the electron mobility. Similarly, when the resistance layer is a p-type semiconductor, the carriers are holes, the carrier concentration indicates the hole carrier concentration, and the carrier mobility indicates the hole mobility. The carrier concentration and carrier mobility of the substance can be obtained by Hall measurement.

<How to find electrical conductivity>
By measuring the sheet resistance of a film whose thickness is known, the electrical conductivity of the film can be determined. Although the electrical conductivity of a semiconductor varies with temperature, the electrical conductivity described in the text indicates the electrical conductivity at room temperature (20 ° C.).

3) Gate insulating film As the gate insulating film, at least two or more insulators such as SiO ₂ , SiN _x , SiON, Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , and HfO ₂ are used. A mixed crystal compound is used. A polymer insulator such as polyimide can also be used as the gate insulating film.

The thickness of the gate insulating film is preferably 10 nm to 10 μm. The gate insulating film needs to be thickened to some extent in order to reduce leakage current and increase voltage resistance. However, increasing the thickness of the gate insulating film results in an increase in the driving voltage of the TFT. Therefore, it is more preferable that the film thickness of the gate insulating film is 50 nm to 1000 nm for an inorganic insulator and 0.5 μm to 5 μm for a polymer insulator. In particular, it is particularly preferable to use a high dielectric constant insulator such as HfO ₂ for the gate insulating film because TFT driving at a low voltage is possible even if the film thickness is increased.

4) Active layer and resistance layer It is preferable to use an oxide semiconductor for the active layer and the resistance layer used in the present invention. In particular, an amorphous oxide semiconductor is more preferable. An oxide semiconductor, particularly an amorphous oxide semiconductor, can be formed at a low temperature, and thus can be formed over a flexible resin substrate such as a plastic. Good amorphous oxide semiconductors that can be manufactured at low temperatures include oxides containing In, oxides containing In and Zn, In, Ga, and Zn as disclosed in JP-A-2006-165529. It is known that InGaO ₃ (ZnO) _m (m is a natural number of less than 6) is preferable as the composition structure. These are n-type semiconductors whose carriers are electrons. Of course, a p-type oxide semiconductor such as ZnO.Rh ₂ O ₃ , CuGaO ₂ , or SrCu ₂ O ₂ may be used for the active layer and the resistance layer.

Specifically, the amorphous oxide semiconductor according to the present invention includes In—Ga—Zn—O, and the composition in the crystalline state is represented by InGaO ₃ (ZnO) _m (m is a natural number of less than 6). A physical semiconductor is preferred. In particular, InGaZnO ₄ is more preferable. As an amorphous oxide semiconductor having this composition, the electron mobility tends to increase as the electrical conductivity increases. Japanese Patent Laid-Open No. 2006-165529 discloses that the electric conductivity can be controlled by the oxygen partial pressure during film formation.
Of course, the active layer and the resistance layer can be applied not only to oxide semiconductors but also to inorganic semiconductors such as Si and Ge, compound semiconductors such as GaAs, organic semiconductor materials such as pentacene and polythiophene, carbon nanotubes, and the like.

<Electrical conductivity of active layer and resistance layer>
In the present invention, the active layer is close to the gate insulating film and has a higher electric conductivity than the resistance layer close to the source electrode and the drain electrode.
Preferably, the electric conductivity of the active layer is 10 ⁻⁶ Scm ⁻¹ or more and less than 10 ² Scm ⁻¹ . More preferably less than ¹⁰ -4 ^{Scm -1} or more ¹⁰ 2 ^{Scm -1,} more preferably less than ¹⁰ -1 ^{Scm -1} or more ¹⁰ 2 ^{Scm -1.}
Electrical conductivity of the resistive layer is previously subjected to resistance reduction processing is the ¹ 0 -9 ^{Scm -1} or less, more preferably ¹⁰ -10 ^{Scm -1} or less.

<Thickness of active layer and resistance layer>
The resistance layer is preferably thicker than the active layer. More preferably, the ratio of the thickness of the resistance layer to the thickness of the active layer is more than 1 and 100 or less, more preferably more than 1 and 10 or less.
The thickness of the active layer is preferably 1 nm to 100 nm, more preferably 2.5 nm to 30 nm. The thickness of the resistance layer is preferably 5 nm or more and 500 nm or less, and more preferably 10 nm or more and 100 nm or less. The thickness of the region subjected to the resistance reduction treatment is equal to the thickness of the resistance layer, that is, the thickness of the non-resistance reduction region.

By using the active layer and the resistance layer having the above structure, transistor characteristics with an ON / OFF ratio of 10 ⁶ or more can be realized.

<Measuring means for electrical conductivity>
As a means for adjusting electric conductivity, the following means can be cited when the active layer and the resistance layer are oxide semiconductors.

(1) Adjustment by oxygen defect It is known that when an oxygen defect is formed in an oxide semiconductor, carrier electrons are generated and electric conductivity is increased. Therefore, the electric conductivity of the oxide semiconductor can be controlled by adjusting the amount of oxygen defects. Specific methods for controlling the amount of oxygen defects include oxygen partial pressure during film formation, oxygen concentration and treatment time during post-treatment after film formation, and the like. Specific examples of post-treatment include heat treatment at 100 ° C. or higher, oxygen plasma, and UV ozone treatment. Among these methods, a method of controlling the oxygen partial pressure during film formation is preferable from the viewpoint of productivity. JP-A 2006-165529 discloses that the electric conductivity of an oxide semiconductor can be controlled by adjusting the oxygen partial pressure during film formation, and this technique can be used.

(2) Adjustment by composition ratio It is known that the electrical conductivity changes by changing the metal composition ratio of an oxide semiconductor. For example, Japanese Patent Laid-Open No. 2006-165529 discloses that in InGaZn _1-X Mg _X O ₄ , the electrical conductivity decreases as the Mg ratio increases. In addition, in the oxide system of (In ₂ O ₃ ) _1-X (ZnO) _X , it has been reported that when the Zn / In ratio is 10% or more, the electrical conductivity decreases as the Zn ratio increases. ("New development of transparent conductive film II" CMC Publishing Co., Ltd. P.34-35). As specific methods for changing these composition ratios, for example, in a film formation method by sputtering, targets having different composition ratios are used. Alternatively, it is possible to change the composition ratio of the film by co-sputtering with a multi-target and adjusting the sputtering rate individually.

(3) Adjustment by impurities By adding an element such as Li, Na, Mn, Ni, Pd, Cu, Cd, C, N, or P to the oxide semiconductor as an impurity, reducing the electron carrier concentration, That is, it is disclosed in Japanese Patent Application Laid-Open No. 2006-165529 that electric conductivity can be reduced. As a method for adding an impurity, an oxide semiconductor and an impurity element are co-evaporated, an ion of the impurity element is added to the formed oxide semiconductor film by an ion doping method, or the like.

(4) Adjustment by oxide semiconductor material In the above (1) to (3), the method for adjusting the electric conductivity in the same oxide semiconductor system has been described. Of course, the electric conductivity can be changed by changing the oxide semiconductor material. You can change the degree. For example, it is generally known that a SnO ₂ oxide semiconductor has a lower electrical conductivity than an In ₂ O ₃ oxide semiconductor. By changing the oxide semiconductor material in this manner, the electric conductivity can be adjusted. In particular, as an oxide material having low electrical conductivity, oxide insulator materials such as Al ₂ O ₃ , Ga ₂ O ₃ , ZrO ₂ , Y ₂ O ₃ , Ta ₂ O ₃ , MgO, or HfO ₃ are known. These can also be used.
As means for adjusting the electrical conductivity, the above methods (1) to (4) may be used alone or in combination.

<Method for forming active layer and resistance layer>
As a method for forming the active layer and the resistance layer, a vapor phase film formation method is preferably used with a polycrystalline sintered body of an oxide semiconductor as a target. Among vapor deposition methods, sputtering and pulsed laser deposition (PLD) are suitable. Furthermore, the sputtering method is preferable from the viewpoint of mass productivity.

  For example, the film is formed by controlling the degree of vacuum and the oxygen flow rate by RF magnetron sputtering deposition. The greater the oxygen flow rate, the smaller the electrical conductivity.

The formed film can be confirmed to be an amorphous film by a known X-ray diffraction method.
The film thickness can be determined by stylus surface shape measurement. The composition ratio can be determined by an RBS (Rutherford backscattering) analysis method.

5) Low resistance treatment The low resistance treatment in the present invention is to lower the electrical conductivity of the resistance layer and to electrically connect the source and drain electrodes and the active layer.
Electrical conductivity of the resistive layer after the low resistance Koka treatment (electric conductivity of the low-resistance region) ^is 10 -8 ^{Scm -1} or higher. More preferably, it is 10 < ^-6 > Scm < ^-1 > or more, More preferably, it is 10 < ⁰ > Scm < ^-1 > or more.

The resistance reduction processing means, the oxide semiconductor is based on the fact that electric conductivity varies by oxygen concentration, the oxygen plasma irradiation, it takes advantage of UV ozone treatment. The reduction rate can be controlled by the irradiation energy intensity of plasma irradiation, the ozone generation concentration in the UV ozone treatment, and the irradiation time. The plasma irradiation apparatus and the UV ozone treatment apparatus are not particularly limited, and commercially available apparatuses can be used.

6) Gate electrode Examples of the gate electrode in the present invention include metals such as Al, Mo, Cr, Ta, Ti, Au, or Ag, alloys such as Al-Nd and APC, tin oxide, zinc oxide, indium oxide, Preferable examples include metal oxide conductive films such as indium tin oxide (ITO) and zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or mixtures thereof.
The thickness of the gate electrode is preferably 10 nm or more and 1000 nm or less.

  The electrode film formation method is not particularly limited, and may be a printing method, a wet method such as a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a CVD method, a plasma CVD method, or the like. It can be formed on the substrate according to a method appropriately selected in consideration of suitability with the material from among chemical methods. For example, when ITO is selected, it can be performed according to a direct current or high frequency sputtering method, a vacuum deposition method, an ion plating method, or the like. When an organic conductive compound is selected as the material for the gate electrode, it can be performed according to a wet film forming method.

7) Source electrode and drain electrode As the source electrode and drain electrode material in the present invention, for example, metal such as Al, Mo, Cr, Ta, Ti, Au, or Ag, alloy such as Al-Nd, APC, tin oxide, Preferred examples include metal oxide conductive films such as zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or mixtures thereof. .
The thickness of the source electrode and the drain electrode is preferably 10 nm or more and 1000 nm or less.

  The electrode film formation method is not particularly limited, and may be a printing method, a wet method such as a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a CVD method, a plasma CVD method, or the like. It can be formed on the substrate according to a method appropriately selected in consideration of suitability with the material from among chemical methods. For example, when ITO is selected, it can be performed according to a direct current or high frequency sputtering method, a vacuum deposition method, an ion plating method, or the like. Further, when an organic conductive compound is selected as a material for the source electrode and the drain electrode, it can be performed according to a wet film forming method.

8) Substrate The substrate used in the present invention is not particularly limited. For example, YSZ (zirconia stabilized yttrium), inorganic materials such as glass, polyethylene terephthalate, polybutylene terephthalate, polyethylene naphthalate Synthetic resins such as polyester such as polyester, polystyrene, polycarbonate, polyethersulfone, polyarylate, allyl diglycol carbonate, polyimide, polycycloolefin, norbornene resin, poly (chlorotrifluoroethylene), etc. Organic materials, and the like. In the case of the said organic material, it is preferable that it is excellent in heat resistance, dimensional stability, solvent resistance, electrical insulation, workability, low air permeability, or low hygroscopicity.

  In the present invention, a flexible substrate is particularly preferably used. The material used for the flexible substrate is preferably an organic plastic film having a high transmittance. For example, polyesters such as polyethylene terephthalate, polybutylene phthalate, polyethylene naphthalate, polystyrene, polycarbonate, polyethersulfone, polyarylate, polyimide, polycyclo Plastic films such as olefin, norbornene resin, and poly (chlorotrifluoroethylene) can be used. In addition, if the insulating property is insufficient for the film-like plastic substrate, the insulating layer, the gas barrier layer for preventing the transmission of moisture and oxygen, the flatness of the film-like plastic substrate and the adhesion with the electrode and active layer It is also preferable to provide an undercoat layer or the like for improvement.

  Here, the thickness of the flexible substrate is preferably 50 μm or more and 500 μm or less. This is because it is difficult for the substrate itself to maintain sufficient flatness when the thickness of the flexible substrate is less than 50 μm. Further, when the thickness of the flexible substrate is more than 500 μm, it is difficult to bend the substrate itself freely, that is, the flexibility of the substrate itself is poor.

9) Protective insulating film If necessary, a protective insulating film may be provided on the TFT. The protective insulating film has a purpose of protecting the semiconductor layer of the active layer or the resistance layer from deterioration due to the atmosphere and a purpose of insulating the electronic device manufactured on the TFT.

Specific examples thereof include MgO, SiO, SiO ₂ , Al ₂ O ₃ , GeO, NiO, CaO, BaO, Fe ₂ O ₃ , Y ₂ O ₃ , or metal oxides such as TiO ₂ , SiN _x , SiN _x. Metal nitride such as O _y , metal fluoride such as MgF ₂ , LiF, AlF ₃ , or CaF ₂ , polyethylene, polypropylene, polymethyl methacrylate, polyimide, polyurea, polytetrafluoroethylene, polychlorotrifluoroethylene, polydichloro Difluoroethylene, a copolymer of chlorotrifluoroethylene and dichlorodifluoroethylene, a copolymer obtained by copolymerizing a monomer mixture containing tetrafluoroethylene and at least one comonomer, and a cyclic structure in the copolymer main chain Fluorine-containing copolymer having water absorption of 1% or more And moisture-proof substances having a water absorption rate of 0.1% or less.

  The method for forming the protective insulating film is not particularly limited. For example, a vacuum deposition method, a sputtering method, a reactive sputtering method, an MBE (molecular beam epitaxy) method, a cluster ion beam method, an ion plating method, a plasma polymerization method ( High-frequency excitation ion plating method), plasma CVD method, laser CVD method, thermal CVD method, gas source CVD method, coating method, printing method, or transfer method can be applied.

10) Post-treatment If necessary, heat treatment may be performed as a post-treatment of the TFT. The heat treatment is performed at a temperature of 100 ° C. or higher in the air or in a nitrogen atmosphere. As a process of performing the heat treatment, the semiconductor layer may be formed after the film formation or may be performed at the end of the TFT manufacturing process. By performing the heat treatment, there are effects such as suppression of in-plane variation in TFT characteristics and improvement in driving stability.

2. Display Device The field effect thin film transistor of the present invention is preferably used for an image display device using liquid crystal or an EL element, in particular, a flat panel display (FPD). More preferably, it is used for a flexible display device using a flexible substrate such as an organic plastic film as the substrate. In particular, the field effect thin film transistor of the present invention is most preferably used for a display device using an organic EL element and a flexible organic EL display device because of its high mobility.

(application)
The field effect thin film transistor of the present invention is used as a switching device and a driving device of the above display device, particularly an FPD, and is a mobile phone display, personal digital assistant (PDA), computer display, automobile information display, TV monitor, or general illumination. It is applied in a wide range of fields including
In addition to the display device, the field effect thin film transistor of the present invention can be widely applied to IC cards, ID tags, etc. by forming the field effect thin film transistor of the present invention on a flexible substrate such as an organic plastic film. Is possible.

  Hereinafter, the thin film field effect transistor of the present invention will be described with reference to examples, but the present invention is not limited to these examples.

Example 1
1. Production of TFT Element 1) Production of Comparative TFT Element A A TFT element A not subjected to a resistance reduction treatment as a reference was produced as follows.
As the substrate, an alkali-free glass plate (Corning, product number NO. 1737) was used.
On the substrate that had been subjected to ultrasonic cleaning in the order of 15 minutes of pure water → 15 minutes of acetone → 15 minutes of pure water, a film of Mo was formed to a thickness of 40 nm as a gate electrode. The Mo film was formed by DC magnetron sputtering (sputtering conditions: DC power 380 W, sputtering gas Ar = 13 sccm, pressure 0.4 Pa, 144 sec). Patterning was performed by photolithography + etching.

Next, the following gate insulating film was formed on the gate electrode.
Gate insulating film: RF ₂ by RF magnetron sputtering vacuum deposition method (conditions: target SiO ₂ , film forming temperature 54 ° C., sputtering gas Ar / O ₂ = 12/2 sccm, RF power 400 W, film forming pressure 0.4 Pa, 4172 sec) And a gate insulating film was provided. The gate insulating film SiO ₂ was patterned by a lift-off method.

Next, an active layer made of IGZO was provided to a thickness of 30 nm on the gate insulating film under the following conditions.
Active layer: The target was a polycrystalline sintered body having a composition of InGaZnO ₄ , and was performed by RF magnetron sputtering under the conditions of Ar flow rate 97 sccm, O ₂ flow rate 1.5 sccm, RF power 200 W, pressure 0.4 Pa, 432 sec. .

Next, a resistance layer made of IGZO was provided on the active layer to a thickness of 40 nm under the following conditions.
Resistance layer: A polycrystalline sintered body having a composition of InGaZnO ₄ was used as a target, and was performed by RF magnetron sputtering under the conditions of Ar flow rate 13 sccm, O ₂ flow rate 1.5 sccm, RF power 200 W, pressure 0.4 Pa, 720 sec. .

  Next, ITO is used as a source electrode and a drain electrode on the resistance layer to a thickness of 40 nm by RF magnetron sputtering (conditions: film formation temperature 43 ° C., sputtering gas Ar = 13 sccm, RF power 40 W, film formation pressure 0.4 Pa, 1573 sec). The patterning of the source electrode and the drain electrode was performed by a lift-off method.

2) Fabrication of TFT subjected to resistance reduction treatment This is a fabrication example of a TFT having the configuration shown in FIG.
In the fabrication of the above-mentioned reference TFT element, a resist pattern is formed by a photolithography method after the resistance layer is installed and before the source electrode and the drain electrode are installed, and the resist pattern is formed in the region where the source electrode and the drain electrode are installed. A resistance treatment process was performed.
The width of the resistance layer protected by the resist was 5 μm narrower than the gate insulating film (d, d ′ = 5 μm) so that the TFT had a channel length of 200 μm and a channel width of 1000 μm.

<Resistance treatment conditions>
A) UV ozone treatment Conditions: UV ozone irradiation was performed at an intensity of 60 mW / cm ² .
B) _{O 2} plasma treatment _conditions: O 2 0.2 sccm, the _{O 2} plasma treatment under conditions of RF power 50W was carried out.

  The change in electrical conductivity of the resistance layer due to the low resistance treatment was obtained by preparing a measurement sample in which only the resistance layer was provided on the substrate and performing the resistance treatment process under the same conditions as in the TFT device production. It measured about the sample, calculated from the obtained value, and substituted with the electrical conductivity of the resistance layer.

-Measuring method of electrical conductivity-
The electrical conductivity of the sample for measuring physical properties was calculated from the measured sheet resistance and film thickness of the sample. Here, when the sheet resistance is ρ (Ω / □) and the film thickness is d (cm), the electrical conductivity σ (Scm ⁻¹ ) is calculated as σ = 1 / (ρ * d).
In this example, (manufactured by Mitsubishi Chemical Corporation) Loresta -GP in sheet resistance 10 ⁷ Ω / □ of less than area of the sample for measuring physical properties, high tester -UP (manufactured by Mitsubishi Chemical Corporation in sheet resistance 10 ⁷ Ω / □ or more regions ) In an environment of 20 ° C. A stylus type surface shape measuring device DekTak-6M (manufactured by ULVAC) was used for measuring the film thickness of the sample for measuring physical properties.

The relationship between the obtained UV ozone treatment and O ₂ plasma treatment time and electric conductivity is shown in FIGS. By the UV ozone treatment step, the electrical conductivity increased from 2.8 × 10 ⁻¹⁰ Scm ⁻¹ with the irradiation time, and increased to 8.0 × 10 ⁻⁵ Scm ^{−1 in} 30 minutes. On the other hand, the electrical conductivity increased from 2.8 × 10 ⁻¹⁰ Scm ⁻¹ with the irradiation time by the O ₂ plasma treatment step, and increased to 3.6 × 10 ⁰ Scm ^{−1 in} 7 minutes.
From the above, it can be seen that the electrical conductivity can be increased to a desired value by changing the treatment conditions of the UV ozone treatment and the O ₂ plasma treatment time.

Similarly, the electrical conductivity of the active layer was measured and found to be 1.0 × 10 ⁻⁴ Scm ⁻¹ .

  The TFT element 1 of the present invention has the above-mentioned experiment No. 1. The resistance reduction treatment was performed under the condition 1, that is, UV ozone for 5 minutes. Other steps were performed in exactly the same manner as the fabrication of the comparative TFT element A.

2. Performance Evaluation With respect to each of the obtained TFT elements, the TFT transfer characteristics were measured at a saturation region drain voltage Vd = + 40 V (gate voltage (Vg): −20 V ≦ Vg ≦ + 40 V) with the source electrode set to 0 (zero) V. The performance of the TFT was evaluated. The measurement of TFT transfer characteristics was performed using a semiconductor parameter analyzer 4156C (manufactured by Agilent Technologies).

  FIG. 18 is a current-voltage characteristic curve showing TFT transfer characteristics of the device of Comparative A and the device 1 of the present invention. The horizontal axis represents the gate voltage Vg, and the vertical axis represents the drain current Id.

-ON / OFF ratio calculation method-
The ON / OFF ratio was determined from the ratio Id _max / Id _min between the maximum value Id _max and the minimum value Id _min in the drain current Id from the TFT transfer characteristics.

Table 2 shows the TFT characteristics obtained from the measurement results of the TFT transfer characteristics shown in FIG. From the results shown in Table 2, the element 1 of the present invention showed excellent performance with a high ON / OFF ratio.
On the other hand, the comparative element A having a low resistance electrical conductivity did not operate as a TFT.

As is clear from the above, a resistance layer having a low electrical conductivity is provided on the active layer, and then a resistance reduction treatment is performed on a portion connected to the source electrode and the drain electrode, so that the active layer is connected to the source electrode and the drain electrode. It has been found that the contact resistance is low, the TFT characteristics are good, and the ON / OFF ratio is high. Further, the electrical conductivity of the resistance layer obtained here is on the order of 10 ⁻⁶ , and as shown in Table 1, the electrical conductivity can be made 10 ⁻⁶ or more in the processing time or the like. The resistance can be further reduced.

Example 2
Similar to the fabrication of the device 1 of the present invention, except that the gate electrode and the unreduced resistance region were made the same in width, and the TFT device 2 having a configuration in which the gate electrode and the unreduced resistance region overlapped was fabricated. (Configuration shown in FIG. 14).
Further, as in the manufacture of the element 1 of the present invention, a comparative TFT element having a configuration in which the width of the non-low resistance region is wider than the width of the gate electrode, and the non-low resistance region protrudes from the gate electrode region. B was produced (configuration shown in FIG. 15).
As a result of evaluating the TFT performance of the obtained device in the same manner as in Example 1, the device 2 of the present invention had a high ON / OFF ratio and showed excellent performance, but the comparative device B had a low ON current, The result was a low ON / OFF ratio.

It is a schematic diagram which shows the TFT element structure of this invention. The manufacturing order of the TFT element of the present invention is shown in FIGS. FIG. 2 shows a substrate. It is a formation process of a gate electrode. This is a step of forming a gate insulating film. This is a process of forming an active layer. It is a formation process of a resistance layer. This is a low resistance treatment process. This is the configuration after the low resistance treatment. This is a process of forming a source electrode and a drain electrode. A manufacturing method of a TFT device according to another aspect of the present invention is shown in FIGS. FIG. 10 shows a process for reducing resistance. This is the configuration after the low resistance treatment. This is a process of forming a source electrode and a drain electrode. It is the structure after a lift-off process. It is a schematic diagram which shows the TFT element structure of another aspect of this invention. It is a schematic diagram which shows the comparative TFT element structure. It is experimental data which shows the relationship between the resistance reduction process conditions by a UV irradiation method, and electrical resistance. Is data showing the relationship between resistance reduction processing conditions and the electrical resistance due to O ₂ plasma process. It is a schematic diagram of the graph which shows how to obtain | require the threshold voltage (Vth) of TFT in performance evaluation. The horizontal axis represents the gate voltage (Vg), and the vertical axis represents Isd (source-drain current).

Claims (9)

At least on an insulating substrate,
(1) forming a gate electrode;
(2) forming a gate insulating film by covering the gate electrode;
(3) forming an active layer made of an oxide semiconductor in contact with the gate insulating film;
(4) A step of forming a resistance layer in contact with the active layer and having an electrical conductivity of 10 ⁻⁹ Scm ⁻¹ or less made of an oxide semiconductor having a lower electrical conductivity than the active layer,
(5) At least a predetermined interval is separated by subjecting a part of the resistance layer to a low resistance treatment such as a UV ozone treatment or a plasma treatment with oxygen so that the electric conductivity becomes 10 ⁻⁸ Scm ⁻¹ or more. A low-resistance treatment step for forming two low-resistance regions, and a region between the two low-resistance regions that has not been subjected to the low-resistance treatment (non-low-resistance region) is A thin film electric field comprising a source / drain electrode forming step formed inside the gate electrode and (6) forming a source electrode in contact with one of the two low resistance regions and a drain electrode in contact with the other Method for producing effect transistor. ^{2. The} method of manufacturing a thin film field effect transistor according to claim 1, wherein the electric conductivity of the active layer is 10 ⁻⁶ Scm ⁻¹ or more and less than 10 ² Scm ⁻¹ . Method of manufacturing a thin film field effect transistor according to claim 1 or claim 2 the thickness of the resistive layer is equal to or greater than the thickness of the active layer. The method for manufacturing a thin film field effect transistor according to any one of claims 1 to 3 , wherein the oxide semiconductor of the active layer and the resistance layer is an amorphous oxide semiconductor. 5. The method of manufacturing a thin film field effect transistor according to claim 4 , wherein the oxygen concentration of the active layer is lower than the oxygen concentration of the resistance layer. Wherein the oxide semiconductor is In, at least one or the method of manufacturing a thin film field effect transistor according to claim 4 or claim 5, characterized in that it comprises a composite oxide thereof selected from the group consisting of Ga and Zn . The oxide semiconductor contains the In and Zn, and the composition ratio of Zn and In (represented by the ratio of Zn to In, Zn / In) of the resistance layer is larger than the composition ratio Zn / In of the active layer A method for manufacturing a thin film field effect transistor according to claim 6 . Method of manufacturing a thin film field effect transistor according to any one of claims 1 to 7, wherein the substrate is a flexible resin substrate. The thin film field effect transistor manufactured by the manufacturing method of any one of Claims 1-8 .