JP7079307B2 - Display device - Google Patents

Description

The present invention relates to a semiconductor device using an oxide semiconductor.

In the present specification, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics, and the electro-optical device such as a liquid crystal display device, the semiconductor circuit, and the electronic device are all semiconductor devices.

In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (thickness of several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as integrated circuits (ICs) and electro-optical devices, and their development is urgently needed as a switching element for image display devices. Metal oxides exist in various ways and are used for various purposes. Indium oxide is a well-known material and is used as a transparent electrode material required for liquid crystal displays and the like.

Some metal oxides exhibit semiconductor properties. Examples of the metal oxide exhibiting semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, and the like, and a thin film having a metal oxide exhibiting such semiconductor characteristics as a channel forming region is already known. (Patent Document 1 and Patent Document 2).

Japanese Unexamined Patent Publication No. 2007-123861 Japanese Unexamined Patent Publication No. 2007-96055

A thin film transistor using an oxide semiconductor layer is required to have a high operating speed, a relatively simple manufacturing process, and sufficient reliability.

One of the issues is to improve the operating characteristics and reliability of a thin film transistor using an oxide semiconductor layer.

In particular, the operating speed of the thin film transistor used in the drive circuit is preferably high.

For example, if the channel length (L) of the thin film transistor is shortened or the channel width (W) is widened, the operating speed is increased. However, if the channel length is shortened, there is a problem that the switching characteristic, for example, the on / off ratio becomes small. Further, if the channel width (W) is widened, there is a problem that the capacitive load of the thin film transistor itself is increased.

Another issue is to provide a semiconductor device provided with a thin film transistor having stable electrical characteristics even if the channel length is short.

Further, when a plurality of different circuits are formed on the insulating surface, for example, when the pixel portion and the drive circuit are formed on the same substrate, the thin film transistor used for the pixel portion has excellent switching characteristics, for example, a large on / off ratio. This is required, and the thin film transistor used in the drive circuit is required to have a high operating speed. In particular, the higher the definition of the display device, the higher the definition.
Since the writing time of the display image is shortened, it is preferable that the thin film transistor used in the drive circuit has a high operating speed.

One of the issues is to reduce the variation in the electrical characteristics of the thin film transistor using the oxide semiconductor layer.

One of the issues is to simplify the process of manufacturing a thin film transistor using an oxide semiconductor layer.

One aspect of the present invention has a drive circuit unit and a display unit (also referred to as a pixel unit) on the same substrate, and the drive circuit unit and the display unit include a semiconductor film and a first wiring (terminal or connection electrode). Also referred to as) and a second wiring (also referred to as a terminal or connection electrode), the semiconductor is a gate electrode made of metal, a gate insulating layer on the gate electrode, and oxidation on the gate insulating layer. A source electrode (also referred to as a source electrode layer) and a drain electrode (also referred to as a drain electrode layer), which are composed of a physical semiconductor layer and a metal on the oxide semiconductor layer and whose peripheral edge is located inside the peripheral edge of the oxide semiconductor layer. The thin film of the drive circuit unit has a conductive layer at a position overlapping the oxide semiconductor layer on the protective insulating layer. The thin film of the display unit is electrically connected to the pixel electrode (also called the pixel electrode layer), the first wiring is made of the same material as the gate electrode, and the second wiring is made of the same material as the source electrode or drain electrode. The first wiring and the second wiring formed are semiconductor devices that are electrically connected through openings (contact holes) provided in the gate insulating layer and the protective insulating layer.

As the thin film transistor for pixels and the thin film transistor for the drive circuit, an inverted staggered thin film transistor having a bottom gate structure is used. The thin film transistor for pixels and the thin film transistor for drive circuits are channel-etched thin film transistors provided with an oxide insulating layer in contact with the exposed oxide semiconductor layer between the source electrode layer and the drain electrode layer.

The thin film transistor for a drive circuit has a configuration in which an oxide semiconductor layer is sandwiched between a gate electrode and a conductive layer. As a result, it is possible to reduce the threshold variation of the thin film transistor, and it is possible to provide a semiconductor device provided with the thin film transistor having stable electrical characteristics. The conductive layer may have the same potential as the gate electrode layer, may be a floating potential, or may be a fixed potential, for example, a GND potential or 0V. Further, the threshold value of the thin film transistor can be controlled by applying an arbitrary potential to the conductive layer.

One aspect of the present invention for realizing the above structure is a first aspect in which a drive circuit unit on the same substrate is formed.
In the region of 1 and the second region where the display unit is formed, a first electrode functioning as a gate electrode by the first photolithography step and a first wiring made of the same material as the first electrode are formed. , A first insulating film functioning as a gate insulating layer is formed on the first electrode and the first wiring, an oxide semiconductor layer is formed on the first insulating film, and the oxide semiconductor layer is dehydrated. Heat treatment for conversion or dehydrogenation is performed to form a metal film for forming a source electrode and a drain electrode on the oxide semiconductor layer, and a second photolithography step is performed on the metal film for multi-gradation. A resist mask having regions with different film thicknesses is formed using a mask, and the oxide semiconductor layer and the metal film are etched using the resist mask having regions with different film thicknesses as a mask layer to form an island-shaped oxide semiconductor layer and islands. It is processed into a metal layer in the shape of a semiconductor, the mask layer is ashed to shrink the mask layer, and at the same time, the resist mask in the thin region is removed to form a separated mask layer, and the exposed portion of the metal layer is formed. A second electrode functioning as a source electrode, a third electrode functioning as a drain electrode, and a source electrode or a drain electrode having a shape in which the peripheral edge portion is recessed inward from the peripheral edge portion of the oxide semiconductor layer by etching. A second wiring made of the same material as the above is formed, the mask layer is removed, and a second insulating film, which is an oxide insulating layer, is formed on the second electrode, the third electrode, and the oxide semiconductor layer. Then, the first insulating film and the second insulating film overlapping with the first wiring are selectively removed by the third photolithography step to form the first opening, and the second insulating film overlaps with the second wiring. The insulating film is selectively removed to form a second opening, and the second insulating film is selectively placed at a position overlapping either the second electrode or the third electrode in the second region. By removing it, a third opening is formed, and a first conductive layer that electrically connects the first wiring and the second wiring through the first opening and the second opening by the fourth photolithography step is formed. A fourth electrode made of the same material as the first conductive layer is formed at a position overlapping the oxide semiconductor layer via the second insulating film in the first region, and the second electrode is formed in the second region. It is a method for manufacturing a semiconductor device characterized by forming a fifth electrode which is made of the same material as the first conductive layer electrically connected to the thin film through the opening of 3 and functions as a pixel electrode.

The number of photomasks can be reduced and the process can be simplified.

Since the mask layer formed by using the multi-gradation mask has a shape having a plurality of film thicknesses and the shape can be further deformed by etching the mask layer, a plurality of etching steps for processing into different patterns. Can be used for. Therefore, one multi-tone mask can form a mask layer corresponding to at least two or more different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced, so that the process can be simplified.

The above configuration solves at least one of the above problems.

Further, the oxide semiconductor used in the present specification is, for example, InMO ₃ (ZnO) _m (m> 0).
A thin film indicated by is formed, and the thin film is used as an oxide semiconductor layer to produce a thin film transistor. In addition, M represents one metal element selected from Ga, Fe, Ni, Mn and Co, or a plurality of metal elements. For example, M may be Ga, or may contain the above metal elements other than Ga, such as Ga and Ni or Ga and Fe. Further, in the oxide semiconductor, in addition to the metal element contained as M, Fe, Ni and other transition metal elements, or an oxide of the transition metal is contained as an impurity element. In the present specification, among the oxide semiconductor layers having a structure represented by InMO ₃ (ZnO) _m (m> 0), an oxide semiconductor having a structure containing Ga as M is oxidized by In—Ga—Zn—O system. It is called a physical semiconductor, and its thin film is also called an In-Ga-Zn-O-based non-single crystal film.

In addition to the above, In—Sn—Zn—O can be used as a metal oxide applied to the oxide semiconductor layer.
System, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn
-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-
O-based, Sn—O-based, and Zn—O-based metal oxides can be applied. Further, silicon oxide may be contained in the oxide semiconductor layer made of the metal oxide.

When heat treatment is performed in an inert gas atmosphere of nitrogen or a rare gas (argon, helium, etc.), the oxide semiconductor layer becomes oxygen-deficient due to the heat treatment, resulting in low resistance, that is, N-type (N-type).
The resistance of the oxide semiconductor layer is increased by forming an oxide insulating layer in contact with the oxide semiconductor layer and then heat ^- treating the oxide semiconductor layer in an oxygen-excessive state.
It can be said that it is typed. It can also be said that solid-phase oxidation is performed to make the oxide semiconductor layer in an oxygen-excessive state. This makes it possible to manufacture and provide a semiconductor device having a thin film transistor having good electrical characteristics and high reliability.

Dehydration or dehydrogenation is carried out by heat treatment at 400 ° C. or higher and below the strain point of the substrate, preferably 420 ° C. or higher and 570 ° C. or lower, in an inert gas atmosphere of nitrogen or a rare gas (argon, helium, etc.). It reduces impurities such as water contained in the oxide semiconductor layer. Also, the water after that (
It is possible to prevent re-impregnation of _H2O ).

The heat treatment for dehydration or dehydrogenation is preferably performed in a nitrogen atmosphere having _H2O of 20 ppm or less. Further, it may be carried out in ultra-dry air having _H2O of 20 ppm or less.

The dehydrogenated or dehydrogenated oxide semiconductor layer has two peaks of water, at least 300, even when measured up to 450 ° C. with TDS for the dehydrogenated or dehydrogenated oxide semiconductor layer.
The heat treatment condition is such that one peak appearing near ° C is not detected. Therefore, for a thin film transistor using a dehydrated or dehydrogenated oxide semiconductor layer, the TDS is 45.
Even if the measurement is performed up to 0 ° C, the peak of water appearing at least around 300 ° C is not detected.

Then, when the temperature is lowered from the heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated, water or hydrogen is not exposed to the atmosphere using the same furnace that has been dehydrated or dehydrogenated. It is important not to mix again. A thin film transistor is manufactured using an oxide semiconductor layer that has been dehydrated or dehydrogenated to reduce the resistance of the oxide semiconductor layer, that is, to make it N-type (N- ^, etc.), and then to increase the resistance to form an I-type. Then, the threshold voltage value of the thin film transistor can be made positive, and a so-called normally-off switching element can be realized. It is desirable for a semiconductor device (display device) that a channel is formed with a positive threshold voltage at which the gate voltage of the thin film transistor is as close as possible to 0V. If the threshold voltage value of the thin film transistor is negative, a current flows between the source electrode and the drain electrode even if the gate voltage is 0 V, which tends to be so-called normally-on. In the active matrix type display device,
The electrical characteristics of the thin film transistors that make up the circuit are important, and these electrical characteristics affect the performance of the display device. In particular, the threshold voltage (Vth) is important among the electrical characteristics of the thin film transistor. Even if the field effect mobility is high, if the threshold voltage value is high or the threshold voltage value is negative, it is difficult to control the circuit. In the case of a thin film transistor having a high threshold voltage value and a large absolute value of the threshold voltage, the switching function as a TFT cannot be fulfilled when the drive voltage is low, which may result in a load. In the case of an n-channel thin film transistor, a transistor in which a channel is formed only when a positive voltage is applied to the gate voltage and a drain current flows out is desirable. A transistor in which a channel is not formed unless the drive voltage is increased, or a transistor in which a channel is formed and a drain current flows even in a negative voltage state is not suitable as a thin film transistor used in a circuit.

Further, the gas atmosphere lowered from the heating temperature T may be switched to a gas atmosphere different from the gas atmosphere raised to the heating temperature T. For example, high-purity oxygen gas or N2O gas, ultra _- dry air (dew point -40 ° C or less, preferably-preferably-) in the same dehydrogenated or dehydrogenated furnace without exposing it to the atmosphere. Fill with (60 ° C. or lower) and cool.

After reducing the water content in the membrane by heat treatment for dehydration or dehydrogenation, slow cooling (or cooling) in a water-free atmosphere (dew point -40 ° C or lower, preferably -60 ° C or lower).
The oxide semiconductor layer is used to improve the electrical characteristics of the thin film transistor and to realize a thin film transistor having both mass productivity and high performance.

In the present specification, the heat treatment of nitrogen or a rare gas (argon, helium, etc.) under an inert gas atmosphere is referred to as a heat treatment for dehydrogenation or dehydrogenation. In the present specification, dehydrogenation is not only referred to as dehydrogenation as H ₂ by this heat treatment.
, OH, etc. will be referred to as dehydration or dehydrogenation for convenience, including desorption.

When heat treatment is performed in an inert gas atmosphere of nitrogen or a rare gas (argon, helium, etc.), the oxide semiconductor layer becomes oxygen-deficient due to the heat treatment, resulting in low resistance, that is, N-type (N-type).
N ^- formation, etc.).

In addition, a high resistance drain region (HRD (High), which is an oxygen-deficient type that overlaps with the drain electrode layer.
A Response Drain) region) is formed. In addition, a high resistance source region (HRS (High Resistance)) that is an oxygen-deficient type that overlaps with the source electrode layer.
The eSource) region) is formed.

Specifically, the carrier concentration in the high resistance drain region is in the range of 1 × 10 ¹⁸ / cm ³ or more, and at least in a region higher than the carrier concentration in the channel forming region (less than 1 × 10 ¹⁸ / cm ³ ). be. The carrier concentration in the present specification refers to the value of the carrier concentration obtained from the Hall effect measurement at room temperature.

Then, by making at least a part of the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excessive state, the resistance is further increased, that is, the type I is formed to form a channel forming region. As a treatment for making the dehydrated or dehydrogenated oxide semiconductor layer in an oxygen-excessive state, a film formation of an oxide insulating layer in contact with the dehydrated or dehydrogenated oxide semiconductor layer by a sputtering method is performed.
Alternatively, heat treatment after film formation of the oxide insulating layer, heat treatment in an atmosphere containing oxygen, or heating in an atmosphere of an inert gas and then cooling in an oxygen atmosphere, ultra-dry air (dew point is -40).
It is carried out by a process of cooling at ° C. or lower, preferably −60 ° C. or lower).

In addition, since at least a part of the dehydrated or dehydrogenated oxide semiconductor layer (the part overlapping the gate electrode layer) is used as the channel formation region, the oxygen is selectively excessive to increase the resistance, that is, It can also be type I. A source electrode layer or drain electrode layer made of a metal electrode such as Ti is formed in contact with a dehydrated or dehydrogenated oxide semiconductor layer, and an exposed region that does not overlap with the source electrode layer or drain electrode layer is selectively oxygenated. The channel formation region can be formed as an excessive state. When the oxygen is selectively excessive, a first high resistance source region overlapping the source electrode layer and a second high resistance drain region overlapping the drain electrode layer are formed, and the first high resistance source region and the first high resistance source region are formed. The region between the second high resistance drain region and the second high resistance drain region is the channel formation region. A channel formation region is self-aligned between the source electrode layer and the drain electrode layer.

This makes it possible to manufacture and provide a semiconductor device having a thin film transistor having good electrical characteristics and high reliability.

By forming a high resistance drain region in the oxide semiconductor layer superimposed on the drain electrode layer, it is possible to improve the reliability when the drive circuit is formed. Specifically, by forming the high resistance drain region, it is possible to form a structure in which the conductivity can be changed stepwise from the drain electrode layer to the high resistance drain region and the channel formation region. Therefore, when operating by connecting to a wiring that supplies a high power supply potential VDD to the drain electrode layer, even if a high electric field is applied between the gate electrode layer and the drain electrode layer, the high resistance drain region becomes a buffer and is localized. A high electric field is not applied, and the withstand voltage of the transistor can be improved.

Further, by forming a high resistance drain region and a high resistance source region in the oxide semiconductor layer superimposed on the drain electrode layer and the source electrode layer, the leakage current in the channel formation region when the drive circuit is formed can be reduced. Can be planned. Specifically, by forming a high resistance drain region, the drain electrode layer, the high resistance drain region on the drain electrode layer side, and the channel are used as a path for the leakage current of the transistor flowing between the drain electrode layer and the source electrode layer. The order is the formation region, the high resistance source region on the source electrode layer side, and the source electrode layer. At this time, in the channel forming region, the leakage current flowing from the high resistance drain region on the drain electrode layer side to the channel region can be concentrated near the interface between the gate insulating layer and the channel forming region, which have high resistance when the transistor is off. It is possible to reduce the leakage current in the back channel portion (a part of the surface of the channel forming region away from the gate electrode layer).

Further, the high resistance source region overlapping the source electrode layer and the high resistance drain region overlapping the drain electrode layer overlap with a part of the gate electrode layer via the gate insulating layer, depending on the width of the gate electrode layer. The electric field strength near the end of the drain electrode layer can be effectively relaxed.

Further, an oxide conductive layer may be formed between the oxide semiconductor layer and the source electrode and the drain electrode. The oxide conductive layer preferably contains zinc oxide as a component, and preferably does not contain indium oxide. For example, zinc oxide, zinc aluminum oxide, aluminum oxynitride, gallium zinc oxide and the like can be used. The oxide conductive layer has a low resistance drain region (LRN (Low Resistance N-type control).
It also functions as an ivity) area and an LRD (Low Response Drain) area). Specifically, the carrier concentration in the low resistance drain region is larger than that in the high resistance drain region (HRD region), for example, 1 × 10 ²⁰ / cm ³ or more and 1 × 10 ²¹ / c.
It is preferably within the range of m ³ or less. By providing the oxide conductive layer between the oxide semiconductor layer and the source electrode and drain electrode, contact resistance can be reduced and high-speed operation of the transistor can be realized, so that the frequency characteristics of the peripheral circuit (drive circuit) can be improved. Can be improved.

When applied to the above-mentioned manufacturing method, an oxide conductive layer may be formed after the oxide semiconductor layer is formed, and then a metal film may be formed. The formation of the oxide conductive layer may be performed before or after the heat treatment for dehydrating or dehydrogenating the oxide semiconductor layer.

The metal film for forming the oxide conductive layer and the source electrode and the drain electrode can be continuously formed.

Further, the first wiring and the second wiring described above may be laminated wiring composed of the same material and metal material as the oxide conductive layer functioning as LRN or LRD. By laminating the metal and the oxide conductive layer, it is possible to improve the covering property against steps such as overcoming of the lower layer wiring and openings, and to reduce the wiring resistance. Further, since it can be expected to have an effect of preventing local high resistance and disconnection of wiring due to migration or the like, it is possible to provide a highly reliable semiconductor device.

Further, also when connecting the first wiring and the second wiring described above, the insulating oxide is formed on the metal surface of the connecting portion (contact portion) by connecting the oxide conductive layer between them. It can be expected to prevent an increase in contact resistance (contact resistance) due to this, and it is possible to provide a highly reliable semiconductor device.

Further, since the thin film transistor is easily destroyed by static electricity or the like, it is preferable to provide a protection circuit for protecting the thin film transistor in the pixel portion on the same substrate for the gate line or the source line. The protection circuit is preferably configured by using a non-linear element using an oxide semiconductor layer.

The ordinal numbers attached as the first and second numbers are used for convenience and do not indicate the process order or the stacking order. In addition, this specification does not indicate a unique name as a matter for specifying the invention.

By using an oxide semiconductor layer, it is possible to realize a semiconductor device equipped with a thin film transistor having excellent electrical characteristics and reliability.

The figure explaining the semiconductor device. The figure explaining the manufacturing method of the semiconductor device. The figure explaining the manufacturing method of the semiconductor device. The figure explaining the manufacturing method of the semiconductor device. The figure explaining the semiconductor device. The figure explaining the manufacturing method of the semiconductor device. The figure explaining the manufacturing method of the semiconductor device. The figure explaining the semiconductor device. The figure explaining the multi-gradation mask. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the block diagram of the semiconductor device. The figure explaining the structure of the signal line drive circuit. A circuit diagram showing the configuration of a shift register. A circuit diagram and a timing chart illustrating the operation of the shift register. The figure explaining the semiconductor device. The figure explaining the semiconductor device. An external view showing an example of an electronic book. Top view showing an example of a television device and a digital photo frame. The external view which shows the example of the gaming machine. The external view which shows an example of the portable computer and the mobile phone. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device. The figure explaining the semiconductor device.

The embodiments will be described in detail with reference to the drawings. However, it is not limited to the following description, and it is easily understood by those skilled in the art that the form and details can be variously changed without departing from the purpose and scope thereof. Therefore, the interpretation is not limited to the description of the embodiments shown below. In the configuration described below, the same reference numerals are commonly used between different drawings for the same parts or parts having similar functions, and the repeated description thereof will be omitted.

(Embodiment 1)
The manufacturing process of the semiconductor device including the thin film transistor will be described with reference to FIGS. 1 to 5.

A liquid crystal display device is shown in FIG. 1 as a semiconductor device which is one embodiment of the present invention. The liquid crystal display device of FIG. 1 includes a thin film transistor 170, a pixel portion including a capacity 147, and a thin film transistor 180.
A drive circuit unit including, a pixel electrode layer 110, a substrate 100 provided with an insulating layer 191 functioning as an alignment film, an insulating layer 193 functioning as an alignment film, a counter electrode layer 194, and a colored layer 195 functioning as a color filter. The provided substrate 190 and the provided substrate 190 sandwich the liquid crystal layer 192 and face each other. Further, polarizing plates (layers having a polarizing element, also simply referred to as a polarizing element) 196a and 196b are provided on the opposite sides of the substrate 100 and the substrate 190 from the liquid crystal layer 192, respectively, and a first terminal portion of the gate wiring is provided. The terminal 121, the terminal electrode 128 for connection, and the terminal portion of the source wiring are provided with a second terminal 122 and a terminal electrode 129 for connection.

The second terminal 122 is laminated on the oxide semiconductor layer 120, and the second terminal 122 and the oxide semiconductor layer 120 are formed by a photolithography step using a resist mask formed by using a multi-gradation mask. Will be done.

In the drive circuit section, the thin film transistor 180 is provided with a conductive layer 111 above the gate electrode layer and the semiconductor layer, and the drain electrode layer 165b is electrically connected via the conductive layer 162 and the wiring layer 145 formed in the same process as the gate electrode layer. Is connected. Further, in the pixel portion, the drain electrode layer of the thin film transistor 170 is electrically connected to the pixel electrode layer 110.

In the manufacturing method, the thin film transistors 170 and 180 are subjected to an etching step using a mask layer formed by a multi-gradation mask, which is an exposure mask in which transmitted light has a plurality of intensities. Therefore, the peripheral portions of the oxide semiconductor layers 103 and 163 are the source electrode layers 105a and 165a.
, The drain electrode layers 105b and 165b are not covered and are exposed. The exposed region on the periphery of the oxide semiconductor layers 103 and 163 is a region in contact with the oxide insulating layer 107. When the oxide semiconductor layers 103 and 163 have a shape exposed on the peripheral edge, the coverage of the oxide insulating layer 107 laminated on the oxide semiconductor layers 103 is good.

Hereinafter, the production method will be described in detail with reference to FIGS. 2 to 5. 5 is a plan view of a pixel portion of a liquid crystal display device, and FIGS. 1 to 4 correspond to cross-sectional views of lines A1-A2 and B1-B2 in FIG.

After forming a conductive layer on the entire surface of the substrate 100, which is a substrate having an insulating surface, a first photolithography step is performed to form a resist mask, and unnecessary parts are removed by etching to remove wiring and electrodes. (Gate electrode layer 101, gate electrode layer 161 and conductive layer 162
, Capacitive wiring layer 108, and first terminal 121). Etching so that a tapered shape is formed at the ends of the wiring and the electrode as shown in FIG. 2A is preferable because the covering property of the film to be laminated is improved. The gate electrode layer 101 and the gate electrode layer 161 are included in the gate wiring, respectively.

There is no major limitation on the substrate that can be used for the substrate 100 having an insulating surface, but it is necessary that the substrate has at least heat resistance that can withstand the subsequent heat treatment. A glass substrate can be used for the substrate 100 having an insulating surface.

Further, as the glass substrate, when the temperature of the subsequent heat treatment is high, it is preferable to use a glass substrate having a strain point of 730 ° C. or higher. Further, for the glass substrate, for example, a glass material such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass is used. By containing a large amount of barium oxide (BaO) as compared with boric acid, more practical heat-resistant glass can be obtained. Therefore _, it is preferable to use a glass substrate containing more BaO _than B2O3.

Instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. In addition, crystallized glass or the like can be used. Since the liquid crystal display device shown in the present embodiment is a transmissive type, a translucent substrate is used as the substrate 100, but in the case of the reflective type, a nontranslucent metal substrate or the like is used as the substrate 100. You may use it.

The insulating film to be the base film is the substrate 100, the gate electrode layer 101, the gate electrode layer 161 and the conductive layer 1.
It may be provided between 62, the capacitive wiring layer 108, and the first terminal 121. The undercoat has a function of preventing the diffusion of impurity elements from the substrate 100, and has a laminated structure consisting of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon nitride film, or a silicon oxide film. Can be formed.

Gate electrode layer 101, gate electrode layer 161, conductive layer 162, capacitive wiring layer 108, and first
The material of the terminal 121 is formed in a single layer or laminated by using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium or an alloy material containing these as the main components. be able to.

For example, the gate electrode layer 101, the gate electrode layer 161 and the conductive layer 162, the capacitive wiring layer 108,
The two-layer laminated structure of the first terminal 121 is a two-layer laminated structure in which a molybdenum layer is laminated on an aluminum layer, a two-layer structure in which a molybdenum layer is laminated on a copper layer, or a copper layer. It is preferable to have a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are laminated. The three-layer laminated structure is preferably a laminate in which a tungsten layer or a tungsten nitride layer, an aluminum-silicon alloy layer or an aluminum-titanium alloy layer, and a titanium nitride layer or a titanium layer are laminated.

Next, the gate electrode layer 101, the gate electrode layer 161 and the conductive layer 162, the capacitive wiring layer 108,
And the gate insulating layer 102 is formed on the first terminal 121.

The gate insulating layer 102 is formed by using a plasma CVD method, a sputtering method, or the like to form a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, a silicon nitride oxide layer, or an aluminum oxide layer as a single layer or laminated. Can be done. For example, a silicon oxynitride layer may be formed by a plasma CVD method using SiH ₄ , oxygen and nitrogen as the film forming gas. The film thickness of the gate insulating layer 102 is 100 nm or more and 500 nm or less, and in the case of lamination, for example, the film thickness is 50 nm or more 2
On the first gate insulating layer of 00 nm or less and the first gate insulating layer, the film thickness is 5 nm or more and 300 n.
The second gate insulating layer of m or less is laminated.

In the present embodiment, the gate insulating layer 102 having a film thickness of 200 nm or less, which is a silicon nitride layer, is formed by the plasma CVD method.

Next, the oxide semiconductor layer 130 is formed on the gate insulating layer 102.

Before forming the oxide semiconductor layer by the sputtering method, it is preferable to perform reverse sputtering in which argon gas is introduced to generate plasma to remove dust adhering to the surface of the gate insulating layer 102. Reverse sputtering is a method of applying a voltage to the substrate side using an RF power supply in an argon atmosphere to form plasma in the vicinity of the substrate and modify the surface. In addition, nitrogen, helium or the like may be used instead of the argon atmosphere. Further, it may be performed in an atmosphere in which oxygen, _N2O , or the like is added to an argon atmosphere. Also, Cl in an argon atmosphere
_2. It may be performed in an atmosphere in which CF ₄ or the like is added.

Next, the oxide semiconductor layer 13 having a film thickness of 2 nm or more and 200 nm or less is placed on the gate insulating layer 102.
Form 0 (see FIG. 2 (A)). Even if heat treatment for dehydrogenation or dehydrogenation is performed after the formation of the oxide semiconductor layer 130, the oxide semiconductor layer is in an amorphous state, so the film thickness is 50.
It is preferable to make it as thin as nm or less. By reducing the film thickness of the oxide semiconductor layer, it is possible to suppress crystallization when heat treatment is performed after the formation of the oxide semiconductor layer.

The oxide semiconductor layer 130 includes an In—Ga—Zn—O system non-single crystal film, an In—Sn—Zn—O system, an In—Al—Zn—O system, a Sn—Ga—Zn—O system, and Al—Ga. -Zn-O system, Sn-
Al-Zn-O system, In-Zn-O system, In-Ga-O system, Sn-Zn-O system, Al-Z
An n—O system, In—O system, Sn—O system, and Zn—O system oxide semiconductor layer is used. In the present embodiment, a film is formed by a sputtering method using an In—Ga—Zn—O-based oxide semiconductor target. Further, the oxide semiconductor layer 130 is placed under a noble gas (typically argon) atmosphere.
It can be formed by a sputtering method under an oxygen atmosphere or a noble gas (typically argon) and an oxygen atmosphere. When the sputtering method is used, a film is formed using a target containing SiO ₂ in an amount of 2% by weight or more and 10% by weight or less, and the oxide semiconductor layer 130 is formed.
It is preferable to contain SiOx (X> 0) that inhibits crystallization to prevent crystallization during the heat treatment for dehydration or dehydrogenation performed in a later step.

Here, an oxide semiconductor target containing In, Ga, and Zn (In ₂ O ₃ : Ga ₂ O).
₃ : ZnO = 1: 1: 1 [mol%], In: Ga: Zn = 1: 1: 0.5 [at%])
The distance between the substrate and the target is 100 mm, the pressure is 0.2 Pa, and the direct current (DC) is used.
The film is formed under the atmosphere of a power source of 0.5 kW, argon and oxygen (argon: oxygen = 30 sccm: 20 sccm oxygen flow rate ratio 40%). It is preferable to use a pulsed direct current (DC) power source because dust can be reduced and the film thickness distribution becomes uniform. The film thickness of the In—Ga—Zn—O-based non-single crystal film shall be 5 nm or more and 200 nm or less. In the present embodiment, an In—Ga—Zn—O non-single crystal film having a film thickness of 20 nm is formed as the oxide semiconductor layer by a sputtering method using an In—Ga—Zn—O oxide semiconductor target. ..

The sputtering method includes an RF sputtering method in which a high frequency power source is used as a power source for sputtering, a DC sputtering method, and a pulse DC sputtering method in which a pulse bias is applied. The RF sputtering method is mainly used for forming an insulating film, and is DC.
The sputtering method is mainly used when forming a metal film.

There is also a multi-dimensional sputtering device that can install multiple targets made of different materials. The multi-dimensional sputtering device can form a laminated film of different material films in the same chamber, or can simultaneously discharge a plurality of types of materials in the same chamber to form a film.

In addition, a sputtering device using a magnetron sputtering method equipped with a magnet mechanism inside the chamber, or a plasma generated by microwaves without using glow discharge is used.
There is a sputtering device that uses the CR sputtering method.

Further, as a film forming method using a sputtering method, a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted to form a thin film of a compound thereof during the film forming, or a voltage is applied to a substrate during the film forming. There is also a bias sputtering method.

A resist pattern may be formed directly on the gate insulating layer to open a contact hole. In that case, it is preferable to perform heat treatment after peeling off the resist to dehydrate, dehydrogenate, and dehydroxylize the surface of the gate insulating layer. For example, heat treatment (400 ° C or higher and less than the strain point of the substrate) is performed under an inert gas atmosphere (nitrogen, helium, neon, argon, etc.) and an oxygen atmosphere to remove hydrogen and water contained in the gate insulating layer. All you have to do is remove the impurities.

Next, the oxide semiconductor layer 130 is dehydrated or dehydrogenated to form the dehydrated or dehydrogenated oxide semiconductor layer 131 (see FIG. 2B). The temperature of the first heat treatment for dehydration or dehydrogenation is 400 ° C. or higher and lower than the strain point of the substrate, preferably 425 ° C. or higher. If the temperature is 425 ° C. or higher, the heat treatment time may be 1 hour or less, but if the temperature is lower than 425 ° C., the heat treatment time is longer than 1 hour. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor layer 130 is heat-treated in a nitrogen atmosphere, and then the oxide semiconductor layer is transferred to the oxide semiconductor layer without touching the atmosphere. The oxide semiconductor layer 131 is obtained by preventing the re-mixing of water and hydrogen. In the present embodiment, the same furnace is used from the heating temperature T for dehydrating or dehydrogenating the oxide semiconductor layer 130 to a sufficient temperature at which water does not enter again, specifically, higher than the heating temperature T. Slowly cool in a nitrogen atmosphere until the temperature drops to 100 ° C or higher. again,
Dehydrogenation or dehydrogenation is performed under a noble gas atmosphere such as helium, neon, or argon or under reduced pressure without being limited to a nitrogen atmosphere.

By heat-treating the oxide semiconductor layer 130 at a temperature of 400 ° C to 700 ° C, the oxide semiconductor layer 130 can be dehydrated and dehydrogenated, and subsequent re-impregnation of water ( _H2O ) can be prevented. can.

In the first heat treatment, it is preferable that nitrogen, a rare gas such as helium, neon, or argon does not contain water, hydrogen, or the like. Especially for the oxide semiconductor layer 130, 4
The heat treatment for dehydration and dehydrogenation performed at 00 ° C. to 700 ° C. is preferably performed in a nitrogen atmosphere having _H2O of 20 ppm or less. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon to be introduced into the heat treatment apparatus is 6N (99.99999%) or more, preferably 7.
N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 p)
It is preferably pm or less).

Further, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, it may be crystallized to become a microcrystalline film or a polycrystalline film.

In the heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer, after the oxide semiconductor layer is formed, the source electrode layer and the drain electrode layer are laminated on the oxide semiconductor layer, and then the source electrode layer and the drain electrode layer are subjected to the heat treatment. After forming the passivation film, it may be carried out by any of.

Next, a metal conductive layer 137 made of a metal material is formed on the oxide semiconductor layer 131 by a sputtering method or a vacuum vapor deposition method (see FIG. 2C).

Examples of the material of the metal conductive layer 137 include an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, an alloy containing the above-mentioned elements as a component, an alloy film in which the above-mentioned elements are combined, and the like. Be done. Further, the metal conductive layer may have a single-layer structure or a laminated structure of two or more layers.
For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a Ti film and an aluminum film laminated on the Ti film, and a Ti film is further formed on the Ti film. Examples thereof include a three-layer structure with a film. In addition, titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (N) are added to Al.
d), an alloy film in which a single element selected from scandium (Sc) or a combination of a plurality of elements may be used, or a nitride film of any of these elements may be used.

When the heat treatment is performed after the metal conductive layer 137 is formed, it is preferable that the metal conductive layer has heat resistance to withstand this heat treatment.

A second photolithography step is performed to form resist masks 135a, 135b, 135c on the gate insulating layer 102, the oxide semiconductor layer 131, and the metal conductive layer 137.

In this embodiment, an example of performing exposure using a high gradation mask to form the resist masks 135a, 135b, 135c is shown. A resist is formed to form the resist masks 135a, 135b, 135c. As the resist, a positive resist or a negative resist can be used. Here, a positive resist is used. The resist may be formed by a spin coating method or may be selectively formed by an inkjet method. When the resist is selectively formed by the inkjet method, it is possible to reduce the formation of the resist in unnecessary portions, so that the waste of the material can be reduced.

Next, using the multi-gradation mask 81a or 81b as the exposure mask, the resist is irradiated with light to expose the resist.

Here, the exposure using the multi-gradation masks 81a and 81b will be described with reference to FIG.

The multi-gradation mask is a mask capable of applying three exposure levels to an exposed portion, an intermediate exposed portion, and an unexposed portion, and is an exposure mask in which transmitted light has a plurality of intensities. It is possible to form a resist mask having a plurality of (typically two types) thick regions by a single exposure and development step. Therefore, it is possible to reduce the number of exposure masks by using the multi-gradation mask.

Typical examples of the multi-gradation mask include a gray tone mask 81a as shown in FIG. 9A and a halftone mask 81b as shown in FIG. 9C.

As shown in FIG. 9A, the gray tone mask 81a is composed of a translucent substrate 83, a light-shielding portion 84 formed on the transparent substrate 83, and a diffraction grating 85. In the light-shielding portion 84, the light transmittance is 0%. On the other hand, in the diffraction grating 85, the light transmittance can be controlled by setting the distance between the light transmitting portions such as slits, dots, and mesh to be equal to or less than the resolution limit of the light used for exposure. As the diffraction grating 85, either a periodic slit, a dot, or a mesh, or an aperiodic slit, a dot, or a mesh can be used.

As the translucent substrate 83, a translucent substrate such as quartz can be used. The light-shielding portion 84 and the diffraction grating 85 can be formed by using a light-shielding material such as chromium or chromium oxide that absorbs light.

When the gray tone mask 81a is irradiated with the exposure light, as shown in FIG. 9B, the light-shielding portion 8
In No. 4, the light transmittance 86 is 0%, and the light transmittance 86 is 100% in the region where the light-shielding portion 84 and the diffraction grating 85 are not provided. Further, in the diffraction grating 85, 10 to 7
The light transmittance can be adjusted in the range of 0%. The light transmittance of the diffraction grating 85 can be adjusted by adjusting the spacing and pitch of the slits, dots, or meshes of the diffraction grating.

As shown in FIG. 9C, the halftone mask 81b is composed of a translucent substrate 83, a semi-transmissive portion 87 formed on the translucent substrate 83, and a light-shielding portion 88. The semi-transmissive portion 87 includes MoSiN and M.
oSi, MoSiO, MoSiON, CrSi and the like can be used. The light-shielding portion 88 can be formed by using a light-shielding material such as chromium or chromium oxide that absorbs light.

When the halftone mask 81b is irradiated with the exposure light, as shown in FIG. 9D, the light-shielding portion 8
In No. 8, the light transmittance 89 is 0%, and the light transmittance 89 is 100% in the region where the light-shielding portion 88 and the semi-transmissive portion 87 are not provided. Further, in the semi-transmissive portion 87, 10 to 7
It can be adjusted in the range of 0%. The light transmittance in the semi-transmissive portion 87 can be adjusted by the material of the semi-transmissive portion 87.

By developing after exposure using a multi-gradation mask, resist masks 135a, 135b, 135c having regions having different film thicknesses can be formed as shown in FIG. 3 (A).

Next, the first etching step is performed using the resist masks 135a, 135b, and 135c, and the oxide semiconductor layer 131 and the metal conductive layer 137 are etched and processed into an island shape. As a result, the oxide semiconductor layers 133, 134, 120 and the metal conductive layers 185, 186, and 188 can be formed (see FIG. 3A).

Next, the resist masks 135a, 135b and 135c are ashed. As a result, the area (volume when viewed three-dimensionally) of the resist mask is reduced, and the thickness is reduced. At this time, the resist of the resist mask (the region overlapping with a part of the gate electrode layer 161) in the region having a thin film thickness is removed, and the separated resist masks 136a and 136b can be formed. Similarly, the resist masks 135b and 135c are also ashed, and the area (volume when viewed three-dimensionally) of the resist mask is reduced to become the resist masks 136c, 136d and 136e.

Using a resist mask 136a, 136b, 136c, 136d, 136e, unnecessary portions are removed by etching to form a source electrode layer 165a, a drain electrode layer 165b, a source electrode layer 105a, a drain electrode layer 105b, and a second terminal 122. Form (see FIG. 3B).

The respective materials and etching conditions are appropriately adjusted so that the oxide semiconductor layers 133 and 134 are not removed when the metal conductive layer is etched.

In this embodiment, a Ti film is used as the metal conductive layer, an In—Ga—Zn—O-based oxide is used for the oxide semiconductor layers 133 and 134, and hydrogen peroxide water (ammonia, water, A mixture of hydrogen peroxide solution) is used.

In this second photolithography step, the oxide semiconductor layer 120 and the source electrode layer 10
Second terminal 122 which is the same material as 5a, 165a and drain electrode layers 105b, 165b
Is formed on the terminal part. The second terminal 122 has source wiring (source electrode layer 105a, 1).
It is electrically connected to the source wiring including 65a).

The etching of the metal conductive layer, the oxide semiconductor layer, and the insulating film here is not limited to wet etching, and dry etching may be used.

The etching gas used for dry etching includes chlorine-containing gas (chlorine-based gas, for example, chlorine (Cl ₂ ), boron chloride (BCl ₃ ), silicon chloride (SiCl ₄ ), carbon tetrachloride (CC).
l ₄ ) etc.) is preferable.

In addition, a gas containing fluorine (fluorine-based gas, for example, carbon tetrafluoride (CF ₄ ), sulfur fluoride (SF).
₆ ), nitrogen fluoride (NF ₃ ), trifluoromethane (CHF ₃ ), etc.), hydrogen bromide (HBr)
), Oxygen (O ₂ ), a gas obtained by adding a rare gas such as helium (He) or argon (Ar) to these gases, or the like can be used.

As a dry etching method, a parallel plate type RIE (Reactive Ion Etch) is used.
The ing) method and the ICP (Inductively Coupled Plasma) etching method can be used. Etching conditions (the amount of electric power applied to the coil-type electrode, the amount of electric power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) are appropriately adjusted so that the etching can be performed into a desired processing shape.

As the etching solution used for wet etching, a solution in which phosphoric acid, acetic acid and nitric acid are mixed, ammonia superwater (31 wt% hydrogen peroxide solution: 28 wt% ammonia water: water = 5: 2: 2), etc. may be used. can. Further, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

Further, the etching solution after wet etching is removed by washing together with the etched material. The waste liquid of the etching solution containing the removed material may be purified and the contained material may be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor layer from the waste liquid after etching, resources can be effectively utilized and the cost can be reduced.

Etching conditions (etching liquid, etching time, temperature, etc.) are appropriately adjusted according to the material so that etching can be performed in a desired processing shape.

Next, the resist masks 136a, 136b, 136c, 136d, and 136e are removed to form the oxide insulating layer 107 which is a protective insulating layer in contact with the oxide semiconductor layers 133 and 134.

At this stage, the oxide semiconductor layers 133 and 134 are formed with a region in contact with the oxide insulating layer 107, and a region of this region that overlaps with the oxide insulating layer 107 via the gate electrode layer and the gate insulating layer is a channel. It becomes a forming region.

The oxide insulating layer 107 has a film thickness of at least 1 nm or more, and can be formed by appropriately using a method such as a sputtering method in which impurities such as water and hydrogen are not mixed in the oxide insulating layer 107. In the present embodiment, a silicon oxide film having a film thickness of 300 nm is formed as the oxide insulating layer 107 by a sputtering method. The substrate temperature at the time of film formation may be room temperature or higher and 300 ° C. or lower, and in this embodiment, it is room temperature. The silicon oxide film is formed by the sputtering method under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon).
And can be done in an oxygen atmosphere. Further, a silicon oxide target or a silicon target can be used as the target. For example, using a silicon target, silicon oxide can be formed by a sputtering method in an oxygen atmosphere. The oxide insulating layer formed in contact with the oxide semiconductor layer whose resistance is lowered later is an inorganic insulating film that does not contain water, hydrogen ions, OH- ^, or other impurities and blocks the invasion of these from the outside. It is typically used, such as a silicon oxide film, a silicon nitride film, a gallium oxide film, an aluminum oxide film, or an aluminum nitride film.

Then, a second heat treatment (preferably 2) under an inert gas atmosphere or a nitrogen gas atmosphere.
00 ° C. or higher and 400 ° C. or lower, for example, 250 ° C. or higher and 350 ° C. or lower) (see FIG. 4 (A)).
). For example, a second heat treatment at 250 ° C. for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layers 133 and 134 overlapping with the oxide insulating layer 107 is heated in a state of being in contact with the oxide insulating layer 107.

Through the above steps, the oxide semiconductor layer after film formation is heat-treated for dehydration or dehydrogenation to reduce the resistance, and then a part of the oxide semiconductor layer is selectively selected. It is in a state of excess oxygen.

As a result, in the oxide semiconductor layer 133, the channel forming region 166 overlapping the gate electrode layer 161 becomes type I, and the high resistance source region 167a overlapping the source electrode layer 165a is formed.
The high resistance drain region 167b overlapping the drain electrode layer 165b is formed in a self-aligned manner, and the oxide semiconductor layer 163 is formed. Similarly, in the oxide semiconductor layer 134, the channel forming region 116 overlapping the gate electrode layer 101 becomes type I, and the high resistance source region 117a overlapping the source electrode layer 105a and the high resistance drain region 117b overlapping the drain electrode layer 105b are formed. Is formed in a self-aligned manner, and the oxide semiconductor layer 103 is formed.

A circuit by forming high resistance drain regions 117b and 167b (or high resistance source regions 117a and 167a) in oxide semiconductor layers 103 and 163 superimposed on the drain electrode layers 105b and 165b (and source electrode layers 105a and 165a). It is possible to improve the reliability when forming the above. Specifically, by forming the high resistance drain regions 117b and 167b, the high resistance drain regions 117b and 16 are formed from the drain electrode layers 105b and 165b.
The structure can be configured so that the conductivity can be changed stepwise over 7b and the channel forming regions 116 and 166. Therefore, the high power supply potential V is applied to the drain electrode layers 105b and 165b.
When operating by connecting to the wiring that supplies the DD, even if a high electric field is applied between the gate electrode layers 101 and 161 and the drain electrode layers 105b and 165b, the high resistance drain region becomes a buffer and a local high electric field is generated. It is not applied, and the withstand voltage of the transistor can be improved.

Further, in the oxide semiconductor layers 103 and 163 superimposed on the drain electrode layers 105b and 165b (and the source electrode layers 105a and 165a), the high resistance drain regions 117b and 167b (and the source electrode layers 105a and 165a)
Alternatively, by forming the high resistance source regions 117a and 167a), it is possible to reduce the leakage current in the channel formation regions 116 and 166 when the circuit is formed.

In the present embodiment, a silicon oxide film is formed as the oxide insulating layer 107 by a sputtering method, and then heat treatment is performed at 250 ° C. to 350 ° C. to expose an exposed portion of the oxide semiconductor layer between the source region and the drain region. Oxygen is impregnated and diffused into the oxide semiconductor layer from the (channel forming region). By producing the silicon oxide film by the sputtering method, excess oxygen can be contained in the silicon oxide film, and the oxygen can be impregnated and diffused in the oxide semiconductor layer by heat treatment. High resistance in the channel region due to the infiltration and diffusion of oxygen into the oxide semiconductor layer (
I-type) can be achieved. As a result, it is possible to obtain a thin film transistor that is normally off.

By the above steps, the thin film transistor 180 can be manufactured in the drive circuit section and the thin film transistor 170 can be manufactured in the pixel section on the same substrate. The thin film transistors 170 and 180 are bottom gate type thin film transistors including an oxide semiconductor layer including a high resistance source region, a high resistance drain region, and a channel forming region. Therefore, the thin film transistors 170, 18
0 means that even if a high electric field is applied, the high resistance drain region or the high resistance source region serves as a buffer and a local high electric field is not applied, so that the withstand voltage of the transistor is improved.

By forming the drive circuit and the pixel portion on the same substrate, the connection wiring between the drive circuit and the external signal can be shortened, and the semiconductor device can be miniaturized and the cost can be reduced.

A protective insulating layer may be further formed on the oxide insulating layer 107. For example, an RF sputtering method is used to form a silicon nitride film. The RF sputtering method is preferable as a method for forming a protective insulating layer because it has good mass productivity. The protective insulating layer uses an inorganic insulating film that does not contain water, hydrogen ions, OH- ^, or other impurities and blocks the invasion of these from the outside, and uses a silicon nitride film, an aluminum nitride film, or a silicon oxide film. An aluminum nitride film or the like is used.

Next, a third photolithography step is performed to form a resist mask, and the oxide insulating layer 1 is formed.
By etching 07, a contact hole 125 reaching the drain electrode layer 105b, a contact hole 118 reaching the drain electrode layer 165b, and a contact hole 119 reaching the conductive layer 162 are formed, and the resist mask is removed (see FIG. 4B). .). again,
By etching here, a contact hole 127 reaching the second terminal 122 and a contact hole 126 reaching the first terminal 121 are also formed. Further, the resist mask for forming the contact hole may be formed by an inkjet method. When the resist mask is formed by the inkjet method, the manufacturing cost can be reduced because the photomask is not used.

Next, a light-transmitting conductive film is formed. As the material of the conductive film having translucency, indium oxide (In ₂ O ₃ ), indium tin oxide alloy (In ₂ O ₃ -SnO ₂ , IT)
(Abbreviated as O) and the like are formed by using a sputtering method, a vacuum vapor deposition method, or the like. As another material of the conductive film having translucency, an Al—Zn—O-based non-single crystal film impregnated with nitrogen, that is, Al-
Even if a Zn-ON-based non-single crystal film, a Zn-ON-based non-single crystal film containing nitrogen, or a Sn-Zn-ON-based non-single crystal film containing nitrogen is used. good. The zinc composition ratio (atomic%) of the Al—Zn—ON non-single crystal film is 47 atomic% or less, and the composition ratio of aluminum in the Al—Zn—ON non-single crystal film (atomic%) ( The composition ratio (atomic%) of aluminum in the Al—Zn—ON non-single crystal film, which is larger than the atomic%), is the composition ratio (atom) of nitrogen in the Al—Zn—ON non-monocrystal film. %) Greater. Etching of such a material is performed with a hydrochloric acid-based solution. However, since the etching of ITO tends to generate a residue, an indium oxide zinc oxide alloy (In ₂ O ₃ -ZnO) may be used in order to improve the etching processability.

The unit of the composition ratio of the conductive film having translucency is atomic%, and the electron probe microanalyzer (EPMA: Electron Probe X-ray MicroAnalyzer) is used.
) Shall be evaluated by analysis.

Next, a fourth photolithography step is performed to form a resist mask, and unnecessary portions are removed by etching to remove the pixel electrode layer 110, the conductive layer 111, the wiring layer 145, and the terminal electrode 12.
8,129 is formed and the resist mask is removed. A cross-sectional view at this stage is shown in FIG. 4 (C). The plan view at this stage corresponds to FIG.

Further, in this fourth photolithography step, the gate insulating layer 102 in the capacitive portion
And the oxide insulating layer 107 is used as a dielectric, and the holding capacity is formed by the capacitive wiring layer 108 and the pixel electrode layer 110.

The capacitance 147, which is a holding capacitance formed by the capacitive wiring layer and the capacitive electrode using the gate insulating layer 102 as a dielectric, can also be formed on the same substrate as the drive circuit portion and the pixel portion. Further, the holding capacitance may be formed by overlapping the pixel electrodes with the gate wiring of the adjacent pixels via the protective insulating layer and the gate insulating layer without providing the capacitive wiring.

The terminal electrodes 128 and 129 formed on the terminal portion are electrodes or wirings used for connection with the FPC. The terminal electrode 128 formed on the first terminal 121 serves as a connection terminal electrode that functions as an input terminal for the gate wiring. Terminal electrode 129 formed on the second terminal 122
Is a terminal electrode for connection that functions as an input terminal for source wiring.

Further, FIGS. 11 (A1) and 11 (A2) show a top view and a cross-sectional view of the gate wiring terminal portion at this stage, respectively. FIG. 11 (A1) corresponds to a cross-sectional view taken along the line C1-C2 in FIG. 11 (A2). In FIG. 11A, the conductive film 155 formed on the protective insulating layer 154 is a terminal electrode for connection that functions as an input terminal. Further, in FIG. 11A, in the terminal portion, the first terminal 151 formed of the same material as the gate wiring and the connection electrode 153 formed of the same material as the source wiring are provided in the gate insulating layer 152. It is conducted through the oxide semiconductor layer 157 in the contact hole. Further, the connection electrode 153 and the conductive film 155 are in direct contact with each other through a contact hole provided in the protective insulating layer to conduct conduction.

Further, FIGS. 11 (B1) and 11 (B2) show a top view and a cross-sectional view of the source wiring terminal portion, respectively. Further, FIG. 11 (B1) corresponds to a cross-sectional view taken along the line D1-D2 in FIG. 11 (B2). In FIG. 11B, the conductive film 155 formed on the protective insulating layer 154 is a terminal electrode for connection that functions as an input terminal. Further, in FIG. 11B, in the terminal portion, an electrode 156 made of the same material as the gate wiring is placed below the second terminal 150 electrically connected to the source wiring via the gate insulating layer 152. Overlap. Electrode 15
6 is not electrically connected to the second terminal 150, and if the electrode 156 is set to a potential different from that of the second terminal 150, for example, floating, GND, 0V, etc., the capacitance or static electricity for noise suppression is used. Capacity for countermeasures can be formed. Further, the second terminal 150 is electrically connected to the conductive film 155 via the protective insulating layer 154. An oxide semiconductor layer 158 is formed under the second terminal 150.

A plurality of gate wirings, source wirings, and capacitive wirings are provided according to the pixel density. Further, in the terminal portion, a plurality of first terminals having the same potential as the gate wiring, second terminals having the same potential as the source wiring, and third terminals having the same potential as the capacitive wiring are arranged side by side. The number of each terminal may be any number, and the practitioner may make an appropriate decision.

In this way, by four photolithography steps, six photomasks are used to complete the drive circuit unit having the thin film transistor 180, the pixel unit having the thin film transistor 170, the capacity 147 having the holding capacity, and the external extraction terminal unit. Can be done. The thin film transistor and the holding capacity can be arranged in a matrix corresponding to each pixel to form a pixel portion, and can be used as one substrate for manufacturing an active matrix type display device. In the present specification, such a substrate is referred to as an active matrix substrate for convenience.

When a resist mask having a plurality of (typically two types) thickness regions formed by a multi-gradation mask as in the present embodiment is used, the number of resist masks can be reduced, so that the process is simplified. It is possible to reduce the cost and cost. Therefore, the semiconductor device can be manufactured at low cost and with high productivity.

When manufacturing an active matrix type liquid crystal display device, a liquid crystal layer is provided between the active matrix substrate and the facing substrate provided with the counter electrode, and the active matrix substrate and the facing substrate are fixed. A common electrode electrically connected to the counter electrode provided on the counter substrate is provided on the active matrix substrate, and a fourth terminal electrically connected to the common electrode is provided in the terminal portion. This fourth terminal is a terminal for setting the common electrode to a fixed potential, for example, GND, 0V, or the like.

An insulating layer 191 that functions as an alignment film is formed on the oxide insulating layer 107, the conductive layer 111, the wiring layer 145, and the pixel electrode layer 110.

On the facing substrate 190, a colored layer 195, a facing electrode layer 194, and an insulating layer 19 functioning as an alignment film 19
Form 3. The substrate 100 and the facing substrate 190 are bonded to each other with a sealing material (not shown) with the liquid crystal layer 192 sandwiched via a spacer for adjusting the cell gap of the liquid crystal display device. The bonding step may be performed under reduced pressure.

As the sealing material, it is typically preferable to use a visible light curable, ultraviolet curable or thermosetting resin. Typically, acrylic resin, epoxy resin, amine resin and the like can be used. Further, it may contain a light (typically ultraviolet) polymerization initiator, a thermosetting agent, a filler, and a coupling agent.

The liquid crystal layer 192 is formed by enclosing a liquid crystal material in a void. The liquid crystal layer 192 may use a dispenser method (dropping method) in which the substrate 100 and the facing substrate 190 are dropped before being bonded to each other, or the substrate 100 and the facing substrate 190 are bonded to each other and then the liquid crystal is used by the capillary phenomenon. The injection method of injecting the liquid crystal can be used. The liquid crystal material is not particularly limited, and various materials can be used. Further, if a material showing a blue phase is used as the liquid crystal material, the alignment film can be eliminated.

A polarizing plate 196a can be provided on the outside of the substrate 100, and a polarizing plate 196b can be provided on the outside of the facing substrate 190 to manufacture a transmissive liquid crystal display device according to the present embodiment (see FIG. 1).

Further, although not shown in the present embodiment, an optical member (optical substrate) such as a black matrix (light-shielding layer), a polarizing member, a retardation member, and an antireflection member is appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a side light or the like may be used as the light source.

In an active matrix type liquid crystal display device, a display pattern is formed on a screen by driving pixel electrodes arranged in a matrix. Specifically, by applying a voltage between the selected pixel electrode and the counter electrode corresponding to the pixel electrode, optical modulation of the liquid crystal layer arranged between the pixel electrode and the counter electrode is performed, and this is performed. The optical modulation is recognized by the observer as a display pattern.

In the moving image display of the liquid crystal display device, there is a problem that afterimages or blurring of moving images occur because the response of the liquid crystal molecules themselves is slow. In order to improve the moving image characteristics of the liquid crystal display device, there is a so-called black insertion driving technique in which the entire black display is performed every other frame.

There is also a so-called double speed drive technique that improves the moving image characteristics by increasing the frame frequency to 1.5 times, preferably 2 times or more the normal frame frequency (60 Hz).

Further, in order to improve the moving image characteristics of the liquid crystal display device, a surface light source is configured by using a plurality of LED (light emitting diode) light sources or a plurality of EL light sources as a backlight, and each light source constituting the surface light source is independent. There is also a drive technology that drives the light source intermittently within one frame period. As the surface light source, three or more types of LEDs may be used, or white light emitting LEDs may be used. Since multiple LEDs can be controlled independently, LE is matched to the switching timing of the optical modulation of the liquid crystal layer.
It is also possible to synchronize the light emission timing of D. Since this drive technology can partially turn off the LED, it is possible to reduce power consumption, especially in the case of video display in which a large proportion of the black display area occupies one screen.

By combining these drive technologies, it is possible to improve display characteristics such as moving image characteristics of the liquid crystal display device as compared with the conventional case.

By forming a thin film transistor using an oxide semiconductor, the manufacturing cost can be reduced. In particular, by forming an oxide insulating layer in contact with an oxide semiconductor layer by the above method, a thin film transistor having stable electrical characteristics can be produced and provided. Therefore, it is possible to provide a semiconductor device having a thin film transistor having good electrical characteristics and high reliability.

Since the semiconductor layer in the channel formation region is in the high resistance region, the electrical characteristics of the thin film transistor can be stabilized and an increase in off-current can be prevented. Therefore, it is possible to obtain a semiconductor device having a thin film transistor having good electrical characteristics and high reliability.

Further, since the thin film transistor is easily destroyed by static electricity or the like, it is preferable to provide a protection circuit on the same substrate as the pixel portion or the drive circuit. The protection circuit is preferably configured by using a non-linear element using an oxide semiconductor layer. For example, the protection circuit is arranged between the pixel unit and the scanning line input terminal and the signal line input terminal. In the present embodiment, a plurality of protection circuits are arranged so that a surge voltage is applied to the scanning line, the signal line, and the capacitive bus line due to static electricity or the like, and the pixel transistor or the like is not destroyed. Therefore, when a surge voltage is applied to the protection circuit, the charge is configured to escape to the common wiring. Further, the protection circuit is composed of non-linear elements arranged in parallel with the scanning line. The non-linear element is composed of a two-terminal element such as a diode or a three-terminal element such as a transistor. for example,
It can be formed in the same process as the thin film transistor 170 of the pixel portion, and for example, by connecting the gate terminal and the drain terminal of the transistor, it is possible to have the same characteristics as the diode.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 2)
In the present embodiment, FIGS. 6 and 7 show an example in which the oxide conductive layer is provided as a source region and a drain region between the oxide semiconductor layer and the source electrode layer or the drain electrode layer in the first embodiment. .. Therefore, other parts can be performed in the same manner as in the first embodiment, and the description of the part having the same or the same function as that of the first embodiment and the repetition of the process will be omitted. Further, since FIGS. 6 and 7 are the same as FIGS. 1 to 5 except that the steps are partially different, the same reference numerals are used for the same parts, and detailed description of the same parts will be omitted.

First, according to the first embodiment, a metal conductive layer is formed on the substrate 100, and the metal conductive layer is etched by using a resist mask formed by the first photolithography step, and the first terminal 121 and the gate electrode layer 161 are etched. , Conductive layer 162, Gate electrode layer 101, Capacitive wiring layer 108
To form.

The gate insulating layer 102 is formed on the first terminal 121, the gate electrode layer 161 and the conductive layer 162, the gate electrode layer 101, and the capacitive wiring layer 108, and the oxide semiconductor layer, the oxide conductive layer, and the metal conductive layer are laminated. .. The gate insulating layer 102, the oxide semiconductor layer, the oxide conductive layer and the metal conductive layer can be continuously formed without being exposed to the atmosphere.

As a film forming method of the oxide conductive layer, a sputtering method, a vacuum vapor deposition method (electron beam vapor deposition method, etc.), an arc discharge ion plating method, or a spray method is used. The material of the oxide conductive layer preferably contains zinc oxide as a component, and preferably does not contain indium oxide. As such an oxide conductive layer, zinc oxide, zinc aluminum oxide, zinc nitride aluminum, zinc gallium oxide and the like can be applied. Film thickness is 50 nm
Select appropriately within the range of 300 nm or less. When the sputtering method is used, S
Film formation is performed using a target containing 2% by weight or more and 10% by weight or less of io ₂ , the oxide conductive layer is impregnated with SiOx (X> 0) that inhibits crystallization, and dehydrogenation or dehydration is performed in a later step. It is preferable to suppress crystallization during heat treatment for dehydrogenation.

Next, the oxide semiconductor layer and the oxide conductive layer are laminated and subjected to dehydrogenation and dehydrogenation heat treatment to form the oxide semiconductor layer 131, the oxide conductive layer 140, and the metal conductive layer 137 (Fig.). 6 (A).). By heat-treating at a temperature of 400 ° C. to 700 ° C., the oxide semiconductor layer can be dehydrated and dehydrogenated, and subsequent re-impregnation of water ( _H2O ) can be prevented.

By this heat treatment, the oxide conductive layer crystallizes unless the oxide conductive layer contains a crystallization inhibitor such as silicon oxide. The crystals of the oxide conductive layer grow in columns with respect to the underlying surface.
As a result, when the metal conductive layer above the oxide conductive layer is etched in order to form the source electrode layer and the drain electrode layer, it is possible to prevent the formation of an undercut.

Further, the conductivity of the oxide conductive layer can be improved by the heat treatment of dehydration and dehydrogenation of the oxide semiconductor layer. Only the oxide conductive layer may be heat-treated at a lower temperature than the heat treatment of the oxide semiconductor layer.

A second photolithography step is performed using exposure using a high gradation mask, and resist masks 135a and 1 are placed on the gate insulating layer 102, the oxide semiconductor layer 131, and the metal conductive layer 137.
Form 35b and 135d.

Next, the first etching step is performed using the resist masks 135a, 135b, and 135d, and the oxide semiconductor layer 131 and the metal conductive layer 137 are etched and processed into an island shape. As a result, the oxide semiconductor layers 133, 134, 120, the oxide conductive layers 175, 176, 177, and the metal conductive layers 185, 186, and 188 can be formed (see FIG. 6B).

Next, the resist masks 135a, 135b, 135d are ashed. As a result, the area (volume when viewed three-dimensionally) of the resist mask is reduced, and the thickness is reduced. At this time, the resist of the resist mask (the region overlapping with a part of the gate electrode layer 161) in the region having a thin film thickness is removed, and the separated resist masks 136a and 136b can be formed. Similarly, the resist masks 135b and 135d are also ashed, and the area (volume when viewed three-dimensionally) of the resist mask is reduced to become the resist masks 136c, 136d and 136e.

Using a resist mask 136a, 136b, 136c, 136d, 136e, unnecessary portions are removed by etching to form a source electrode layer 165a, a drain electrode layer 165b, a source electrode layer 105a, a drain electrode layer 105b, and a second terminal 122. Form (see FIG. 6 (C)).

In this step, a second terminal 122, which is the same material as the oxide semiconductor layer 120, the source electrode layers 105a and 165a, and the drain electrode layers 105b and 165b, is formed in the terminal portion. The second terminal 122 is source wiring (source wiring including source electrode layers 105a and 165a).
Is electrically connected to.

The respective materials and etching conditions are appropriately adjusted so that the oxide conductive layers 175, 176, 177 and the oxide semiconductor layers 133, 134, and 120 are not removed when the metal conductive layer is etched.

Next, the resist masks 136a, 136b, 136c, 136d, and 136e were removed, and the oxide conductive layer 140 was etched using the source electrode layer 105a, the drain electrode layer 105b, the source electrode layer 165a, and the drain electrode layer 165b as masks. Oxide conductive layer 164a,
164b, oxide conductive layers 104a and 104b are formed (see FIG. 6D). The oxide conductive layer 140 containing zinc oxide as a component can be easily etched by using an alkaline solution such as a stripping solution of a resist. In the same process, the oxide conductive layer 13 is also applied to the terminal portion.
9 is formed.

Using the difference in etching rate between the oxide semiconductor layer and the oxide conductive layer, an etching process for dividing the oxide conductive layer in order to form a channel region is performed. The oxide conductive layer on the oxide semiconductor layer is selectively etched by utilizing the fact that the etching rate of the oxide conductive layer is faster than that of the oxide semiconductor layer.

Therefore, it is preferable to remove the resist masks 136a, 136b, 136c, 136d and 136e by an ashing step. In the case of etching using a stripping solution, the etching conditions (type of etchant, concentration, etching time) are appropriately adjusted so that the oxide conductive layers 175 and 176 and the oxide semiconductor layers 133 and 134 are not excessively etched.

As in the present embodiment, the oxide conductive layer and the metal conductive layer are laminated, and the wiring pattern including the source electrode layer and the drain electrode layer is etched with the same mask under the wiring pattern of the metal conductive layer. , The oxide conductive layer can be left.

Also in the contact between the gate wiring and the source wiring, since the oxide conductive layer is formed in the lower layer of the source wiring, the oxide conductive layer is preferable as a buffer, and further, it is preferable because it does not form an oxide insulating from metal. ..

The oxide insulating layer 107 is formed as a protective insulating layer in contact with the oxide semiconductor layers 133 and 134. In the present embodiment, a silicon oxide film having a film thickness of 300 nm is formed as the oxide insulating layer 107 by using a sputtering method.

Then, a second heat treatment (preferably 2) under an inert gas atmosphere or a nitrogen gas atmosphere.
00 ° C. or higher and 400 ° C. or lower, for example, 250 ° C. or higher and 350 ° C. or lower). For example, a second heat treatment at 250 ° C. for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layers 133 and 134 overlapping with the oxide insulating layer 107 is heated in a state of being in contact with the oxide insulating layer 107.

Through the above steps, the oxide semiconductor layer after film formation is heat-treated for dehydration or dehydrogenation to reduce the resistance, and then a part of the oxide semiconductor layer is selectively selected. It is in a state of excess oxygen.

As a result, in the oxide semiconductor layer 133, the channel forming region 166 overlapping the gate electrode layer 161 becomes type I, and the high resistance source region 167a overlapping the source electrode layer 165a and the oxide conductive layer 164a, the drain electrode layer 165b, and the drain electrode layer 165b. The high resistance drain region 167b overlapping the oxide conductive layer 164b is formed in a self-aligned manner, and the oxide semiconductor layer 163 is formed. Similarly, in the oxide semiconductor layer 134, the channel forming region 116 overlapping the gate electrode layer 101 becomes type I, and the high resistance source region 117a overlapping the source electrode layer 105a and the oxide conductive layer 104a, the drain electrode layer 105b, and the drain electrode layer 105b. The high resistance drain region 117b overlapping the oxide conductive layer 104b is formed in a self-aligned manner, and the oxide semiconductor layer 103 is formed.

The oxide conductive layers 104b and 164b provided between the oxide semiconductor layers 163 and 103, the drain electrode layer 105b made of a metal material, and the drain electrode layer 165b are low resistance drain regions (
It also functions as an LRN (Low Response N-type conductivity) region, also referred to as an LRD (Low Response Drain) region). Similarly, the source electrode layer 105a made of the oxide semiconductor layers 163 and 103 and the metal material.
, The oxide conductive layers 104a and 164a provided between the source electrode layers 165a are low resistance source regions (LRN (Low Response N-type connected).
It also functions as a ty) region and an LRS (Low Response Source) region). The withstand voltage of the transistor can be further improved by forming the oxide semiconductor layer, the low resistance drain region, and the drain electrode layer made of a metal material. Specifically, the carrier concentration in the low resistance drain region is larger than that in the high resistance drain region (HRD region), and is preferably in the range of, for example, 1 × 10 ²⁰ / cm ³ or more and 1 × 10 ²¹ / cm ³ or less. ..

By the above steps, the thin film transistor 181 can be manufactured in the drive circuit section and the thin film transistor 171 can be manufactured in the pixel section on the same substrate. The thin film transistors 171 and 181 are bottom gate type thin film transistors including an oxide semiconductor layer including a high resistance source region, a high resistance drain region, and a channel forming region. Therefore, the thin film transistors 171 and 18
In No. 1, even if a high electric field is applied, the high resistance drain region or the high resistance source region serves as a buffer and a local high electric field is not applied, so that the withstand voltage of the transistor is improved.

Further, in the capacitive portion, the capacitive wiring layer 108, the gate insulating layer 102, and the oxide conductive layer 104b
A capacity 146 formed by laminating the oxide conductive layer 107 and the drain electrode layer 105b formed in the same step and the metal conductive layer formed in the same step is formed.

Next, the flattening insulating layer 109 is formed on the oxide insulating layer 107. In this embodiment, the flattening insulating layer 109 is formed only in the pixel portion. As the flattening insulating layer 109, an organic material having heat resistance such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphorus glass), BPSG (phosphorus glass) and the like can be used. The flattening insulating layer 109 may be formed by laminating a plurality of insulating films formed of these materials.

The siloxane-based resin is Si—O—S formed from a siloxane-based material as a starting material.
It corresponds to a resin containing i-bond. As the substituent of the siloxane-based resin, an organic group (for example, an alkyl group or an aryl group) or a fluoro group may be used. Further, the organic group may have a fluoro group.

The method for forming the flattening insulating layer 109 is not particularly limited, and depending on the material thereof, a sputtering method, an SOG method, a spin coating method, a dip, a spray coating method, or a droplet ejection method (inkjet method,
Screen printing, offset printing, etc.) can be used. Also, a doctor knife,
The flattening insulating layer 109 can be formed by using a roll coater, a curtain coater, a knife coater, or the like. In the present embodiment, the flattening insulating layer 109 is formed by using photosensitive acrylic.

Next, a third photolithography step is performed to form a resist mask, and the flattening insulating layer 1 is formed.
The contact hole 125 reaching the drain electrode layer 105b is formed by etching 09 and the oxide insulating layer 107, and the resist mask is removed. Further, the contact hole 127 reaching the second terminal 122 and the contact hole 126 reaching the first terminal 121 are also formed by etching here.

Next, a light-transmitting conductive film is formed, a fourth photolithography step is performed, a resist mask is formed, and unnecessary portions are removed by etching to remove the pixel electrode layer 110 and the conductive layer 11.
1. Form terminal electrodes 128 and 129 and remove the resist mask (see FIG. 7A).
..

Similar to the first embodiment, the liquid crystal layer 192 is sandwiched and the opposed substrates 190 are bonded to each other to manufacture the liquid crystal display device of the present embodiment (see FIG. 7B).

By providing the oxide conductive layer between the oxide semiconductor layer and the source electrode layer and the drain electrode layer as the source region and the drain region, it is possible to reduce the resistance of the source region and the drain region, and the high speed of the transistor can be achieved. Can work. It is effective to use the oxide conductive layer as the source region and the drain region in order to improve the frequency characteristics of the peripheral circuit (drive circuit). This is because the contact between the metal electrode (Ti or the like) and the oxide conductive layer can lower the contact resistance as compared with the contact between the metal electrode (Ti or the like) and the oxide semiconductor layer.

Further, molybdenum (Mo) used as a part of the wiring material in the liquid crystal panel (for example, Mo / Al / Mo) has a high contact resistance with the oxide semiconductor layer, which has been a problem. This is T
This is because Mo is less likely to oxidize than i, so that the action of extracting oxygen from the oxide semiconductor layer is weak, and the contact interface between Mo and the oxide semiconductor layer is not n-shaped. However, even in such a case, the contact resistance can be reduced by interposing the oxide conductive layer between the oxide semiconductor layer and the source electrode layer and the drain electrode layer, and the frequency characteristics of the peripheral circuit (drive circuit) can be improved. Can be done.

Since the channel length of the thin film transistor is determined at the time of etching the oxide conductive layer, the channel length can be further shortened. For example, the channel length can be shortened to L0.1 μm or more and 2 μm or less to increase the operating speed.

(Embodiment 3)
Here, in the liquid crystal display device in which the liquid crystal layer is enclosed between the first substrate and the second substrate, the second
An example of forming a common connection portion for electrically connecting to a counter electrode provided on the substrate of No. 1 on the first substrate is shown. A thin film transistor is formed as a switching element on the first substrate, and the process is formed without complicating the process by sharing the manufacturing process of the common connection portion with the manufacturing process of the switching element of the pixel portion.

The common connection portion is arranged at a position where it overlaps with the sealing material for adhering the first substrate and the second substrate, and is electrically connected to the counter electrode via the conductive particles contained in the sealing material. .. Alternatively, a common connection portion is provided at a location that does not overlap with the sealing material (excluding the pixel portion), and a paste containing conductive particles is provided separately from the sealing material so as to overlap the common connection portion, and is electrically connected to the counter electrode. The connection is made.

FIG. 8A is a diagram showing a cross-sectional structure diagram of a semiconductor device in which a thin film transistor and a common connection portion are manufactured on the same substrate.

In FIG. 8A, the thin film transistor 220 electrically connected to the pixel electrode layer 227 is
It is a channel protection type thin film transistor provided in the pixel portion, and in the present embodiment, the same structure as the thin film transistor 170 of the first embodiment is used.

Further, FIG. 8B is a diagram showing an example of a top view of the common connection portion, and the chain line C3-C4 in the figure corresponds to the cross section of the common connection portion in FIG. 8A. In FIG. 8B, the same parts as those in FIG. 8A will be described using the same reference numerals.

The common potential line 205 provided on the oxide semiconductor layer 210 is provided on the gate insulating layer 202, and is manufactured by the same material and the same process as the source electrode layer and drain electrode layer of the thin film transistor 220.

Further, the common potential line 205 is covered with the protective insulating layer 203, and the protective insulating layer 203 has a plurality of openings at positions overlapping with the common potential line 205. This opening is the thin film transistor 2
It is produced in the same process as the contact hole connecting the drain electrode layer 20 and the pixel electrode layer 227.

Since the area size is significantly different here, the contact hole in the pixel portion and the opening in the common connection portion will be referred to separately. Further, in FIG. 8A, the pixel portion and the common connection portion are not shown at the same scale, and for example, the length of the chain line C3-C4 of the common connection portion is 500.
While the width is about μm, the width of the thin film transistor is less than 50 μm, which is actually 10.
Although the area size is more than doubled, the scales of the pixel portion and the common connection portion are shown in FIG. 8A for the sake of clarity.

Further, the common electrode layer 206 is provided on the protective insulating layer 203, and the pixel electrode layer 227 of the pixel portion is provided.
Made of the same material and in the same process.

In this way, the manufacturing process of the common connection portion is performed in common with the manufacturing process of the switching element of the pixel portion. It is preferable that the common potential line is a metal wiring and has a configuration for reducing wiring resistance.

Then, the first substrate 200 provided with the pixel portion and the common connection portion and the second substrate having the counter electrode are fixed by using the sealing material.

When the sealing material contains conductive particles, the alignment of the pair of substrates is performed so that the sealing material and the common connection portion overlap. For example, in a small liquid crystal panel, two common connecting portions are arranged so as to be overlapped with a sealing material on the diagonal of the pixel portion. In addition, for large LCD panels,
Four or more common connection portions are arranged so as to overlap with the sealing material.

The common electrode layer 206 is an electrode that comes into contact with the conductive particles contained in the sealing material, and is a second electrode.
It is electrically connected to the counter electrode of the substrate.

When the liquid crystal injection method is used, the liquid crystal is injected between the pair of substrates after fixing the pair of substrates with the sealing material. When the liquid crystal drop method is used, a sealing material is drawn on the second substrate or the first substrate, the liquid crystal is dropped, and then the pair of substrates are bonded together under reduced pressure.

In this embodiment, an example of a common connection portion that is electrically connected to the counter electrode is shown, but the connection portion is not particularly limited, and is a connection portion that connects to other wiring, a connection portion that connects to an external connection terminal, or the like. Can be used for.

This embodiment can be freely combined with other embodiments.

(Embodiment 4)
In the present embodiment, an example in which a part of the manufacturing process of the thin film transistor is different from that of the first embodiment is shown in FIG.
Shown at 0. Since FIG. 10 is the same as FIGS. 1 to 5 except that the steps are partially different, the same reference numerals are used for the same parts, and detailed description of the same parts will be omitted.

First, according to the first embodiment, the gate electrode layer, the gate insulating layer 102, and the oxide semiconductor layer 130 are formed on the substrate 100.

Next, the oxide semiconductor layer 130 is dehydrated or dehydrogenated. The temperature of the first heat treatment for dehydration or dehydrogenation is 400 ° C. or higher and lower than the strain point of the substrate, preferably 425 ° C. or higher. If the temperature is 425 ° C. or higher, the heat treatment time may be 1 hour or less, but if the temperature is lower than 425 ° C., the heat treatment time is longer than 1 hour. Here, after introducing the substrate into an electric furnace, which is one of the heat treatment devices, and heat-treating the oxide semiconductor layer in a nitrogen atmosphere, water to the oxide semiconductor layer is not exposed to the atmosphere. It prevents the remixing of hydrogen and hydrogen, and obtains an oxide semiconductor layer. Then, high-purity oxygen gas, high _- purity N2O gas, or ultra-dry air (dew point is −40 ° C. or lower, preferably −60 ° C. or lower) is introduced into the same furnace for cooling. It is preferable that the oxygen gas or _N2O gas does not contain water, hydrogen, or the like. Alternatively, the purity of the oxygen gas or N2O gas to be introduced into the heat treatment apparatus is 6N (99.99999%) or _more , preferably 7N (99.99999%) or _more (that is, in oxygen gas or N2O gas). The impurity concentration is preferably 1 ppm or less, preferably 0.1 ppm or less).

Further, after the first heat treatment for dehydration or dehydrogenation, heat treatment is performed in an oxygen gas or N2O gas atmosphere at a temperature of ₂₀₀ ° C. or higher and 400 ° C. or lower, preferably 200 ° C. or higher and 300 ° C. or lower. May be good.

By going through the above steps, the entire oxide semiconductor layer is brought into a state of excess oxygen, so that the resistance is increased, that is, the type I is formed. Therefore, an oxide semiconducting film that is entirely I-shaped is obtained.

Next, a metal conductive layer is formed on the oxide semiconductor layer, a resist mask is formed by a second photolithography step using a multi-gradation mask, and etching is selectively performed to obtain a source electrode layer and a drain electrode layer. The oxide semiconductor layers 168 and 118 are formed, and the oxide insulating layer 107 is formed by a sputtering method.

Next, in order to reduce variations in the electrical characteristics of the thin film transistor, heat treatment (preferably 150 ° C. or higher and lower than 350 ° C.) may be performed under an inert gas atmosphere or a nitrogen gas atmosphere. For example, heat treatment is performed at 250 ° C. for 1 hour in a nitrogen atmosphere.

A resist mask is formed by a third photolithography step, and etching is selectively performed to form a first terminal 121, a conductive layer 162, a drain electrode layer 105b, and an oxide semiconductor layer 120 on the gate insulating layer and the oxide insulating layer. A contact hole is formed to reach the second terminal 122 to be stacked. After forming a light-transmitting conductive film, a resist mask is formed by a fifth photolithography step, and selective etching is performed to pixel electrode layer 110 and terminal electrodes 12.
8. Form the terminal electrode 129 and the wiring layer 145.

In this embodiment, the connection between the first terminal 121 and the terminal electrode 128 is directly performed without going through the connection electrode 120. Further, the drain electrode layer 165b and the conductive layer 162 are connected to each other via the wiring layer 145.

Further, in the capacitance section, the capacitance is formed by laminating the capacitive wiring layer 108, the gate insulating layer 102, the metal conductive layer formed in the same process as the source electrode layer and the drain electrode layer, the oxide insulating layer 107, and the pixel electrode layer 110. 148 is formed.

By the above steps, the thin film transistor 183 can be manufactured in the drive circuit section and the thin film transistor 173 can be manufactured in the pixel section on the same substrate.

Similar to the first embodiment, the liquid crystal layer 192 is sandwiched and the opposed substrates 190 are bonded to each other to manufacture the liquid crystal display device of the present embodiment (see FIG. 10).

This embodiment can be freely combined with other embodiments.

(Embodiment 5)
In this embodiment, an example of manufacturing at least a part of the drive circuit and a thin film transistor to be arranged in the pixel portion on the same substrate will be described below.

The thin film transistor to be arranged in the pixel portion is formed according to the first to fourth embodiments. Further, since the thin film transistors shown in the first to fourth embodiments are n-channel type TFTs, a part of the drive circuit that can be configured by the n-channel type TFT is placed on the same substrate as the thin film transistor of the pixel portion. Form.

FIG. 12A shows an example of a block diagram of the active matrix type display device. On the substrate 5300 of the display device, a pixel unit 5301, a first scanning line driving circuit 5302, a second scanning line driving circuit 5303, and a signal line driving circuit 5304 are provided. A plurality of signal lines are extended from the signal line drive circuit 5304 and arranged in the pixel unit 5301, and the plurality of scan lines are extended from the first scan line drive circuit 5302 and the second scan line drive circuit 5303. Have been placed. In the intersection region between the scanning line and the signal line, pixels having a display element are arranged in a matrix. Further, the substrate 5300 of the display device is FPC (Flexible Printed Ci).
Timing control circuit 5305 (controller, control I) via a connection such as rcut).
It is also connected to C).

In FIG. 12A, the first scanning line driving circuit 5302, the second scanning line driving circuit 5303, and the signal line driving circuit 5304 are formed on the same substrate 5300 as the pixel portion 5301. Therefore, the number of parts such as a drive circuit provided externally is reduced, so that the cost can be reduced. Further, when the drive circuit is provided outside the substrate 5300, the number of connections at the connection portion can be reduced by extending the wiring, and the reliability or the yield can be improved.

The timing control circuit 5305 supplies the first scan line drive circuit 5302 with, for example, a first scan line drive circuit start signal (GSP1) and a scan line drive circuit clock signal (GCLK1). Further, the timing control circuit 5305 has, as an example, a second scanning line driving circuit start signal (GSP2) (also referred to as a start pulse) and a scanning line driving circuit clock signal (also referred to as a start pulse) with respect to the second scanning line driving circuit 5303. GCLK2) is supplied. The signal line drive circuit 5304 is provided with a signal line drive circuit start signal (SSP), a signal line drive circuit clock signal (SCLK), a video signal data (DATA) (also simply referred to as a video signal), and a latch signal (LAT). It shall be supplied. Each clock signal may be a plurality of clock signals with different periods, or may be supplied together with a signal (CKB) in which the clock signal is inverted. It is possible to omit one of the first scanning line driving circuit 5302 and the second scanning line driving circuit 5303.

In FIG. 12B, a circuit having a low drive frequency (for example, a first scan line drive circuit 5302 and a second scan line drive circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and a signal line drive circuit 5304 is formed. Is shown for a configuration in which is formed on a substrate different from the pixel portion 5301. With this configuration, a drive circuit formed on the substrate 5300 can be configured by a thin film transistor having a smaller field effect mobility than a transistor using a single crystal semiconductor. Therefore, it is possible to increase the size of the display device, reduce the cost, or improve the yield.

Further, the thin film transistors shown in the first to fourth embodiments are n-channel TFTs. Figure 1
3 (A) and FIG. 13 (B) show and explain an example of the configuration and operation of the signal line drive circuit configured by the n-channel TFT.

The signal line drive circuit has a shift register 5601 and a switching circuit 5602.
The switching circuit 5602 has a plurality of circuits called switching circuits 5602_1 to 5602_N (N is a natural number). Each of the switching circuits 5602_1 to 5602_N has a plurality of transistors of thin film transistors 5603_1 to 5603_k (k is a natural number). An example in which the thin film transistors 5603_1 to 5603_k are N-channel TFTs will be described.

The connection relationship of the signal line drive circuit will be described by taking the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are each wired 5604_1.
It is connected to ~ 5604_k. The second terminals of the thin film transistors 5603_1 to 5603_k are connected to the signal lines S1 to Sk, respectively. Thin film transistor 5603_1-5603_
The gate of k is connected to the shift register 5601.

The shift register 5601 outputs H level (also referred to as H signal, high power supply potential level) signals to the wirings 5605_1 to 5605_N in order, and the switching circuits 5602_1 to 56
It has a function to select 02_N in order.

The switching circuit 5602_1 includes wirings 5604_1 to 5604_k and signal lines S1 to Sk.
A function to control the continuity state (continuity between the first terminal and the second terminal), that is, wiring 5604_
It has a function of controlling whether or not the potential of 1 to 5604_k is supplied to the signal lines S1 to Sk.
As described above, the switching circuit 5602_1 has a function as a selector. Further, the thin film transistors 5603_1 to 5603_k are each wired 5604_1 to 5604_k.
A function to control the conduction state between the signal lines S1 to Sk, that is, wiring 5604_1 to 5604_k.
It has a function of supplying the potential of the above to the signal lines S1 to Sk. Thus, the thin film transistor 56
Each of 03_1 to 5603_k has a function as a switch.

Video signal data (DATA) is input to each of the wirings 5604_1 to 5604_k. The video signal data (DATA) is often image information or an analog signal corresponding to the image signal.

Next, the operation of the signal line drive circuit of FIG. 13A will be described with reference to the timing chart of FIG. 13B. FIG. 13B shows an example of the signals Sout_1 to Sout_N and the signals Vdata_1 to Vdata_k. The signals Sout_1 to Sout_N are examples of output signals of the shift register 5601, respectively, and the signals Vdata_1 to Vdata
_K is an example of a signal input to the wirings 5604_1 to 5604_k, respectively. note that,
One operation period of the signal line drive circuit corresponds to one gate selection period in the display device. The 1-gate selection period is, for example, divided into a period T1 to a period TN. The periods T1 to TN are periods for writing video signal data (DATA) to pixels belonging to the selected rows, respectively.

In addition, the bluntness of the signal waveform and the like in each configuration shown in the drawings and the like of the present embodiment may be exaggerated for the sake of clarification. Therefore, it should be added that it is not necessarily limited to the scale.

In the period T1 to the period TN, the shift register 5601 wires the H level signal 560.
Output in order from 5-1 to 5605_N. For example, in the period T1, the shift register 5
The 601 outputs a high-level signal to the wiring 5605_1. Then, since the thin film transistors 5603_1 to 5603_k are turned on, the wirings 5604_1 to 5604_k and the signal lines S1 to Sk are in a conductive state. At this time, in the wiring 5604_1 to 5604_k,
Data (S1) to Data (Sk) are input. Data (S1) to Data (Sk)
) Is written to the pixels in the first column to the kth column among the pixels belonging to the selected row via the thin film transistors 5603_1 to 5603_k, respectively. In this way, in the periods T1 to TN, the video signal data (DATA) is written in order of k columns to the pixels belonging to the selected row.

As described above, by writing the video signal data (DATA) to the pixels in a plurality of columns, the number of video signal data (DATA) or the number of wirings can be reduced.
Therefore, the number of connections with the external circuit can be reduced. Further, by writing the video signal to the pixels in a plurality of columns, the writing time can be lengthened and the writing shortage of the video signal can be prevented.

As the shift register 5601 and the switching circuit 5602, it is possible to use the circuit composed of the thin film transistors shown in the first to fifth embodiments. In this case, the polarities of all the transistors of the shift register 5601 can be configured only with either the N-channel type or the P-channel type polarity.

The configuration of the scanning line drive circuit will be described. The scan line drive circuit has a shift register. In some cases, it may have a level shifter or a buffer. In the scan line drive circuit, the clock signal (CLK) and start pulse signal (SP) are stored in the shift register.
) Is input to generate a selection signal. The generated selection signal is buffered and amplified in the buffer and fed to the corresponding scan line. A gate electrode of a transistor having pixels for one line is connected to the scanning line. Since the transistors of one line of pixels must be turned on all at once, a buffer capable of passing a large current is used.

A form of a shift register used as a part of a scan line drive circuit and / or a signal line drive circuit will be described with reference to FIGS. 14 and 15.

The shift registers of the scanning line drive circuit and the signal line drive circuit will be described with reference to FIGS. 14 and 15. The shift register has a first pulse output circuit 10_1 to an Nth pulse output circuit 10_N (N is a natural number of 3 or more) (see FIG. 14A). The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the shift register shown in FIG. 14 (A).
The first clock signal CK1 from the first wiring 11, the second clock signal CK2 from the second wiring 12, the third clock signal CK3 from the third wiring 13, and the fourth from the fourth wiring 14
Clock signal CK4 is supplied. Further, in the first pulse output circuit 10_1, the start pulse SP1 (first start pulse) from the fifth wiring 15 is input. Further, in the nth pulse output circuit 10_n (n is a natural number of 2 or more and N or less) in the second and subsequent stages, the signal from the pulse output circuit 10_ (n-1) in the previous stage (previous stage signal OUT (n-1)). ) Is entered. Further, in the first pulse output circuit 10_1, the third pulse output circuit 10 in the second stage after the second stage
The signal from _3 is input. Similarly, in the second and subsequent stages of the nth pulse output circuit 10_n, the signal from the second (n + 2) pulse output circuit 10_ (n + 2) in the second and subsequent stages (second stage signal OU).
T (called n + 2)) is input. Therefore, from the pulse output circuit of each stage, the subsequent stage and /
Alternatively, the first output signal (OUT (1) (SR) for input to the pulse output circuit of the two previous stages.
)-OUT (N) (SR)), a second output signal (OUT (1)-
OUT (N)) is output. However, as shown in FIG. 14A, since the subsequent stage signal OUT (n + 2) is not input to the two final stages of the shift register, as an example, the second start pulse SP2 and the third stage are separately used. The start pulse SP3 may be input respectively.

The clock signal (CK) is a signal that repeats an H level and an L level (also referred to as an L signal or a low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1/4 cycle. In the present embodiment, the drive of the pulse output circuit is controlled by using the first clock signal (CK1) to the fourth clock signal (CK4). The clock signal is GCL depending on the input drive circuit.
Although it may be referred to as K or SCLK, it will be described here as CK.

The first input terminal 21, the second input terminal 22, and the third input terminal 23 are the first wiring 11
-It is electrically connected to any of the fourth wiring 14. For example, in FIG. 14A, in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, and the second input terminal 22 is connected to the second wiring 12. Electrically connected, third input terminal 23
Is electrically connected to the third wiring 13. Further, the second pulse output circuit 10_2 is
The first input terminal 21 is electrically connected to the second wiring 12, the second input terminal 22 is electrically connected to the third wiring 13, and the third input terminal 23 is the fourth wiring 14. Is electrically connected to.

Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, and a fifth. It is assumed that the input terminal 25, the first output terminal 26, and the second output terminal 27 are provided (see FIG. 14B). In the first pulse output circuit 10_1, the first clock signal CK1 is input to the first input terminal 21, the second clock signal CK2 is input to the second input terminal 22, and the third clock signal CK2 is input.
The third clock signal CK3 is input to the input terminal 23, the start pulse is input to the fourth input terminal 24, the subsequent signal OUT (3) is input to the fifth input terminal 25, and the first output terminal is used. The first output signal OUT (1) (SR) is output from 26, and the second output signal OUT (1) is output from the second output terminal 27.

The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N may use a 4-terminal thin film transistor described in the above embodiment in addition to a 3-terminal thin film transistor (TFT: also referred to as a Thin Film Transistor). can. FIG. 14 (C)
The symbol of the 4-terminal thin film transistor 28 described in the above embodiment is shown in the above. The symbol of the thin film transistor 28 shown in FIG. 14C means the four-terminal thin film transistor described in any one of the first, second, fifth, and sixth embodiments, and will be used below in the drawings and the like. In the present specification, when the thin film transistor has two gate electrodes via the semiconductor layer, the gate electrode below the semiconductor layer is referred to as the lower gate electrode, and the gate electrode above the semiconductor layer is referred to as the upper gate electrode. Call.

When an oxide semiconductor is used for a semiconductor layer including a channel forming region of a thin film transistor, the threshold voltage may shift to the minus side or the plus side depending on the manufacturing process. Therefore, in a thin film transistor using an oxide semiconductor for the semiconductor layer including the channel formation region,
A configuration capable of controlling the threshold voltage is preferable. The threshold voltage of the thin film transistor is controlled to a desired value by providing gate electrodes above and below the channel forming region of the thin film transistor 28 via a gate insulating layer and controlling the potentials of the upper and / or lower gate electrodes. Can be done.

Next, FIG. 14 shows an example of a specific circuit configuration of the pulse output circuit shown in FIG. 14 (B).
This will be described in (D).

The pulse output circuit shown in FIG. 14D has the first transistor 31 to the thirteenth transistor 43. Further, in addition to the first input terminal 21 to the fifth input terminal 25, the first output terminal 26, and the second output terminal 27 described above, the power line 51 to which the first high power potential VDD is supplied, A signal or a power supply potential is supplied to the first transistor 31 to the thirteenth transistor 43 from the power supply line 52 to which the second high power supply potential VCS is supplied and the power supply line 53 to which the low power supply potential VSS is supplied. Here, regarding the magnitude relationship of the power supply potentials of each power supply line in FIG. 14D, the first power supply potential VDD is set to a potential equal to or higher than the second power supply potential VCS, and the second power supply potential V
CC has a potential larger than the third power supply potential VSS. The first clock signal (CK1)
) To the fourth clock signal (CK4) is a signal that repeats the H level and the L level at regular intervals. It is assumed that the H level is VDD and the L level is VSS. Power line 51
By making the potential VDD higher than the potential VCS of the power line 52, the potential applied to the gate electrode of the transistor can be suppressed to a low level without affecting the operation, and the shift of the threshold value of the transistor is reduced. However, deterioration can be suppressed. Of the first transistors 31 to the thirteenth transistor 43, it is preferable to use a four-terminal thin film transistor for the first transistor 31, the sixth transistor 36 to the ninth transistor 39. 1st transistor 31, 6th transistor 36 to 9th transistor 3
The operation of 9 is a transistor that is required to switch the potential of the node to which one of the source or drain electrodes is connected by the control signal of the gate electrode, and the response to the control signal input to the gate electrode is fast ( It is a transistor that can reduce the malfunction of the pulse output circuit by making the on-current rise steep). Therefore, the threshold voltage can be controlled by using the 4-terminal thin film transistor 28, and the pulse output circuit can further reduce the malfunction.

In FIG. 14D, in the first transistor 31, the first terminal is electrically connected to the power supply line 51, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode. (Lower gate electrode and upper gate electrode) are electrically connected to the fourth input terminal 24. In the second transistor 32, the first terminal is electrically connected to the power line 53, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is the fourth transistor 34. It is electrically connected to the gate electrode. In the third transistor 33, the first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. In the fourth transistor 34, the first terminal is electrically connected to the power line 53, and the second terminal is electrically connected to the first output terminal 26. In the fifth transistor 35, the first terminal is electrically connected to the power line 53, the second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate is formed. The electrode is the 4th
It is electrically connected to the input terminal 24 of. In the sixth transistor 36, the first terminal is electrically connected to the power supply line 52, the second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate is formed. The electrodes (lower gate electrode and upper gate electrode) are electrically connected to the fifth input terminal 25. In the seventh transistor 37, the first terminal is electrically connected to the power line 52, and the second terminal is the eighth transistor 3.
It is electrically connected to the second terminal of No. 8, and the gate electrode (lower gate electrode and upper gate electrode) is electrically connected to the third input terminal 23. In the eighth transistor 38, the first terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and the gate electrode (lower gate electrode and upper gate electrode) is the second. It is electrically connected to the input terminal 22 of 2. In the ninth transistor 39, the first terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32, and the second terminal is second.
The terminals are electrically connected to the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40, and the gate electrodes (lower gate electrode and upper gate electrode) are connected to the power supply line 5.
It is electrically connected to 2. In the tenth transistor 40, the first terminal is electrically connected to the first input terminal 21, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is the ninth transistor 39. It is electrically connected to the second terminal. In the eleventh transistor 41, the first terminal is electrically connected to the power line 53, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is the gate electrode of the second transistor 32 and the gate electrode. It is electrically connected to the gate electrode of the fourth transistor 34. The twelfth transistor 42 is the first
The terminals are electrically connected to the power supply line 53, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is the gate electrode of the seventh transistor 37 (lower gate electrode and upper gate electrode). ) Is electrically connected. In the thirteenth transistor 43, the first terminal is electrically connected to the power supply line 53, the second terminal is electrically connected to the first output terminal 26, and the gate electrode is the gate electrode of the seventh transistor 37 (the gate electrode of the seventh transistor 37. It is electrically connected to the lower gate electrode and the upper gate electrode).

In FIG. 14D, the connection point of the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 40, and the second terminal of the ninth transistor 39 is referred to as a node A. Further, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34,
Node B is a connection point between the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, and the gate electrode of the eleventh transistor 41.

In FIG. 15 (A), the pulse output circuit described in FIG. 14 (B) is replaced with the first pulse output circuit 10_.
When applied to 1, the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26
And the signal input or output to the second output terminal 27 is shown.

Specifically, the first clock signal CK1 is input to the first input terminal 21, the second clock signal CK2 is input to the second input terminal 22, and the third clock is input to the third input terminal 23. The signal CK3 is input, a start pulse is input to the fourth input terminal 24, the subsequent signal OUT (3) is input to the fifth input terminal 25, and the first output signal OUT is input from the first output terminal 26.
(1) (SR) is output, and the second output signal OUT (1) is output from the second output terminal 27.

The thin film transistor is an element having at least three terminals including a gate, a drain, and a source. Further, it has a semiconductor in which a channel region is formed in a region superimposed on the gate, and by controlling the potential of the gate, it is possible to control the current flowing between the drain and the source via the channel region. Here, since the source and the drain change depending on the structure of the thin film transistor, operating conditions, and the like, it is difficult to limit which is the source or the drain. Therefore, the region that functions as a source and a drain may not be called a source or a drain. In that case, as an example, each is the first
It may be referred to as a terminal or a second terminal.

In FIGS. 14 (D) and 15 (A), a capacitive element for performing a bootstrap operation by putting the node A in a floating state may be separately provided. Further, in order to maintain the potential of the node B, a capacitive element in which one electrode is electrically connected to the node B may be separately provided.

Here, a timing chart of a shift register including a plurality of pulse output circuits shown in FIG. 15 (A) is shown in FIG. 15 (B). When the shift register is a scanning line drive circuit, the period 61 in FIG. 15B corresponds to the vertical blanking interval, and the period 62 corresponds to the gate selection period.

As shown in FIG. 15A, by providing the ninth transistor 39 to which the second power supply potential VCS is applied to the gate, there are the following advantages before and after the bootstrap operation. ..

When the gate electrode does not have the ninth transistor 39 to which the second power potential VCS is applied, when the potential of the node A rises due to the bootstrap operation, the second transistor 31 of the first transistor 31 is second.
The potential of the source, which is a terminal, rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 is switched to the first terminal side, that is, the power line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may cause deterioration of the transistor. Therefore, a ninth power supply potential VCS is applied to the gate electrode.
By providing the transistor 39 of the above, although the potential of the node A rises due to the bootstrap operation, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced. Therefore, by adopting the circuit configuration of the present embodiment, the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced, so that the deterioration of the first transistor 31 due to stress is suppressed. be able to.

In addition, about the place where the 9th transistor 39 is provided, the 2nd of the 1st transistor 31
The configuration may be such that the terminal and the gate of the third transistor 33 are connected to each other via the first terminal and the second terminal. In the case of the shift register including a plurality of pulse output circuits in the present embodiment, the ninth transistor 39 may be omitted in the signal line drive circuit having more stages than the scan line drive circuit, and the number of transistors is reduced. There is an advantage in that.

By using an oxide semiconductor as the semiconductor layer of the first transistor 31 to the thirteenth transistor 43, it is possible to reduce the off-current of the thin film, increase the on-current and the field effect mobility, and the degree of deterioration. Therefore, it is possible to reduce malfunctions in the circuit. Further, the transistor using an oxide semiconductor has a smaller degree of deterioration of the transistor due to the application of a high potential to the gate electrode than the transistor using amorphous silicon. Therefore, the same operation can be obtained even if the first power potential VDD is supplied to the power line that supplies the second power potential VCS, and the number of power lines that are routed between the circuits can be reduced. The circuit can be downsized.

The gate electrode of the seventh transistor 37 (lower gate electrode and upper gate electrode)
The clock signal supplied by the third input terminal 23 and the clock signal supplied by the second input terminal 22 to the gate electrode (lower gate electrode and upper gate electrode) of the eighth transistor 38 are the seventh. The clock signal supplied by the second input terminal 22 to the gate electrode of the transistor 37 (lower gate electrode and upper gate electrode), the gate electrode of the eighth transistor 38 (lower gate electrode and upper gate electrode). Third input terminal 23
Even if the connection relationship is exchanged so that the clock signal is supplied by, the same effect is obtained. At this time, in the shift register shown in FIG. 15A, the seventh transistor 37 and the eighth transistor 38 are both on, the seventh transistor 37 is off, and the eighth transistor 38 is turned on.
Transistor 38 is on, then the seventh transistor 37 is off, and the eighth transistor 38 is off, so that the second input terminal 22 and the third input terminal 2 are turned on.
The decrease in the potential of the node B caused by the decrease in the potential of 3 occurs twice due to the decrease in the potential of the gate electrode of the seventh transistor 37 and the decrease in the potential of the gate electrode of the eighth transistor 38. It will be. On the other hand, as shown in FIG. 15 (B), the shift register shown in FIG. 15 (A) is changed from the state in which both the seventh transistor 37 and the eighth transistor 38 are on to the seventh transistor.
Transistor 37 is on, the eighth transistor 38 is off, then the seventh transistor 37 is off, and the eighth transistor 38 is off, so that the second input terminal 22 and the third transistor 38 are in the off state. The decrease in the potential of the node B caused by the decrease in the potential of the input terminal 23 can be reduced to one time due to the decrease in the potential of the gate electrode of the eighth transistor 38. Therefore, a clock signal is supplied from the third input terminal 23 to the gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37, and the eighth transistor 38
It is preferable to have a wiring relationship in which a clock signal is supplied from the second input terminal 22 to the gate electrodes (lower gate electrode and upper gate electrode). This is because the number of fluctuations in the potential of the node B can be reduced and noise can be reduced.

In this way, the pulse output is configured so that the H level signal is periodically supplied to the node B during the period in which the potentials of the first output terminal 26 and the second output terminal 27 are held at the L level. It is possible to suppress the malfunction of the circuit.

(Embodiment 6)
A thin film transistor can be manufactured, and the thin film transistor can be used in a pixel portion and further in a drive circuit to manufacture a semiconductor device (also referred to as a display device) having a display function. Further, the thin film transistor can be integrally formed on a part or the whole of the drive circuit on the same substrate as the pixel portion to form a system on panel.

The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be used. The light emitting element includes an element whose brightness is controlled by a current or a voltage in the category, and specifically, an inorganic EL (Electr).
o Luminescence) element, organic EL element and the like are included. Further, a display medium whose contrast changes due to an electric action, such as electronic ink, can also be applied.

Further, the display device includes a panel in which the display element is sealed, and a module in which an IC or the like including a controller is mounted on the panel. Further, with respect to the element substrate corresponding to one form before the display element is completed in the process of manufacturing the display device, the element substrate is provided with means for supplying a current to the display element in each of a plurality of pixels. Specifically, the element substrate may be in a state in which only the pixel electrode of the display element is formed, or after the conductive film to be the pixel electrode is formed, the pixel electrode is formed by etching. It may be in the previous state,
All forms apply.

The display device in the present specification refers to an image display device, a display device, or a light source (including a lighting device). Also, a connector such as FPC (Flexible pr)
integrated cycle) or TAB (Tape Automated Bon)
A module with a ding) tape or TCP (Tape Carrier Package) attached, a module with a printed wiring board at the end of a TAB tape or TCP, or an IC (integrated circuit) on the display element by the COG (Chip On Glass) method. All directly mounted modules shall be included in the display device.

The appearance and cross section of the liquid crystal display panel corresponding to one form of the semiconductor device will be described with reference to FIG. 16 (A1) and 16 (A2) show a panel in which the thin film transistors 4010 and 4011 formed on the first substrate 4001 and the liquid crystal element 4013 are sealed between the thin film transistors 4010 and 4011 and the second substrate 4006 with a sealing material 4005. It is a plan view, and FIG. 16 (B) is a plan view of FIG. 16 (A1).
Corresponds to the cross-sectional view taken along the line MN of (A2).

A sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line drive circuit 4004. Further, a second substrate 4006 is provided on the pixel unit 4002 and the scanning line drive circuit 4004. Therefore, the pixel unit 4002 and the scanning line drive circuit 4004 are the first substrate 4001, the sealing material 4005, and the second substrate 4006.
It is sealed together with the liquid crystal layer 4008. Further, a signal line drive circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. Has been done.

The method of connecting the separately formed drive circuit is not particularly limited, and the COG method can be used.
A wire bonding method, a TAB method, or the like can be used. FIG. 16 (A1)
Is an example of mounting the signal line drive circuit 4003 by the COG method, and FIG. 16 (A2) shows.
This is an example of mounting the signal line drive circuit 4003 by the TAB method.

Further, the pixel unit 4002 provided on the first substrate 4001 and the scanning line drive circuit 4004 are
It has a plurality of thin film transistors, and in FIG. 16B, the thin film transistor 4010 included in the pixel unit 4002 and the thin film transistor 4011 included in the scanning line drive circuit 4004.
Is illustrated. Protective insulating layers 4020, 4 on the thin film transistors 4010, 4011
021 is installed.

As the thin film transistors 4010 and 4011, highly reliable thin film transistors including the oxide semiconductor layer shown in the first to fifth embodiments can be applied. The thin film transistor 4011 for the drive circuit includes the thin film transistors 180 and 1 shown in the first, second, and fourth embodiments.
81, 183, as the thin film transistor 4010 for pixels, the thin film transistor 170,
171, 173 can be used. In this embodiment, the thin film transistor 401
0 and 4011 are n-channel thin film transistors.

On the insulating layer 4021, the conductive layer 4040 is provided at a position overlapping the channel forming region of the oxide semiconductor layer of the thin film transistor 4011 for the drive circuit. By providing the conductive layer 4040 at a position overlapping the channel forming region of the oxide semiconductor layer, it is possible to reduce the amount of change in the threshold voltage of the thin film transistor 4011 before and after the BT test. again,
The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011, or may be the same.
It may be different and may function as a second gate electrode layer. Further, the potential of the conductive layer 4040 may be GND, 0V, or a floating state.

Further, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is the second substrate 40.
It is formed on 06. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap each other corresponds to the liquid crystal element 4013. The pixel electrode layer 4030 and the counter electrode layer 4031 are provided with insulating layers 4032 and 4033, which function as alignment films, respectively.
The liquid crystal layer 4008 is sandwiched between the insulating layers 4032 and 4033.

As the first substrate 4001 and the second substrate 4006, a translucent substrate can be used, and glass, ceramics, and plastic can be used. As plastic, FRP (Fiberglass-Reinforced Plastics) plate, PV
F (polyvinyl fluoride) film, polyester film or acrylic resin film can be used.

Further, 4035 is a columnar spacer obtained by selectively etching the insulating film.
It is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. A spherical spacer may be used. Further, the counter electrode layer 4031
Is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. Counter electrode layer 40 via conductive particles arranged between a pair of substrates using a common connection.
The 31 and the common potential line can be electrically connected. The conductive particles are the sealing material 40.
It is contained in 05.

Further, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase is expressed only in a narrow temperature range, a liquid crystal composition mixed with 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008 in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec.
Since it is as short as the following and is optically isotropic, no orientation treatment is required and the viewing angle dependence is small.

In addition to the transmissive liquid crystal display device, it can also be applied to a semi-transmissive liquid crystal display device.

Further, in the liquid crystal display device, an example is shown in which a polarizing plate is provided on the outside (visual side) of the substrate, a colored layer (color filter) is provided on the inside, and an electrode layer used for the display element is provided in this order. It may be provided. Further, the laminated structure of the polarizing plate and the colored layer is not limited to the present embodiment, and may be appropriately set depending on the material of the polarizing plate and the colored layer and the manufacturing process conditions. In addition to the display unit, a light-shielding film that functions as a black matrix may be provided.

Further, a protective insulating layer 4020 is formed on the thin film transistors 4010 and 4011. The protective insulating layer 4020 can be formed by the same material and method as the oxide insulating layer 107 shown in the first embodiment, but here, as the protective insulating layer 4020, a silicon nitride film is formed by an RF sputtering method. ..

Further, the insulating layer 4021 is formed as a flattening insulating film. The insulating layer 4021 may be formed of the same material and method as the flattened insulating layer 109 shown in the first embodiment, and may be made of acrylic.
A heat-resistant organic material such as polyimide, benzocyclobutene, polyamide, or epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphorus glass), BPSG (phosphorus glass) and the like can be used. The insulating layer 40 is formed by laminating a plurality of insulating films formed of these materials.
21 may be formed.

The method for forming the insulating layer 4021 is not particularly limited, and depending on the material thereof, a sputtering method, S.
An OG method, spin coating, dip, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater and the like can be used. By combining the firing process of the insulating layer 4021 and the annealing of the semiconductor layer, it is possible to efficiently manufacture a semiconductor device.

The pixel electrode layer 4030 and the counter electrode layer 4031 are indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and the like.
Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO),
A translucent conductive material such as indium zinc oxide or indium tin oxide to which silicon oxide is added can be used.

Further, the pixel electrode layer 4030 and the counter electrode layer 4031 can be formed by using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed by using the conductive composition preferably has a sheet resistance of 10000 Ω / □ or less and a light transmittance of 70% or more at a wavelength of 550 nm. Further, it is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω · cm or less.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more thereof can be mentioned.

Further, a separately formed signal line drive circuit 4003 and a scan line drive circuit 4004 or a pixel unit 4
Various signals and potentials given to 002 are supplied from FPC4018.

The connection terminal electrode 4015 is formed of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013, and the terminal electrode 4016 is formed of the same conductive film as the source electrode layer and drain electrode layer of the thin film transistor 4011.

The connection terminal electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019.

Further, FIG. 16 shows an example in which the signal line drive circuit 4003 is separately formed and mounted on the first substrate 4001, but the configuration is not limited to this. The scanning line drive circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

FIG. 17 shows an example of configuring a liquid crystal display module as a semiconductor device using a TFT substrate 2600 manufactured by the manufacturing method disclosed in the present specification.

FIG. 17 is an example of a liquid crystal display module, in which a TFT substrate 2600 and a facing substrate 2601 are fixed by a sealing material 2602, and a pixel portion 2603 including a TFT or the like, a display element 2604 including a liquid crystal layer, and a colored layer 2605 are arranged between them. It forms a display area. Colored layer 2605
Is required for color display, and in the case of the RGB method, colored layers corresponding to each of the red, green, and blue colors are arranged corresponding to each pixel. A polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged outside the TFT substrate 2600 and the facing substrate 2601. The light source is composed of a cold cathode fluorescent lamp 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit section 2608 of the TFT board 2600 by a flexible wiring board 2609, and an external circuit such as a control circuit and a power supply circuit is incorporated. There is. Further, the polarizing plate and the liquid crystal layer may be laminated with a retardation plate.

The liquid crystal display module has a TN (Twisted Nematic) mode and an IPS (I).
n-Plane-Switching) mode, FFS (Fringe Field S)
(witching) mode, MVA (Multi-domain Vertical A)
lignment) mode, PVA (Patterned Vertical Alig)
nment) mode, ASM (Axially symmetric aligned)
Micro-cell mode, OCB (Optical Compensated B)
irrefringence) mode, FLC (Ferroelectric Liquid Liqui)
d Crystal) mode, AFLC (AntiFerolectric Liq)
A uid Crystal) mode or the like can be used.

Through the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 7)
The semiconductor device disclosed in the present specification can be applied to an electronic book (electronic book), a poster, an in-vehicle advertisement of a vehicle such as a train, a display unit of various cards such as a credit card, and the like by having flexibility. An example of an electronic device is shown in FIG.

FIG. 18 shows an example of an electronic book. For example, the electronic book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are
It is integrated by the shaft portion 2711, and the opening / closing operation can be performed with the shaft portion 2711 as a shaft. With such a configuration, it becomes possible to perform an operation like a paper book.

A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 may be configured to display a continuous screen or may be configured to display different screens. By displaying different screens, for example, a text can be displayed on the right display unit (display unit 2705 in FIG. 18), and an image can be displayed on the left display unit (display unit 2707 in FIG. 18). ..

Further, FIG. 18 shows an example in which the housing 2701 is provided with an operation unit or the like. For example, housing 2
The 701 includes a power switch 2721, an operation key 2723, a speaker 2725, and the like. The page can be sent by the operation key 2723. A keyboard, a pointing device, or the like may be provided on the same surface as the display unit of the housing. Further, the back surface or the side surface of the housing may be provided with an external connection terminal (such as an earphone terminal, a USB terminal, or a terminal that can be connected to various cables such as an AC adapter and a USB cable), a recording medium insertion portion, and the like. .. Further, the electronic book 2700 may be configured to have a function as an electronic dictionary.

Further, the electronic book 2700 may be configured to be able to transmit and receive information wirelessly. By radio
It is also possible to purchase desired book data or the like from an electronic book server and download it.

(Embodiment 8)
The semiconductor device disclosed in the present specification can be applied to various electronic devices (including gaming machines). Examples of electronic devices include television devices (also referred to as televisions or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, and mobile phones (also referred to as mobile phones and mobile phone devices). ), Portable game machines, mobile information terminals, sound reproduction devices, large game machines such as pachinko machines, and the like.

FIG. 19A shows an example of a television device. The television device 9600 is
A display unit 9603 is incorporated in the housing 9601. The display unit 9603 can display an image. Further, here, a configuration in which the housing 9601 is supported by the stand 9605 is shown.

The operation of the television device 9600 can be performed by the operation switch provided in the housing 9601 or the remote control operation machine 9610 separately provided. The operation key 9609 provided in the remote control operation machine 9610 can be used to operate the channel and the volume, and can operate the image displayed on the display unit 9603. Further, the remote controller 9610 may be provided with a display unit 9607 for displaying information output from the remote controller 9610.

The television device 9600 is configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts, and by connecting to a wired or wireless communication network via a modem, one-way (sender to receiver) or two-way (sender and receiver). It is also possible to perform information communication between (or between receivers, etc.).

FIG. 19B shows an example of a digital photo frame. For example, in the digital photo frame 9700, the display unit 9703 is incorporated in the housing 9701. Display unit 970
3 can display various images, and for example, by displaying image data taken by a digital camera or the like, it can function in the same manner as a normal photo frame.

The digital photo frame 9700 has an operation unit and an external connection terminal (USB terminal, US).
It is configured to include a terminal that can be connected to various cables such as a B cable), a recording medium insertion part, and the like. These configurations may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side surface or the back surface because the design is improved. For example, digital photo frame 9700
A memory for storing image data taken by a digital camera can be inserted into the recording medium insertion unit to capture the image data, and the captured image data can be displayed on the display unit 9703.

Further, the digital photo frame 9700 may be configured to be able to transmit and receive information wirelessly. It is also possible to adopt a configuration in which desired image data is captured and displayed wirelessly.

FIG. 20A is a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891, and is openably and closably connected by a connecting portion 9893. A display unit 9882 is incorporated in the housing 9881, and a display unit 9883 is incorporated in the housing 9891. In addition, the portable gaming machine shown in FIG. 20A has a speaker unit 9884 and a recording medium insertion unit 988.
6. LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9)
888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature,
It is equipped with chemical substances, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays (including functions for measuring), microphone 9889) and the like. Of course, the configuration of the portable gaming machine is not limited to the above-mentioned one, and at least the configuration including the semiconductor device disclosed in the present specification may be used, and other auxiliary equipment may be appropriately provided. The portable gaming machine shown in FIG. 20A has a function of reading a program or data recorded on a recording medium and displaying it on a display unit, and wirelessly communicates with other portable gaming machines to share information. Has a function. The functions of the portable gaming machine shown in FIG. 20 (A) are not limited to this, and can have various functions.

FIG. 20B shows an example of a slot machine which is a large gaming machine. Slot machine 9
The 900 has a display unit 9903 incorporated in the housing 9901. Also, slot machine 9
The 900 is also an operation means such as a start lever and a stop switch, a coin slot, and a coin slot.
It is equipped with speakers and the like. Of course, the configuration of the slot machine 9900 is not limited to the above-mentioned one, and at least a configuration including the semiconductor device disclosed in the present specification may be used, and other auxiliary equipment may be appropriately provided.

FIG. 21 (A) is a perspective view showing an example of a portable computer.

In the portable computer of FIG. 21A, the upper housing 9301 having the display unit 9303 and the lower housing 9302 having the keyboard 9304 with the hinge unit connecting the upper housing 9301 and the lower housing 9302 closed. It is possible to put the above on top of each other, which is convenient to carry, and when the user inputs on the keyboard, the hinge unit can be opened and the input operation can be performed by looking at the display unit 9303.

Further, the lower housing 9302 has a pointing device 9306 for performing an input operation in addition to the keyboard 9304. Further, if the display unit 9303 is used as a touch input panel, an input operation can be performed by touching a part of the display unit. Further, the lower housing 9302 has a calculation function unit such as a CPU and a hard disk. Further, the lower housing 9302 is another device, for example, U.
It has an external connection port 9305 into which a communication cable conforming to the SB communication standard is inserted.

The upper housing 9301 has a display unit 93 that can be slid and stored inside the upper housing 9301.
It has 07, and a wide display screen can be realized. In addition, the display unit 93 that can be stored
The user can adjust the orientation of the screen of 07. Further, if the storable display unit 9307 is used as a touch input panel, the input operation can be performed by touching a part of the storable display unit.

The display unit 9303 or the retractable display unit 9307 uses a video display device such as a liquid crystal display panel, a light emitting display panel such as an organic light emitting element or an inorganic light emitting element.

Further, the portable computer of FIG. 21A can receive a television broadcast and display an image on the display unit 9303 or the display unit 9307 as a configuration including a receiver or the like. Further, with the hinge unit connecting the upper housing 9301 and the lower housing 9302 closed, the display unit 9307 is slid to expose the entire screen, and the screen angle is adjusted so that the user watches the television broadcast. You can also do it. In this case, the display unit 9 is set with the hinge unit open.
Since 303 is not displayed and only the circuit for displaying the television broadcast is activated, the power consumption can be minimized, which is useful for a portable computer having a limited battery capacity.

Further, FIG. 21B is a perspective view showing an example of a mobile phone having a form that can be worn on a user's arm like a wristwatch.

This mobile phone has at least a communication device having a telephone function, a main body having a battery, a band portion 9204 for attaching the main body to an arm, an adjustment unit 9205 for adjusting the fixed state of the band portion 9204 to the arm, a display unit 9201, and a speaker. It is composed of a 9207 and a microphone 9208.

In addition, the main body has an operation switch 9203, and associates each function with a power input switch, a display changeover switch, an image pickup start instruction switch, and for example, when a switch is pressed, a program for the Internet is started. Can be done.

The input operation of the mobile phone is performed by touching the display unit 9201 with a finger, an input pen, or the like, operating the operation switch 9203, or inputting voice to the microphone 9208. In addition, in FIG. 21B, the display button 9202 displayed on the display unit 9201 is illustrated, and input can be performed by touching it with a finger or the like.

Further, the main body has a camera unit 9206 having an imaging means for converting a subject image imaged through a photographing lens into an electronic image signal. It is not necessary to provide a camera unit in particular.

Further, the mobile phone shown in FIG. 21B can receive a television broadcast and display an image on the display unit 9201 as a configuration including a receiver for the television broadcast, and further, a storage device such as a memory or the like. As a configuration equipped with, a television broadcast can be recorded in a memory. In addition, FIG. 21 (B)
The mobile phone shown in the above may have a function of collecting location information such as GPS.

The display unit 9201 uses an image display device such as a liquid crystal display panel, a light emitting display panel such as an organic light emitting element or an inorganic light emitting element. Since the mobile phone shown in FIG. 21B is small and lightweight, the battery capacity is limited, and it is preferable that the display device used for the display unit 9201 uses a panel that can be driven with low power consumption.

Although FIG. 21B shows an electronic device of the type to be attached to the "arm", the electronic device is not particularly limited and may have a shape that can be carried.

(Embodiment 9)
In the present embodiment, as one embodiment of the semiconductor device, an example of the display device having the thin film transistors shown in the first to sixth embodiments will be described with reference to FIGS. 22 to 35. In this embodiment, an example of a liquid crystal display device using a liquid crystal element as a display element will be described with reference to FIGS. 22 to 35. The TFTs 628 and 629 used in the liquid crystal display devices of FIGS. 22 to 35 are the first and second embodiments.
The thin film transistor shown in 5 and 6 can be applied, and is a thin film transistor having high electrical characteristics and reliability that can be similarly produced in the steps shown in the first to sixth embodiments.

First, a VA (Vertical Alignment) type liquid crystal display device will be described. The VA type liquid crystal display device is a kind of method for controlling the arrangement of liquid crystal molecules in a liquid crystal display panel. The VA type liquid crystal display device is a system in which liquid crystal molecules face in the direction perpendicular to the panel surface when no voltage is applied. In this embodiment, the pixels are particularly divided into several areas (subpixels), and the molecules are devised to be tilted in different directions. This is called multi-domain or multi-domain design. In the following description, a liquid crystal display device considering a multi-domain design will be described.

23 and 24 show a pixel electrode and a counter electrode, respectively. Note that FIG. 23 is a plan view of the substrate side on which the pixel electrodes are formed, and FIG. 22 shows a cross-sectional structure corresponding to the cutting lines EF shown in the drawing. Further, FIG. 24 is a plan view of the substrate side on which the counter electrode is formed. In the following description, these figures will be referred to.

In FIG. 22, the substrate 600 on which the TFT 628, the pixel electrode layer 624 connected to the TFT 628, and the holding capacity portion 630 are formed, and the facing substrate 601 on which the facing electrode layer 640 and the like are formed are superposed, and the liquid crystal is injected. It shows the state.

A colored film 636 and a counter electrode layer 640 are formed on the facing substrate 601, and a protrusion 644 is formed on the facing electrode layer 640. An alignment film 648 is formed on the pixel electrode layer 624, and an alignment film 646 is also formed on the counter electrode layer 640 and the protrusion 644. A liquid crystal layer 650 is formed between the substrate 600 and the facing substrate 601.

As the spacer, a columnar spacer may be formed or a bead spacer may be sprayed. When the spacer is translucent, it may be formed on the pixel electrode layer 624 formed on the substrate 600.

On the substrate 600, the TFT 628, the pixel electrode layer 624 connected to the TFT 628, and the holding capacity portion 6
30 is formed. The pixel electrode layer 624 includes a TFT 628, wiring 616, and a holding capacity portion 6.
A contact hole 623 penetrating the insulating film 620 covering the insulating film 30 and the insulating film 622 covering the insulating film 620 are connected to the wiring 618. As the TFT 628, the thin film transistors shown in the first to sixth embodiments can be appropriately used. Further, the holding capacitance portion 630 is composed of a first capacitive wiring 604 formed at the same time as the gate wiring 602 of the TFT 628, a gate insulating layer 606, and a second capacitive wiring 617 formed at the same time as the wiring 618.

A liquid crystal element is formed by overlapping the pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640.

FIG. 23 shows the structure on the substrate 600. The pixel electrode layer 624 is formed by using the material shown in the first embodiment. The pixel electrode layer 624 is provided with a slit 625. The slit 625 is for controlling the orientation of the liquid crystal display.

The TFT 629 shown in FIG. 23, the pixel electrode layer 626 connected to the TFT 629, and the holding capacity unit 631 are
They can be formed in the same manner as the TFT 628, the pixel electrode layer 624, and the holding capacity portion 630, respectively. Both TFT 628 and TFT 629 are connected to wiring 616. The pixels of this liquid crystal display panel are composed of a pixel electrode layer 624 and a pixel electrode layer 626. The pixel electrode layer 624 and the pixel electrode layer 626 are sub-pixels.

FIG. 24 shows a planar structure on the opposite substrate side. A counter electrode layer 640 is formed on the light-shielding film 632. The counter electrode layer 640 is preferably formed by using the same material as the pixel electrode layer 624. A protrusion 644 that controls the orientation of the liquid crystal is formed on the counter electrode layer 640. In FIG. 24, the pixel electrode layer 624 and the pixel electrode layer 626 formed on the substrate 600 are shown by broken lines, and the counter electrode layer 640 and the pixel electrode layer 624 and the pixel electrode layer 626 are arranged so as to overlap each other. Shows.

The equivalent circuit of this pixel structure is shown in FIG. Both TFT 628 and TFT 629 are connected to the gate wiring 602 and the wiring 616. In this case, by making the potentials of the capacitive wiring 604 and the capacitive wiring 605 different, the operations of the liquid crystal element 651 and the liquid crystal element 652 can be made different. That is, by individually controlling the potentials of the capacitive wiring 604 and the capacitive wiring 605, the orientation of the liquid crystal is precisely controlled to widen the viewing angle.

When a voltage is applied to the pixel electrode layer 624 provided with the slit 625, electric field distortion (oblique electric field) is generated in the vicinity of the slit 625. By arranging the slit 625 and the protrusion 644 on the facing substrate 601 side so as to alternately mesh with each other, an oblique electric field is effectively generated to control the orientation of the liquid crystal, thereby locating the direction in which the liquid crystal is oriented. Different by. That is,
The viewing angle of the liquid crystal display panel is widened by making it multi-domain.

Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 26 to 29.

26 and 27 show the pixel structure of the VA type liquid crystal display panel. FIG. 27 shows the substrate 600.
It is a plan view of FIG. 26, and the cross-sectional structure corresponding to the cutting line YZ shown in the figure is shown in FIG.

In this pixel structure, one pixel has a plurality of pixel electrodes, and a TFT is connected to each pixel electrode. Each TFT is configured to be driven by a different gate signal. That is, it has a configuration in which the signals applied to the individual pixel electrodes are independently controlled in the multi-domain designed pixel.

The pixel electrode layer 624 is connected to the TFT 628 by wiring 618 in the contact hole 623 penetrating the insulating film 620 and the insulating film 622, respectively. Further, the pixel electrode layer 62
Reference numeral 6 is connected to the TFT 629 by wiring 619 in the contact hole 627 penetrating the insulating film 620 and the insulating film 622, respectively. With the gate wiring 602 of TFT 628,
The gate wiring 603 of the TFT 629 is separated so that different gate signals can be given. On the other hand, the wiring 616 that functions as a data line includes the TFT 628 and the TFT 62.
It is commonly used in 9. As the TFT 628 and the TFT 629, the thin film transistors shown in the first to sixth embodiments can be appropriately used. The gate wiring 602 and the gate wiring 603
A gate insulating layer 606 is formed on the gate insulating layer 606.

The shapes of the pixel electrode layer 624 and the pixel electrode layer 626 are different, and they are separated by a slit 625. The pixel electrode layer 626 is formed so as to surround the outside of the pixel electrode layer 624 extending in a V shape. The voltage applied to the pixel electrode layer 624 and the pixel electrode layer 626 is set to TFT 628.
And the orientation of the liquid crystal is controlled by making them different by TFT 629. The equivalent circuit of this pixel structure is shown in FIG. The TFT 628 is connected to the gate wiring 602, and the TFT 629 is connected to the gate wiring 603. Further, both TFT 628 and TFT 629 are wired 616.
It is connected to the capacitance wiring 660 via the capacitance. By giving different gate signals to the gate wiring 602 and the gate wiring 603, the operations of the liquid crystal element 651 and the liquid crystal element 652 can be made different. That is, by individually controlling the operations of the TFT 628 and the TFT 629, the orientation of the liquid crystal can be precisely controlled to widen the viewing angle.

A colored film 636 and a facing electrode layer 640 are formed on the facing substrate 601. Further, a flattening film 637 is formed between the colored film 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. FIG. 28 shows the structure on the facing substrate side. The counter electrode layer 640 is an electrode that is common among different pixels, but a slit 641 is formed. By arranging the slit 641 and the slits 624 on the pixel electrode layer 624 side and the slits 625 on the pixel electrode layer 626 side alternately, an oblique electric field can be effectively generated and the orientation of the liquid crystal can be controlled. As a result, the direction in which the liquid crystal is oriented can be changed depending on the location, and the viewing angle is widened. In FIG. 28, the pixel electrode layer 624 and the pixel electrode layer 626 formed on the substrate 600 are shown by broken lines, and the counter electrode layer 640, the pixel electrode layer 624, and the pixel electrode layer 626 are arranged so as to overlap each other. Shows.

An alignment film 648 is formed on the pixel electrode layer 624 and the pixel electrode layer 626, and similarly, an alignment film 646 is formed on the counter electrode layer 640. A liquid crystal layer 650 is formed between the substrate 600 and the facing substrate 601. Further, the pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640
The first liquid crystal element is formed by overlapping the above. Further, a second liquid crystal element is formed by overlapping the pixel electrode layer 626, the liquid crystal layer 650, and the counter electrode layer 640. The pixel structure of the display panel described with reference to FIGS. 30 to 33 is a multi-domain structure in which a first liquid crystal element and a second liquid crystal element are provided in one pixel.

Next, a horizontal electric field type liquid crystal display device will be described. The lateral electric field method is a method of driving a liquid crystal to express gradation by applying an electric field in the horizontal direction to the liquid crystal molecules in the cell. According to this method, the viewing angle can be widened to about 180 degrees. In the following description, a liquid crystal display device that employs a transverse electric field method will be described.

FIG. 30 shows a state in which the substrate 600 on which the pixel electrode layer 624 connected to the electrode layer 607, the TFT 628, and the TFT 628 is formed is superposed on the facing substrate 601 and the liquid crystal is injected. A colored film 636, a flattening film 637, and the like are formed on the facing substrate 601. The facing electrode layer is not provided on the facing substrate 601 side. Further, a liquid crystal layer 650 is formed between the substrate 600 and the facing substrate 601 via the alignment film 646 and the alignment film 648.

On the substrate 600, the electrode layer 607, the capacitive wiring 604 connected to the electrode layer 607, and the T.
FT628 is formed. The capacitive wiring 604 can be formed at the same time as the gate wiring 602 of the TFT 628. As the TFT 628, the thin film transistor shown in the first to sixth embodiments can be applied. As the electrode layer 607, the same material as the pixel electrode layer shown in the first to sixth embodiments can be used. Further, the electrode layer 607 is formed in a shape partitioned into a substantially pixel shape. A gate insulating layer 606 is formed on the electrode layer 607 and the capacitive wiring 604.

Wiring 616 and wiring 618 of the TFT 628 are formed on the gate insulating layer 606. Wiring 61
Reference numeral 6 is a data line on which a video signal is placed on the liquid crystal display panel, which is a wiring extending in one direction, and at the same time, is connected to the source region or the drain region of the TFT 628 and serves as one of the electrodes of the source and the drain. The wiring 618 is a wiring that serves as the other electrode of the source and the drain and is connected to the pixel electrode layer 624.

An insulating film 620 is formed on the wiring 616 and the wiring 618. Further, on the insulating film 620, a pixel electrode layer 624 connected to the wiring 618 is formed via the contact hole 623 formed in the insulating film 620. The pixel electrode layer 624 is formed by using the same material as the pixel electrodes shown in the first to sixth embodiments.

In this way, the TFT 628 and the pixel electrode layer 624 connected to the TFT 628 are formed on the substrate 600. The holding capacity is formed between the electrode layer 607 and the pixel electrode layer 624.

FIG. 31 is a plan view showing the configuration of the pixel electrodes. The cross-sectional structure corresponding to the cutting line OP shown in FIG. 31 is shown in FIG. The pixel electrode layer 624 is provided with a slit 625. The slit 625 is for controlling the orientation of the liquid crystal display. In this case, an electric field is generated between the electrode layer 607 and the pixel electrode layer 624. A gate insulating layer 606 is formed between the electrode layer 607 and the pixel electrode layer 624, but the thickness of the gate insulating layer 606 is 50 to 200 nm, and 2
Since it is sufficiently thin as compared with the thickness of the liquid crystal layer of about 10 μm, an electric field is generated in a direction substantially parallel to the substrate 600 (horizontal direction). The orientation of the liquid crystal is controlled by this electric field. Liquid crystal molecules are rotated horizontally using an electric field in a direction substantially parallel to this substrate. In this case, since the liquid crystal molecules are horizontal in any state, the influence of the viewing angle such as contrast is small, and the viewing angle is widened. Further, since both the electrode layer 607 and the pixel electrode layer 624 are translucent electrodes, the aperture ratio can be improved.

Next, another example of the horizontal electric field type liquid crystal display device will be described.

32 and 33 show the pixel structure of the IPS type liquid crystal display device. FIG. 33 is a plan view, and FIG. 32 shows a cross-sectional structure corresponding to the cutting line VW shown in the drawing. In the following description, both figures will be referred to.

FIG. 32 shows the substrate 600 on which the TFT 628 and the pixel electrode layer 624 connected to the TFT 628 are formed.
The state in which the facing substrate 601 is overlapped and the liquid crystal is injected is shown. On the facing board 601
A colored film 636, a flattening film 637, and the like are formed. The facing electrode layer is not provided on the facing substrate 601 side. A liquid crystal layer 650 is formed between the substrate 600 and the facing substrate 601 via the alignment film 646 and the alignment film 648.

A common potential line 609 and a TFT 628 are formed on the substrate 600. Common potential line 60
9 can be formed at the same time as the gate wiring 602 of the TFT 628. As the TFT 628, the thin film transistor shown in the first to sixth embodiments can be applied.

Wiring 616 and wiring 618 of the TFT 628 are formed on the gate insulating layer 606. Wiring 61
Reference numeral 6 is a data line on which a video signal is placed on the liquid crystal display panel, which is a wiring extending in one direction, and at the same time, is connected to the source region or the drain region of the TFT 628 and serves as one of the electrodes of the source and the drain. The wiring 618 is a wiring that serves as the other electrode of the source and the drain and is connected to the pixel electrode layer 624.

An insulating film 620 and an insulating film 621 are formed on the wiring 616 and the wiring 618. Further, on the insulating film 620, the wiring 618 is passed through the contact hole 623 formed in the insulating film 620.
A pixel electrode layer 624 connected to is formed. The pixel electrode layer 624 is formed by using the same material as the pixel electrodes shown in the first to sixth embodiments. As shown in FIG. 33, the pixel electrode layer 6
24 is formed so as to generate a transverse electric field with the comb-shaped electrode formed at the same time as the common potential line 609. Further, the comb-teeth portion of the pixel electrode layer 624 is formed so as to alternately mesh with the comb-shaped electrode formed at the same time as the common potential line 609.

When an electric field is generated between the potential applied to the pixel electrode layer 624 and the potential of the common potential line 609,
The orientation of the liquid crystal is controlled by this electric field. Liquid crystal molecules are rotated horizontally using an electric field in a direction substantially parallel to this substrate. In this case, since the liquid crystal molecules are horizontal in any state, the influence of the viewing angle such as contrast is small, and the viewing angle is widened.

In this way, the TFT 628 and the pixel electrode layer 624 connected to the TFT 628 are formed on the substrate 600. The holding capacitance is formed by providing a gate insulating layer 606 between the common potential line 609 and the capacitance electrode 615. The capacitive electrode 615 and the pixel electrode layer 624 are contact holes 63.
It is connected via 3.

Next, the form of the TN type liquid crystal display device will be described.

34 and 35 show the pixel structure of the TN type liquid crystal display device. FIG. 35 is a plan view, and FIG. 34 shows a cross-sectional structure corresponding to the cutting line KL shown in the figure. In the following description, both figures will be referred to.

The pixel electrode layer 624 is a contact hole 623 formed in the second gate insulating layer 606b.
And is connected to TFT 628 via wiring 618. Wiring 61 that functions as a data line
6 is connected to TFT 628. As the TFT 628, any of the TFTs shown in the first to sixth embodiments can be applied.

The pixel electrode layer 624 is formed by using the pixel electrodes shown in the first to sixth embodiments. The capacitive wiring 604 can be formed at the same time as the gate wiring 602 of the TFT 628. A first gate insulating layer 606a and a second gate insulating layer 6 are placed on the gate wiring 602 and the capacitive wiring 604.
06b is formed. The holding capacitance is formed between the capacitive wiring 604 and the capacitive electrode 615 via a first gate insulating layer 606a and a second gate insulating layer 606b. The capacitive electrode 615 and the pixel electrode layer 624 are connected via a contact hole 623.

A colored film 636 and a facing electrode layer 640 are formed on the facing substrate 601. Further, a flattening film 637 is formed between the colored film 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. The liquid crystal layer 650 is formed between the pixel electrode layer 624 and the counter electrode layer 640 via the alignment film 648 and the alignment film 646.

A liquid crystal element is formed by overlapping the pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640.

Further, the colored film 636 may be formed on the substrate 600 side. Further, a polarizing plate is attached to the surface of the substrate 600 opposite to the surface on which the thin film transistor is formed, and the facing substrate 601 is formed.
A polarizing plate is attached to the surface opposite to the surface on which the counter electrode layer 640 is formed.

By the above steps, a liquid crystal display device can be manufactured as a display device.

10 Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 Input terminal 25 Input terminal 26 Output terminal 27 Output terminal 28 Thin film 31 Transistor 32 Transistor 33 Transistor 34 Transistor 35 Transistor 36 Transistor 37 Transistor 38 Transistor 39 Transistor 40 Transistor 41 Transistor 42 Transistor 51 Power line 52 Power line 53 Power line 83 Translucent substrate 84 Light-shielding part 85 Diffraction grid 86 Light transmission 87 Semi-transmissive part 88 Light-shielding part 89 Light transmission 100 Substrate 101 Electrode 102 Gate insulating layer 103 Oxide semiconductor layer 107 Oxide insulating layer 108 Capacitive wiring layer 109 Flattening insulating layer 110 Pixel electrode layer 111 Conductive layer 116 Channel forming region 118 Contact hole 119 Contact hole 120 Oxide semiconductor layer 121 Terminal 122 Terminal 125 Contact hole 126 Contact hole 127 Contact hole 128 Terminal electrode 129 Terminal electrode 130 Oxide semiconductor layer 131 Oxide semiconductor layer 133 Oxide semiconductor layer 134 Oxide semiconductor layer 137 Metal conductive layer 139 Oxide conductive layer 140 Oxide conductive layer 145 Wiring layer 145 Capacity 146 Capacity 147 Capacity 148 Capacity 150 Terminal 151 Terminal 152 Gate insulating layer 153 Connection electrode 154 Protective insulating layer 155 Conductive 156 Electrode 157 Oxide semiconductor layer 158 Oxide semiconductor layer 161 Gate electrode layer 162 Conductive layer 162 Wiring Layer 163 Oxide semiconductor layer 166 Channel formation region 168 Oxide semiconductor layer 170 Thin film 171 Thin film 173 Thin film 175 Oxide conductive layer 177 Oxide conductive layer 180 Thin film 181 Thin film 183 Thin film 183 Thin film 185 Metal conductive layer 190 Substrate 190 Opposing substrate 191 Insulation layer 192 Liquid crystal layer 193 Insulation layer 194 Opposing electrode layer 195 Colored layer 202 Gate insulating layer 203 Protective insulating layer 205 Common potential line 206 Common electrode layer 210 Oxide semiconductor layer 220 Thin film 227 Pixel electrode layer 402 Gate insulating layer 600 Substrate 601 Opposing substrate 602 Gate Wiring 603 Gate wiring 604 Capacitive wiring 605 Capacitive wiring 606 Gate insulation layer 607 Electrode layer 6 09 Common potential line 615 Capacitive electrode 616 Wiring 617 Wiring 618 Wiring 619 Wiring 620 Insulation film 621 Insulation film 622 Insulation film 623 Contact hole 624 Pixel electrode layer 625 Slit 626 Pixel electrode layer 627 Contact hole 628 TFT
629 TFT
630 Retaining capacity part 630 Capacity wiring 631 Retaining capacity part 632 Light-shielding film 633 Contact hole 636 Colored film 637 Flattening film 640 Opposing electrode layer 641 Slit 644 Protrusions 646 Alignment film 648 Alignment film 650 Liquid crystal layer 651 Liquid crystal element 652 Liquid crystal element 660 Capacity wiring 81a Gray tone mask 81b Halftone mask 104a Oxide conductive layer 104b Oxide conductive layer 105a Source electrode layer 105b Drain electrode layer 117a High resistance source region 117b High resistance drain region 135a Resist mask 135b Resist mask 136a Resist mask 136c Resist mask 164a Oxidation Object Conductive layer 164b Oxide conductive layer 165a Source electrode layer 165b Drain electrode layer 167a High resistance source region 167b High resistance drain region 196a Plate plate 2600 TFT substrate 2601 Opposing substrate 2602 Sealing material 2603 Pixel part 2604 Display element 2605 Colored layer 2606 Plate plate 2607 Thin film transistor 2608 Wiring circuit part 2609 Flexible wiring board 2610 Cold cathode tube 2611 Reflector plate 2612 Circuit board 2613 Diffuse board 2700 Electronic book 2701 Case 2703 Case 2705 Display part 2707 Display part 2711 Shaft part 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel part 4003 Signal line drive circuit 4004 Scanning line drive circuit 4005 Sealing material 4006 Substrate 4008 Liquid film layer 4010 Thin film transistor 4011 Thin film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC
4019 Anisotropic conductive film 4020 Protective insulation layer 4021 Insulation layer 4030 Speaker electrode layer 4031 Opposite electrode layer 4032 Insulation layer 4040 Conductive layer 5300 On board 5300 Board 5301 Speaker part 5302 Scan line drive circuit 5303 Scan line drive circuit 5304 Signal line drive circuit 5305 Timing control circuit 5601 Shift register 5602 Switching circuit 5603 Thin film 5604 Wiring 5605 Wiring 606a Gate insulation layer 606b Gate insulation layer 9201 Display unit 9202 Display button 9203 Operation switch 9205 Adjustment unit 9206 Camera unit 9207 Speaker 9208 Microphone 9301 Upper housing 9302 Lower casing Body 9303 Display unit 9304 Keyboard 9305 External connection port 9306 Pointing device 9307 Display unit 9600 Television device 9601 Housing 9603 Display unit 9605 Stand 9607 Display unit 9609 Operation key 9610 Remote control operation machine 9700 Digital photo frame 9701 Housing 9703 Display unit 9881 Body 9882 Display unit 9883 Display unit 9884 Speaker unit 988 5 Operation key 9886 Recording medium insertion unit 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED lamp 9891 Housing 9893 Connection unit 9900 Slot machine 9901 Housing 9903 Display unit

Claims (2)

A pixel unit having a transistor, a pixel electrode electrically connected to the transistor, and a capacitive element.
It has a connection portion located outside the pixel portion, and has.
The transistor has a first conductive layer in contact with the upper surface of a glass substrate, a first insulating film having a region in contact with the upper surface of the first conductive layer , and the first insulating film via the first insulating film. A first oxide semiconductor layer having a region overlapping with one conductive layer, and a first oxide conductive layer and a second oxide conductive layer having a region in contact with the upper surface of the first oxide semiconductor layer. It has a second conductive layer having a region in contact with the upper surface of the first oxide conductive layer, and a third conductive layer having a region in contact with the upper surface of the second oxide conductive layer .
The first conductive layer has a function as a gate electrode of the transistor and has a function.
The second conductive layer has a function as one of a source electrode and a drain electrode of the transistor.
The third conductive layer has a function as the other of the source electrode and the drain electrode of the transistor.
It has a second insulating film having a region in contact with the upper surface of the second conductive layer and a region in contact with the upper surface of the third conductive layer.
The capacitive element has a fourth conductive layer in contact with the upper surface of the glass substrate, and the second oxide conductive layer located on the fourth conductive layer via the first insulating film. death,
The connection portion includes a fifth conductive layer that is in contact with the upper surface of the glass substrate and has the same material as the first conductive layer, and a second oxide semiconductor layer located above the fifth conductive layer . A sixth conductive layer located above the second oxide semiconductor layer and having the same material as the second conductive layer and the third conductive layer, and above the sixth conductive layer . A seventh conductive layer having a region in contact with the upper surface of the second insulating film .
The first insulating film has a first opening for electrically connecting the fifth conductive layer and the sixth conductive layer.
The second insulating film has a second opening for electrically connecting the sixth conductive layer and the seventh conductive layer.
In a plan view, the first opening and the second opening do not overlap, and the first opening does not overlap.
The first oxide semiconductor layer has a region that does not overlap with the first conductive layer and whose upper surface is in contact with the second insulating film.
The second oxide semiconductor layer has a region that overlaps with the fifth conductive layer and has an upper surface in contact with the second insulating film.
A display device in which both ends of the third conductive layer are located on the first oxide semiconductor layer in a cross-sectional view of the transistor in the channel length direction . A pixel portion having a transistor and a pixel electrode electrically connected to the transistor,
It has a connection portion located outside the pixel portion, and has.
The transistor has a first conductive layer in contact with the upper surface of a glass substrate, a first insulating film having a region in contact with the upper surface of the first conductive layer, and the first insulating film via the first insulating film. A first oxide semiconductor layer having a region overlapping with the conductive layer of the above, a first oxide conductive layer and a second oxide conductive layer having a region in contact with the upper surface of the first oxide semiconductor layer, and the above-mentioned It has a second conductive layer having a region in contact with the upper surface of the first oxide conductive layer, and a third conductive layer having a region in contact with the upper surface of the second oxide conductive layer.
The first conductive layer has a function as a gate electrode of the transistor and has a function.
The second conductive layer has a function as one of a source electrode and a drain electrode of the transistor.
The third conductive layer has a function as the other of the source electrode and the drain electrode of the transistor.
It has a second insulating film having a region in contact with the upper surface of the second conductive layer and a region in contact with the upper surface of the third conductive layer.
The connection portion includes a fourth conductive layer that is in contact with the upper surface of the glass substrate and has the same material as the first conductive layer, and a second oxide semiconductor layer located above the fourth conductive layer. It is located above the second oxide semiconductor layer, the fifth conductive layer having the same material as the second conductive layer and the third conductive layer, and above the fifth conductive layer. A sixth conductive layer having a region in contact with the upper surface of the second insulating film.
The first insulating film has a first opening for electrically connecting the fourth conductive layer and the fifth conductive layer.
The second insulating film has a second opening for electrically connecting the fifth conductive layer and the sixth conductive layer.
In a plan view, the first opening and the second opening do not overlap, and the first opening does not overlap.
The first oxide semiconductor layer has a region that does not overlap with the first conductive layer and whose upper surface is in contact with the second insulating film.
The second oxide semiconductor layer has a region that overlaps with the fourth conductive layer and has an upper surface in contact with the second insulating film.
A display device in which both ends of the third conductive layer are located on the first oxide semiconductor layer in a cross-sectional view of the transistor in the channel length direction.

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