JP6752905B2 - フィンカウントに基づく拡散のための標準セルアーキテクチャ - Google Patents

フィンカウントに基づく拡散のための標準セルアーキテクチャ Download PDF

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JP6752905B2
JP6752905B2 JP2018566482A JP2018566482A JP6752905B2 JP 6752905 B2 JP6752905 B2 JP 6752905B2 JP 2018566482 A JP2018566482 A JP 2018566482A JP 2018566482 A JP2018566482 A JP 2018566482A JP 6752905 B2 JP6752905 B2 JP 6752905B2
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diffusion
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cell
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diffusion regions
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JP2019519114A5 (enExample
JP2019519114A (ja
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アンソニー・コッレアーレ・ジュニア
ベンジャミン・バウアーズ
トレーシー・デラ・ロヴァ
ウィリアム・グドール・ザ・サード
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クアルコム，インコーポレイテッド
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/853—Complementary IGFETs, e.g. CMOS comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10W20/20—
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Peptides Or Proteins (AREA)
  • Error Detection And Correction (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
JP2018566482A 2016-06-22 2017-06-22 フィンカウントに基づく拡散のための標準セルアーキテクチャ Active JP6752905B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662353536P 2016-06-22 2016-06-22
US62/353,536 2016-06-22
US15/629,728 2017-06-21
US15/629,728 US10366196B2 (en) 2016-06-22 2017-06-21 Standard cell architecture for diffusion based on fin count
PCT/US2017/038730 WO2018013315A1 (en) 2016-06-22 2017-06-22 Standard cell architecture for diffusion based on fin count

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JP2019519114A JP2019519114A (ja) 2019-07-04
JP2019519114A5 JP2019519114A5 (enExample) 2019-11-28
JP6752905B2 true JP6752905B2 (ja) 2020-09-09

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US (2) US10236302B2 (enExample)
EP (2) EP3475984A1 (enExample)
JP (2) JP6752905B2 (enExample)
KR (2) KR102083190B1 (enExample)
CN (2) CN109314110B (enExample)
CA (1) CA3024332C (enExample)
SG (1) SG11201810054RA (enExample)
WO (2) WO2018013315A1 (enExample)

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BR112018075720A2 (pt) 2019-03-26
US20170373090A1 (en) 2017-12-28
US20170371995A1 (en) 2017-12-28
US10236302B2 (en) 2019-03-19
CA3024332C (en) 2021-09-14
CN109314109A (zh) 2019-02-05
EP3475983A1 (en) 2019-05-01
KR20190019952A (ko) 2019-02-27
JP6972031B2 (ja) 2021-11-24
EP3475984A1 (en) 2019-05-01
BR112018075596A2 (pt) 2019-03-26
CA3024332A1 (en) 2017-12-28
CN109314109B (zh) 2023-08-11
KR102528329B1 (ko) 2023-05-02
WO2018013315A1 (en) 2018-01-18
JP2019519110A (ja) 2019-07-04
WO2017223295A1 (en) 2017-12-28
KR20190020682A (ko) 2019-03-04
JP2019519114A (ja) 2019-07-04
US10366196B2 (en) 2019-07-30
CN109314110B (zh) 2023-06-13
SG11201810054RA (en) 2019-01-30
KR102083190B1 (ko) 2020-03-02
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