JP2019519114A5 - - Google Patents
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- JP2019519114A5 JP2019519114A5 JP2018566482A JP2018566482A JP2019519114A5 JP 2019519114 A5 JP2019519114 A5 JP 2019519114A5 JP 2018566482 A JP2018566482 A JP 2018566482A JP 2018566482 A JP2018566482 A JP 2018566482A JP 2019519114 A5 JP2019519114 A5 JP 2019519114A5
- Authority
- JP
- Japan
- Prior art keywords
- logic cell
- diffusion region
- diffusion
- full row
- diffusion regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009792 diffusion process Methods 0.000 claims 135
- 238000000034 method Methods 0.000 claims 35
- 239000007943 implant Substances 0.000 claims 3
- 239000002184 metal Substances 0.000 claims 3
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201662353536P | 2016-06-22 | 2016-06-22 | |
| US62/353,536 | 2016-06-22 | ||
| US15/629,728 | 2017-06-21 | ||
| US15/629,728 US10366196B2 (en) | 2016-06-22 | 2017-06-21 | Standard cell architecture for diffusion based on fin count |
| PCT/US2017/038730 WO2018013315A1 (en) | 2016-06-22 | 2017-06-22 | Standard cell architecture for diffusion based on fin count |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019519114A JP2019519114A (ja) | 2019-07-04 |
| JP2019519114A5 true JP2019519114A5 (enExample) | 2019-11-28 |
| JP6752905B2 JP6752905B2 (ja) | 2020-09-09 |
Family
ID=60675625
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018566482A Active JP6752905B2 (ja) | 2016-06-22 | 2017-06-22 | フィンカウントに基づく拡散のための標準セルアーキテクチャ |
| JP2018563676A Active JP6972031B2 (ja) | 2016-06-22 | 2017-06-22 | フィンカウントに基づく拡散のための標準セルアーキテクチャ |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018563676A Active JP6972031B2 (ja) | 2016-06-22 | 2017-06-22 | フィンカウントに基づく拡散のための標準セルアーキテクチャ |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US10236302B2 (enExample) |
| EP (2) | EP3475984A1 (enExample) |
| JP (2) | JP6752905B2 (enExample) |
| KR (2) | KR102083190B1 (enExample) |
| CN (2) | CN109314110B (enExample) |
| CA (1) | CA3024332C (enExample) |
| SG (1) | SG11201810054RA (enExample) |
| WO (2) | WO2018013315A1 (enExample) |
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| US10236302B2 (en) | 2016-06-22 | 2019-03-19 | Qualcomm Incorporated | Standard cell architecture for diffusion based on fin count |
| US11347925B2 (en) | 2017-05-01 | 2022-05-31 | Advanced Micro Devices, Inc. | Power grid architecture and optimization with EUV lithography |
| US11211330B2 (en) * | 2017-05-01 | 2021-12-28 | Advanced Micro Devices, Inc. | Standard cell layout architectures and drawing styles for 5nm and beyond |
| DE102018108836B4 (de) | 2017-11-14 | 2023-10-05 | Taiwan Semiconductor Manufacturing Co. Ltd. | Halbleitervorrichtungen mit standardzellen |
| US11011545B2 (en) | 2017-11-14 | 2021-05-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including standard cells |
| KR102465964B1 (ko) | 2018-05-18 | 2022-11-10 | 삼성전자주식회사 | 다중 높이 셀을 포함하는 집적 회로 및 이를 제조하기 위한 방법 |
| KR102560368B1 (ko) | 2018-06-20 | 2023-07-27 | 삼성전자주식회사 | 확산 방지 영역을 구비하는 반도체 소자 |
| US10522542B1 (en) | 2018-06-28 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Double rule integrated circuit layouts for a dual transmission gate |
| US10797078B2 (en) * | 2018-08-14 | 2020-10-06 | Taiwan Semiconductor Manufacturing Company Limited | Hybrid fin field-effect transistor cell structures and related methods |
| KR102599048B1 (ko) | 2018-08-16 | 2023-11-06 | 삼성전자주식회사 | 표준 셀을 포함하는 집적 회로 및 이를 제조하기 위한 방법 |
| US10783313B2 (en) * | 2018-08-30 | 2020-09-22 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for improved cut metal patterning |
| DE102019125739B4 (de) | 2018-09-28 | 2025-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Halbleitervorrichtung mit zellregion, verfahren zum erzeugen eines layoutdiagramms und systems für dasselbe |
| US10977418B2 (en) | 2018-09-28 | 2021-04-13 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device with cell region, method of generating layout diagram and system for same |
| US10700065B2 (en) | 2018-10-10 | 2020-06-30 | Apple Inc. | Leakage current reduction in electrical isolation gate structures |
| KR102539066B1 (ko) * | 2018-11-09 | 2023-06-01 | 삼성전자주식회사 | 서로 다른 타입의 셀들을 포함하는 집적 회로, 그 설계 방법 및 설계 시스템 |
| US11030381B2 (en) | 2019-01-16 | 2021-06-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Leakage analysis on semiconductor device |
| KR102556811B1 (ko) | 2019-01-25 | 2023-07-18 | 삼성전자주식회사 | 반도체 장치 |
| KR102635671B1 (ko) * | 2019-03-21 | 2024-02-14 | 에스케이하이닉스 주식회사 | 반도체 장치 |
| CN112018112B (zh) * | 2019-05-29 | 2025-05-02 | 中芯国际集成电路制造(上海)有限公司 | 半导体单元结构及其形成方法 |
| KR102784791B1 (ko) * | 2019-06-14 | 2025-03-24 | 삼성전자주식회사 | 반도체 소자 |
| US11387229B2 (en) | 2019-06-14 | 2022-07-12 | Samsung Electronics Co., Ltd. | Semiconductor device |
| US11862637B2 (en) * | 2019-06-19 | 2024-01-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tie off device |
| KR102812124B1 (ko) | 2019-07-17 | 2025-05-22 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
| US10868538B1 (en) * | 2019-07-29 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company Ltd. | Logic cell structure and integrated circuit with the logic cell structure |
| US11488947B2 (en) * | 2019-07-29 | 2022-11-01 | Tokyo Electron Limited | Highly regular logic design for efficient 3D integration |
| US10796061B1 (en) | 2019-08-29 | 2020-10-06 | Advanced Micro Devices, Inc. | Standard cell and power grid architectures with EUV lithography |
| KR102866516B1 (ko) | 2019-09-03 | 2025-10-13 | 삼성전자주식회사 | 반도체 장치의 레이아웃 설계 방법 |
| CN110690215A (zh) * | 2019-11-13 | 2020-01-14 | 上海华力微电子有限公司 | 基于FinFET小面积标准单元的版图结构 |
| KR102868418B1 (ko) * | 2019-11-29 | 2025-10-13 | 삼성전자주식회사 | 집적된 표준셀 구조를 포함하는 집적 회로 |
| KR102807821B1 (ko) | 2019-12-17 | 2025-05-14 | 삼성전자주식회사 | 반도체 집적 회로 |
| US11263378B2 (en) * | 2020-01-16 | 2022-03-01 | Taiwan Semiconductor Manufacturing Company Limited | Multi-row standard cell design method in hybrid row height system |
| KR102770405B1 (ko) | 2020-04-17 | 2025-02-18 | 삼성전자주식회사 | 반도체 장치 |
| KR102800879B1 (ko) * | 2020-04-28 | 2025-04-29 | 삼성전자주식회사 | Mosfet 소자 및 그 제조방법 |
| KR102883698B1 (ko) * | 2020-04-29 | 2025-11-11 | 삼성전자주식회사 | 중앙의 파워 레일들을 갖는 스탠다드 셀 및 스탠다드 셀 블록 |
| US11355395B2 (en) * | 2020-05-22 | 2022-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit in hybrid row height structure |
| TWI790619B (zh) * | 2020-05-26 | 2023-01-21 | 台灣積體電路製造股份有限公司 | 積體電路結構 |
| US11424250B2 (en) * | 2020-08-27 | 2022-08-23 | Qualcomm Incorporated | Memory |
| US11817392B2 (en) | 2020-09-28 | 2023-11-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit |
| CN112259535A (zh) * | 2020-09-28 | 2021-01-22 | 牛芯半导体(深圳)有限公司 | 基于Finfet工艺的基本数字逻辑单元、集成电路版图 |
| US11552085B2 (en) | 2020-09-28 | 2023-01-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device including memory cell and fin arrangements |
| KR20220085138A (ko) | 2020-12-15 | 2022-06-22 | 삼성전자주식회사 | 반도체 장치, 반도체 장치의 레이아웃 디자인 방법 및 반도체 장치의 제조 방법 |
| CN114792727A (zh) * | 2021-01-25 | 2022-07-26 | 台湾积体电路制造股份有限公司 | 半导体器件及其使用方法 |
| EP4060738A4 (en) * | 2021-02-05 | 2022-11-30 | Changxin Memory Technologies, Inc. | STANDARD CELL TEMPLATE AND SEMICONDUCTOR STRUCTURE |
| US11955369B2 (en) | 2021-06-08 | 2024-04-09 | International Business Machines Corporation | Recessed local interconnect formed over self-aligned double diffusion break |
| EP4141932A3 (en) * | 2021-08-31 | 2023-05-03 | Invention And Collaboration Laboratory Pte. Ltd. | Standard cell structure |
| US12205897B2 (en) | 2021-09-23 | 2025-01-21 | Advanced Micro Devices, Inc. | Standard cell design architecture for reduced voltage droop utilizing reduced contacted gate poly pitch and dual height cells |
| US20230335644A1 (en) * | 2022-04-14 | 2023-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gates of Hybrid-Fin Devices |
| US12336264B2 (en) * | 2022-06-21 | 2025-06-17 | Nanya Technology Corporation | Semiconductor device having gate electrodes with dopant of different conductive types |
| US20240304521A1 (en) * | 2023-03-08 | 2024-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device having cfet with power grid rails in second metallization layer and method of manufacturing same |
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| US7266787B2 (en) | 2005-02-24 | 2007-09-04 | Icera, Inc. | Method for optimising transistor performance in integrated circuits |
| US20060190893A1 (en) | 2005-02-24 | 2006-08-24 | Icera Inc. | Logic cell layout architecture with shared boundary |
| US8124976B2 (en) * | 2005-12-02 | 2012-02-28 | Nec Corporation | Semiconductor device and method of manufacturing the same |
| US7763534B2 (en) * | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
| US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
| US9563733B2 (en) * | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
| JP4791868B2 (ja) * | 2006-03-28 | 2011-10-12 | 株式会社東芝 | Ｆｉｎ−ＮＡＮＤ型フラッシュメモリ |
| US7838948B2 (en) | 2007-01-30 | 2010-11-23 | Infineon Technologies Ag | Fin interconnects for multigate FET circuit blocks |
| JP4461154B2 (ja) * | 2007-05-15 | 2010-05-12 | 株式会社東芝 | 半導体装置 |
| JP2009016418A (ja) * | 2007-07-02 | 2009-01-22 | Nec Electronics Corp | 半導体装置 |
| US8141016B2 (en) | 2008-08-29 | 2012-03-20 | International Business Machines Corporation | Integrated design for manufacturing for 1×N VLSI design |
| JP2010098081A (ja) * | 2008-09-16 | 2010-04-30 | Hitachi Ltd | 半導体装置 |
| US8258577B2 (en) * | 2009-06-04 | 2012-09-04 | International Business Machines Corporation | CMOS inverter device with fin structures |
| US8258572B2 (en) * | 2009-12-07 | 2012-09-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM structure with FinFETs having multiple fins |
| US8610176B2 (en) * | 2011-01-11 | 2013-12-17 | Qualcomm Incorporated | Standard cell architecture using double poly patterning for multi VT devices |
| US10192859B2 (en) * | 2011-05-11 | 2019-01-29 | Texas Instruments Incorporated | Integrated circuits and processes for protection of standard cell performance from context effects |
| US8595661B2 (en) * | 2011-07-29 | 2013-11-26 | Synopsys, Inc. | N-channel and p-channel finFET cell architecture |
| WO2013106799A1 (en) * | 2012-01-13 | 2013-07-18 | Tela Innovations, Inc. | Circuits with linear finfet structures |
| US9252021B2 (en) * | 2012-02-09 | 2016-02-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for patterning a plurality of features for Fin-like field-effect transistor (FinFET) devices |
| US8723268B2 (en) | 2012-06-13 | 2014-05-13 | Synopsys, Inc. | N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch |
| US8901615B2 (en) | 2012-06-13 | 2014-12-02 | Synopsys, Inc. | N-channel and P-channel end-to-end finfet cell architecture |
| US9123565B2 (en) | 2012-12-31 | 2015-09-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Masks formed based on integrated circuit layout design having standard cell that includes extended active region |
| US8943455B2 (en) | 2013-03-12 | 2015-01-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for layout verification for polysilicon cell edge structures in FinFET standard cells |
| US9158877B2 (en) * | 2013-05-02 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Standard cell metal structure directly over polysilicon structure |
| JP6281571B2 (ja) * | 2013-08-28 | 2018-02-21 | 株式会社ソシオネクスト | 半導体集積回路装置 |
| WO2015033490A1 (ja) * | 2013-09-04 | 2015-03-12 | パナソニック株式会社 | 半導体装置 |
| CN104779207A (zh) * | 2014-01-13 | 2015-07-15 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制造方法 |
| JP2016029690A (ja) * | 2014-07-25 | 2016-03-03 | マイクロン テクノロジー， インク． | 半導体装置及びその製造方法 |
| JP6449082B2 (ja) * | 2014-08-18 | 2019-01-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP6373686B2 (ja) * | 2014-08-22 | 2018-08-15 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US20160111421A1 (en) * | 2014-10-21 | 2016-04-21 | Mark S. Rodder | Multiple cpp for increased source/drain area for fets including in a critical speed path |
| FI20150334A (fi) * | 2015-01-14 | 2016-07-15 | Artto Mikael Aurola | Paranneltu puolijohdekokoonpano |
| US9337099B1 (en) | 2015-01-30 | 2016-05-10 | Globalfoundries Inc. | Special constructs for continuous non-uniform active region FinFET standard cells |
| US10236302B2 (en) | 2016-06-22 | 2019-03-19 | Qualcomm Incorporated | Standard cell architecture for diffusion based on fin count |
-
2017
- 2017-06-21 US US15/629,725 patent/US10236302B2/en active Active
- 2017-06-21 US US15/629,728 patent/US10366196B2/en active Active
- 2017-06-22 WO PCT/US2017/038730 patent/WO2018013315A1/en not_active Ceased
- 2017-06-22 CN CN201780036697.XA patent/CN109314110B/zh active Active
- 2017-06-22 KR KR1020187036970A patent/KR102083190B1/ko active Active
- 2017-06-22 WO PCT/US2017/038716 patent/WO2017223295A1/en not_active Ceased
- 2017-06-22 CA CA3024332A patent/CA3024332C/en active Active
- 2017-06-22 EP EP17739771.8A patent/EP3475984A1/en active Pending
- 2017-06-22 JP JP2018566482A patent/JP6752905B2/ja active Active
- 2017-06-22 CN CN201780035668.1A patent/CN109314109B/zh active Active
- 2017-06-22 SG SG11201810054RA patent/SG11201810054RA/en unknown
- 2017-06-22 EP EP17737414.7A patent/EP3475983A1/en active Pending
- 2017-06-22 KR KR1020187036980A patent/KR102528329B1/ko active Active
- 2017-06-22 JP JP2018563676A patent/JP6972031B2/ja active Active
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