JP2019519114A5 - - Google Patents

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JP2019519114A5
JP2019519114A5 JP2018566482A JP2018566482A JP2019519114A5 JP 2019519114 A5 JP2019519114 A5 JP 2019519114A5 JP 2018566482 A JP2018566482 A JP 2018566482A JP 2018566482 A JP2018566482 A JP 2018566482A JP 2019519114 A5 JP2019519114 A5 JP 2019519114A5
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diffusion region
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ｆｉｎｆｅｔベースの論理セルを有する集積回路を設計する方法であって、
ｙ方向に積み重ねられた２つ以上のｐ拡散領域であって、前記２つ以上のｐ拡散領域の各々がｘ方向の２つ以上のフィンを含み、前記２つ以上のｐ拡散領域の各々がｎ型ウェル内にｐ型ドーピングを有するアイランドを含む、２つ以上のｐ拡散領域、または
前記ｙ方向に積み重ねられた２つ以上のｎ拡散領域であって、前記２つ以上のｎ拡散領域の各々が前記ｘ方向の２つ以上のフィンを含み、前記２つ以上のｎ拡散領域の各々がｐ型ウェル内にｎ型ドーピングを有するアイランドを含む、２つ以上のｎ拡散領域
のうちの少なくとも１つを有する少なくとも第１の論理セルを形成するステップを含む、方法。 A method for designing an integrated circuit having finfet-based logic cells, comprising:
two or more p diffusion regions stacked in the y direction, each of the two or more p diffusion regions including two or more fins in the x direction, and each of the two or more p diffusion regions two or more p-diffusion regions comprising islands with p-type doping in the n-type well, or
And two or more n diffusion region stacked prior Symbol y direction, each of the two or more n diffusion region comprises two or more fins of the x-direction, the two or more n diffusion region Forming at least a first logic cell having at least one of two or more n diffusion regions, each including an island having n-type doping in a p-type well. 異なるフィンカウントを有する第１のｐ拡散領域および第２のｐ拡散領域、または
異なるフィンカウントを有する第１のｎ拡散領域および第２のｎ拡散領域
のうちの少なくとも１つを有する前記第１の論理セルを形成するステップをさらに含む、請求項１に記載の方法。 The first p diffusion region and a second p diffusion region having a different fin count or,
Further comprising the step of forming said first logic cell having at least one of the first n diffusion region and the second n diffusion regions having different fin count, The method of claim 1. 前記２つ以上のｐ拡散領域のうちの少なくとも１つに関連する少なくとも第１のローカル電力レール、または
前記２つ以上のｎ拡散領域のうちの少なくとも１つに関連する少なくとも第２のローカル電力レール
のうちの少なくとも１つを有する分散された電力レールネットワークを形成するステップをさらに含む、請求項１に記載の方法。 At least a first local power rail associated with at least one of the two or more p diffusion regions, or at least a second local power rail associated with at least one of the two or more n diffusion regions. The method of claim 1, further comprising forming a distributed power rail network having at least one of: 前記第１のローカル電力レールが、前記２つ以上のｐ拡散領域のうちの少なくとも１つに専用され、かつ／または
前記第２のローカル電力レールが、前記２つ以上のｎ拡散領域のうちの少なくとも１つに専用される、請求項３に記載の方法。 The first local power rail is dedicated to at least one of the two or more p diffusion regions and / or the second local power rail is of the two or more n diffusion regions. The method of claim 3 dedicated to at least one. 異なるレベルのｐ型インプラントによって形成された第１のｐ拡散領域および第２のｐ拡散領域、またはA first p diffusion region and a second p diffusion region formed by p-type implants at different levels, or
異なるレベルのｎ型インプラントによって形成された第１のｎ拡散領域および第２のｎ拡散領域First n-diffusion region and second n-diffusion region formed by different levels of n-type implants
のうちの少なくとも１つを有する前記第１の論理セルを形成するステップをさらに含む、請求項１に記載の方法。The method of claim 1, further comprising forming the first logic cell having at least one of: 第１のｐ拡散領域内に形成された第１のｐｆｅｔおよび第２のｐ拡散領域内に形成された第２のｐｆｅｔであって、前記第１のｐｆｅｔおよび前記第２のｐｆｅｔが、異なるしきい電圧もしくはチャネル長を有する、第１のｐ拡散領域内に形成された第１のｐｆｅｔおよび第２のｐ拡散領域内に形成された第２のｐｆｅｔ、あるいはA first pfet formed in the first p diffusion region and a second pfet formed in the second p diffusion region, wherein the first pfet and the second pfet are different from each other; A first pfet formed in the first p-diffusion region and a second pfet formed in the second p-diffusion region having a threshold voltage or channel length, or
第１のｎ拡散領域内に形成された第１のｎｆｅｔおよび第２のｎ拡散領域内に形成された第２のｎｆｅｔであって、前記第１のｎｆｅｔおよび前記第２のｎｆｅｔが、異なるしきい電圧もしくはチャネル長を有する、第１のｎ拡散領域内に形成された第１のｎｆｅｔおよび第２のｎ拡散領域内に形成された第２のｎｆｅｔA first nfet formed in the first n diffusion region and a second nfet formed in the second n diffusion region, wherein the first nfet and the second nfet are different; A first nfet formed in the first n diffusion region and a second nfet formed in the second n diffusion region having a threshold voltage or channel length
のうちの少なくとも１つを有する前記第１の論理セルを形成するステップをさらに含む、請求項１に記載の方法。The method of claim 1, further comprising forming the first logic cell having at least one of: 比率論理を有する２入力ＮＡＮＤゲートとして前記第１の論理セルを形成するステップを含み、第１のフィンカウントが第２のフィンカウントと異なる、請求項１に記載の方法。   The method of claim 1, comprising forming the first logic cell as a two-input NAND gate having a ratio logic, wherein the first fin count is different from the second fin count. 前記第１のｐ拡散領域内に２フィンに等しい前記第１のフィンカウントを有する２つのｐｆｅｔを形成するステップ、および接続された前記２つのｐｆｅｔを並列に接続するステップと、
２つのｎｆｅｔを形成するステップであって、前記２つのｎｆｅｔの各々が４フィンに等しい前記第２のフィンカウントを有し、前記４フィンのうちの２つが前記第１のｎ拡散領域内にあり、前記４フィンのうちの２つが別のｎ拡散領域内にある、ステップ、および前記２つのｎｆｅｔを直列に接続するステップとをさらに含む、請求項７に記載の方法。 Forming two pfets having the first fin count equal to 2 fins in the first p diffusion region, and connecting the two connected pfets in parallel;
Forming two nfets, each of the two nfets having the second fin count equal to four fins, two of the four fins being in the first n diffusion region The method of claim 7 , further comprising: two of the four fins are in another n diffusion region, and connecting the two nfets in series. 前記２つのｐｆｅｔと前記２つのｎｆｅｔとの間で共有される、少なくとも１つのポリ線を形成するステップをさらに含む、請求項８に記載の方法。 The method of claim 8 , further comprising forming at least one polyline shared between the two pfets and the two nfets. 前記第１の論理セルの前記第１のｐ拡散領域と別のｐ拡散との間の前記少なくとも１つのポリ線上にポリカットを配置するステップをさらに含む、請求項９に記載の方法。 Further comprising the step of placing a Polycut on at least one poly line between said first p diffusion region and another p diffusion of the first logic cell, The method of claim 9. 前記２つのｐｆｅｔと前記２つのｎｆｅｔとの間の前記少なくとも１つのポリ線上に少なくとも１つのゲートビアを形成するステップ、および金属−拡散（ＭＤ）層を前記少なくとも１つのゲートビアに接続するステップをさらに含む、請求項９に記載の方法。 Further comprising the step of connecting the diffusion (MD) layer to the at least one Getobia - the step of forming at least one Getobia on at least one poly lines, and the metal between the two pfet the two nfet The method according to claim 9 . ｆｉｎｆｅｔベースの論理セルを有する集積回路を設計する方法であって、A method for designing an integrated circuit having finfet-based logic cells, comprising:
第１の論理セル境界を有する第１の論理セルを第２の論理セル境界を有する第２の論理セルに隣接して配置するステップであって、前記第１の論理セル境界および前記第２の論理セル境界が共通縁部を有し、Disposing a first logic cell having a first logic cell boundary adjacent to a second logic cell having a second logic cell boundary, wherein the first logic cell boundary and the second logic cell boundary; Logic cell boundaries have a common edge,
前記第１の論理セルが、第１のフィンカウントを有する第１のｐ拡散領域上に形成された少なくとも１つのｐｆｅｔおよび第２のフィンカウントを有する第１のｎ拡散領域上に形成された少なくとも１つのｎｆｅｔを含み、The first logic cell is formed on at least one pfet formed on a first p diffusion region having a first fin count and on a first n diffusion region having a second fin count. Contains one nfet,
前記第２の論理セルが、前記第１のフィンカウントを有する第２のｐ拡散領域上に形成された少なくとも１つのｐｆｅｔおよび前記第２のフィンカウントを有する第２のｎ拡散領域上に形成された少なくとも１つのｎｆｅｔを含む、The second logic cell is formed on at least one pfet formed on a second p diffusion region having the first fin count and on a second n diffusion region having the second fin count. Including at least one nfet,
配置するステップと、Placing step;
前記共通縁部を横断し、前記第１の論理セルの前記第１のｐ拡散領域および前記第２の論理セルの前記第２のｐ拡散領域を接合する第１のｐ拡散フィル、またはA first p diffusion fill that crosses the common edge and joins the first p diffusion region of the first logic cell and the second p diffusion region of the second logic cell; or
前記共通縁部を横断し、前記第１の論理セルの前記第１のｎ拡散領域および前記第２の論理セルの前記第２のｎ拡散領域を接合する第１のｎ拡散フィルA first n diffusion fill that crosses the common edge and joins the first n diffusion region of the first logic cell and the second n diffusion region of the second logic cell.
のうちの少なくとも１つを形成するステップとを含む、方法。Forming at least one of the methods. 前記第１のｐ拡散フィルを有する、前記第１の論理セルの前記第１のｐ拡散領域および前記第２の論理セルの前記第２のｐ拡散領域、またはThe first p diffusion region of the first logic cell and the second p diffusion region of the second logic cell having the first p diffusion fill, or
前記第１のｎ拡散フィルを有する、前記第１の論理セルの前記第１のｎ拡散領域および前記第２の論理セルの前記第２のｎ拡散領域The first n diffusion region of the first logic cell and the second n diffusion region of the second logic cell having the first n diffusion fill.
のうちの少なくとも１つの拡散の長さ（ＬＯＤ）を延ばすステップを含む、請求項１２に記載の方法。The method of claim 12, comprising extending a length of diffusion (LOD) of at least one of the two. 前記第１の論理セルの前記第１のｐ拡散領域および前記第２の論理セルの前記第２のｐ拡散領域が、共通の第１の電位にあり、かつ／またはThe first p diffusion region of the first logic cell and the second p diffusion region of the second logic cell are at a common first potential and / or
前記第１の論理セルの前記第１のｎ拡散領域および前記第２の論理セルの前記第２のｎ拡散領域が、共通の第２の電位にある、請求項１２に記載の方法。13. The method of claim 12, wherein the first n diffusion region of the first logic cell and the second n diffusion region of the second logic cell are at a common second potential. 前記共通の第１の電位における前記第１のｐ拡散フィルと第１の金属層との間の接続、またはA connection between the first p-diffusion fill and the first metal layer at the common first potential, or
前記共通の第２の電位における前記第１のｎ拡散フィルと第２の金属層との間の接続Connection between the first n diffusion fill and the second metal layer at the common second potential
のうちの少なくとも１つを形成するステップをさらに含む、請求項１４に記載の方法。15. The method of claim 14, further comprising forming at least one of: 前記共通の第１の電位が電力レールの電位に相当し、前記共通の第２の電位が接地レールまたはローカル相互接続の電位に相当する、請求項１５に記載の方法。The method of claim 15, wherein the common first potential corresponds to a power rail potential and the common second potential corresponds to a ground rail or local interconnect potential. 前記電力レールまたは前記接地レールのうちの少なくとも１つが、前記第１の論理セルの前記拡散領域と前記第２の論理セルの前記拡散領域との間の空間内に分散される、請求項１６に記載の方法。17. At least one of the power rail or the ground rail is distributed in a space between the diffusion region of the first logic cell and the diffusion region of the second logic cell. The method described. 前記第１の論理セルまたは前記第２の論理セルの少なくとも１つのポリ線をフローティングさせるステップをさらに含み、前記少なくとも１つのポリ線が前記共通縁部に隣接し、前記第１のｐ拡散領域、前記第２のｐ拡散領域、前記第１のｎ拡散領域、または前記第２のｎ拡散領域のうちの少なくとも１つと交差する、請求項１２に記載の方法。Floating at least one polyline of the first logic cell or the second logic cell, wherein the at least one polyline is adjacent to the common edge, and the first p diffusion region; The method of claim 12, wherein the method intersects at least one of the second p diffusion region, the first n diffusion region, or the second n diffusion region. 前記第１のフィンカウントが、前記第２のフィンカウントとは異なる、請求項１２に記載の方法。The method of claim 12, wherein the first fin count is different from the second fin count. 前記第１の論理セルが、前記第１のフィンカウントと前記第２のフィンカウントとの間の比率論理を有する２入力ＮＡＮＤゲートである、請求項１９に記載の方法。The method of claim 19, wherein the first logic cell is a two-input NAND gate having a ratio logic between the first fin count and the second fin count. 前記２入力ＮＡＮＤゲートを形成するステップが、Forming the two-input NAND gate comprises:
２つのｐｆｅｔを並列に接続するステップであって、前記２つのｐｆｅｔの各々が、前記第１のｐ拡散領域上に形成された２フィンに等しい前記第１のフィンカウントを有する、ステップと、Connecting two pfets in parallel, each of the two pfets having the first fin count equal to two fins formed on the first p diffusion region;
２つのｎｆｅｔを直列に接続するステップであって、前記２つのｎｆｅｔの各々が４フィンに等しい前記第２のフィンカウントを有し、前記第１の論理セルの前記第１のｎ拡散領域上に形成された前記４フィンのうちの２つと別のｎ拡散領域上に形成された前記４フィンのうちの２つとが、前記第１のｎ拡散領域と直列に接続される、ステップとを含む、請求項２０に記載の方法。Connecting two nfets in series, each of the two nfets having the second fin count equal to four fins, on the first n diffusion region of the first logic cell Two of the four fins formed and two of the four fins formed on another n diffusion region are connected in series with the first n diffusion region. The method of claim 20. 前記２つのｐｆｅｔと前記２つのｎｆｅｔとの間で少なくとも１つのポリ線を共有するステップを含む、請求項２１に記載の方法。24. The method of claim 21, comprising sharing at least one polyline between the two pfets and the two nfets. 前記２つのｐｆｅｔと前記２つのｎｆｅｔとの間の少なくとも１つのポリ線上に少なくとも１つのゲートビアを形成するステップを含む、請求項２１に記載の方法。23. The method of claim 21, comprising forming at least one gate via on at least one poly line between the two pfets and the two nfets. 前記少なくとも１つのゲートビアを金属−拡散（ＭＤ）層に接続するステップを含む、請求項２３に記載の方法。24. The method of claim 23, comprising connecting the at least one gate via to a metal-diffusion (MD) layer. 前記第２の論理セルが、各ｐｆｅｔが２フィンに等しい前記第１のフィンカウントを有し、少なくとも前記第２のｐ拡散領域を含む２つのｐ拡散領域内に形成される２つのｐｆｅｔと、各ｎｆｅｔが２フィンに等しい前記第２のフィンカウントを有し、少なくとも前記第２のｎ拡散領域を含む２つのｎ拡散領域内に形成される２つのｎｆｅｔとを含むインバータである、請求項２４に記載の方法。The second logic cell has two first pfets formed in two p diffusion regions, each pfet having the first fin count equal to two fins, and including at least the second p diffusion region; 25. An inverter comprising: each nfet having the second fin count equal to 2 fins and including two nfets formed in two n diffusion regions including at least the second n diffusion region. The method described in 1. 前記第１の論理セルの前記第１のｐ拡散領域と別のｐ拡散領域との間の少なくとも１つのポリ線上にポリカットを配置するステップを含む、請求項２０に記載の方法。21. The method of claim 20, comprising placing a polycut on at least one polyline between the first p diffusion region and another p diffusion region of the first logic cell. 前記第１もしくは第２のｎ拡散領域または第１もしくは第２のｐ拡散領域のうちの少なくとも１つのインプラントもしくはしきい電圧を調整するステップをさらに含む、請求項１２に記載の方法。13. The method of claim 12, further comprising adjusting an implant or threshold voltage of at least one of the first or second n diffusion region or the first or second p diffusion region. 前記第１もしくは第２のｎ拡散領域または第１もしくは第２のｐ拡散領域のうちの少なくとも１つの中に形成されたゲートのチャネル長を調整するステップをさらに含む、請求項１２に記載の方法。13. The method of claim 12, further comprising adjusting a channel length of a gate formed in at least one of the first or second n diffusion region or the first or second p diffusion region. . ｆｉｎｆｅｔベースの論理セルを有する集積回路を設計する方法であって、A method for designing an integrated circuit having finfet-based logic cells, comprising:
２つ以上のｐ拡散領域または２つ以上のｎ拡散領域のうちの少なくとも１つを含む、少なくとも第１の全行高さ論理セルを含む第１の全行を形成するステップと、Forming a first full row including at least a first full row height logic cell including at least one of two or more p diffusion regions or two or more n diffusion regions;
２つ以上のｐ拡散領域または２つ以上のｎ拡散領域のうちの少なくとも１つを含む、少なくとも第２の全行高さ論理セルを含む第２の全行を前記第１の全行に隣接して形成するステップであって、A second full row including at least a second full row height logic cell including at least one of two or more p diffusion regions or two or more n diffusion regions adjacent to the first full row The step of forming
前記第１の全行および前記第２の全行の２つ以上のｐ拡散領域はｙ方向に積み重ねられ、前記２つ以上のｐ拡散領域の各々がｘ方向の２つ以上のフィンを含み、前記２つ以上のｐ拡散領域の各々がｎ型ウェル内にｐ型ドーピングを有するアイランドを含む、またはTwo or more p diffusion regions of the first full row and the second full row are stacked in the y direction, each of the two or more p diffusion regions including two or more fins in the x direction; Each of the two or more p-diffusion regions includes an island having p-type doping in the n-type well, or
前記第１の全行および前記第２の全行の２つ以上のｎ拡散領域はｙ方向に積み重ねられ、前記２つ以上のｎ拡散領域の各々が前記ｘ方向の２つ以上のフィンを含み、前記２つ以上のｎ拡散領域の各々がｐ型ウェル内にｎ型ドーピングを有するアイランドを含む、ステップと、Two or more n diffusion regions of the first full row and the second full row are stacked in the y direction, and each of the two or more n diffusion regions includes two or more fins in the x direction. Each of the two or more n diffusion regions includes an island having n-type doping in a p-type well;
前記第１の全行と前記第２の全行との間に１つまたは複数の副行を散在させるステップであって、前記１つまたは複数の副行のうちの少なくとも第１の副行が、少なくとも１つのｐ拡散領域および少なくとも１つのｎ拡散領域を含む第１の半行高さ論理セルを含み、Interspersing one or more sub-rows between the first full row and the second full row, wherein at least a first sub-row of the one or more sub-rows is A first half-height logic cell comprising at least one p-diffusion region and at least one n-diffusion region;
前記第１の半行高さ論理セルの前記少なくとも１つのｐ拡散領域が、前記第１の全行高さ論理セルもしくは前記第２の全行高さ論理セルの前記２つ以上のｐ拡散領域のうちの１つに隣接し、かつ／またはThe at least one p diffusion region of the first half row height logic cell is the two or more p diffusion regions of the first full row height logic cell or the second full row height logic cell. Adjacent to one of and / or
前記第１の半行高さ論理セルの前記少なくとも１つのｎ拡散領域が、前記第１の全行高さ論理セルもしくは前記第２の全行高さ論理セルの前記２つ以上のｎ拡散領域のうちの１つに隣接する、ステップとを含む方法。The at least one n diffusion region of the first half row height logic cell is the two or more n diffusion regions of the first full row height logic cell or the second full row height logic cell. Adjacent to one of the steps. 前記第１の全行高さ論理セルに対して前記第２の全行高さ論理セルを垂直方向にミラー反転することなく、前記第２の全行高さ論理セルを形成するステップを含む、請求項２９に記載の方法。Forming the second full row height logic cell without mirror inverting the second full row height logic cell with respect to the first full row height logic cell; 30. The method of claim 29. 前記１つまたは複数の副行のうちの２つの隣接する副行の隣接する半行高さセルを、互いに対して垂直方向にミラー反転することによって、前記１つまたは複数の副行のうちの前記２つの隣接する副行の隣接する半行高さセルを形成するステップを含む、請求項２９に記載の方法。Of the one or more subrows by mirror-inverting adjacent half row height cells of two adjacent subrows of the one or more subrows in a direction perpendicular to each other; 30. The method of claim 29, comprising forming adjacent half row height cells of the two adjacent subrows. 前記第１の半行高さ論理セルの前記少なくとも１つのｐ拡散領域、および前記第１の全行高さ論理セルまたは前記第２の全行高さ論理セルの前記２つ以上のｐ拡散領域のうちの１つの拡散の長さを、少なくとも１つのｐ拡散フィルを用いて延ばすステップをさらに含む、請求項２９に記載の方法。The at least one p diffusion region of the first half-row logic cell and the two or more p diffusion regions of the first full row logic cell or the second full row logic cell. 30. The method of claim 29, further comprising extending the length of one of the diffusions using at least one p-diffusion fill. 前記第１の半行高さ論理セルの前記少なくとも１つのｎ拡散領域、および前記第１の全行高さ論理セルまたは前記第２の全行高さ論理セルの前記２つ以上のｎ拡散領域のうちの１つの拡散の長さを、少なくとも１つのｎ拡散フィルを用いて延ばすステップをさらに含む、請求項２９に記載の方法。The at least one n diffusion region of the first half row height logic cell and the two or more n diffusion regions of the first full row height logic cell or the second full row height logic cell; 30. The method of claim 29, further comprising extending the length of one of the diffusions using at least one n diffusion fill. プロセッサによって実行されると、ｆｉｎｆｅｔベースの論理セルを有する集積回路を設計するための動作を前記プロセッサに実行させるコードを含む非一時的コンピュータ可読記憶媒体であって、前記非一時的コンピュータ可読記憶媒体が、A non-transitory computer-readable storage medium comprising code that, when executed by a processor, causes the processor to perform an operation to design an integrated circuit having finfet-based logic cells But,
２つ以上のｐ拡散領域であって、ｙ方向に積み重ねられ、前記２つ以上のｐ拡散領域の各々がｘ方向の２つ以上のフィンを含み、前記２つ以上のｐ拡散領域の各々がｎ型ウェル内にｐ型ドーピングを有するアイランドを含む、２つ以上のｐ拡散領域、またはTwo or more p diffusion regions, stacked in the y direction, each of the two or more p diffusion regions including two or more fins in the x direction, each of the two or more p diffusion regions being two or more p-diffusion regions comprising islands with p-type doping in the n-type well, or
２つ以上のｎ拡散領域であって、前記ｙ方向に積み重ねられ、前記２つ以上のｎ拡散領域の各々が前記ｘ方向の２つ以上のフィンを含み、前記２つ以上のｎ拡散領域の各々がｐ型ウェル内にｎ型ドーピングを有するアイランドを含む、２つ以上のｎ拡散領域Two or more n diffusion regions, stacked in the y direction, each of the two or more n diffusion regions including two or more fins in the x direction, Two or more n diffusion regions each including an island with n-type doping in a p-type well
のうちの少なくとも１つを有する少なくとも第１の論理セルを形成するためのコードを含む、非一時的コンピュータ可読記憶媒体。A non-transitory computer readable storage medium comprising code for forming at least a first logic cell having at least one of the following. プロセッサによって実行されると、ｆｉｎｆｅｔベースの論理セルを有する集積回路を設計するための動作を前記プロセッサに実行させるコードを含む非一時的コンピュータ可読記憶媒体であって、前記非一時的コンピュータ可読記憶媒体が、A non-transitory computer-readable storage medium comprising code that, when executed by a processor, causes the processor to perform an operation to design an integrated circuit having finfet-based logic cells But,
第１の論理セル境界を有する第１の論理セルを第２の論理セル境界を有する第２の論理セルに隣接して配置するためのコードであって、前記第１の論理セル境界および前記第２の論理セル境界が共通縁部を有し、A code for placing a first logic cell having a first logic cell boundary adjacent to a second logic cell having a second logic cell boundary, wherein the first logic cell boundary and the first logic cell boundary Two logic cell boundaries have a common edge;
前記第１の論理セルが、第１のフィンカウントを有する第１のｐ拡散領域上に形成された少なくとも１つのｐｆｅｔおよび第２のフィンカウントを有する第１のｎ拡散領域上に形成された少なくとも１つのｎｆｅｔを含み、The first logic cell is formed on at least one pfet formed on a first p diffusion region having a first fin count and on a first n diffusion region having a second fin count. Contains one nfet,
前記第２の論理セルが、前記第１のフィンカウントを有する第２のｐ拡散領域上に形成された少なくとも１つのｐｆｅｔおよび前記第２のフィンカウントを有する第２のｎ拡散領域上に形成された少なくとも１つのｎｆｅｔを含む、The second logic cell is formed on at least one pfet formed on a second p diffusion region having the first fin count and on a second n diffusion region having the second fin count. Including at least one nfet,
コードと、Code,
前記共通縁部を横断し、前記第１の論理セルの前記第１のｐ拡散領域および前記第２の論理セルの前記第２のｐ拡散領域を接合する第１のｐ拡散フィル、またはA first p diffusion fill that crosses the common edge and joins the first p diffusion region of the first logic cell and the second p diffusion region of the second logic cell; or
前記共通縁部を横断し、前記第１の論理セルの前記第１のｎ拡散領域および前記第２の論理セルの前記第２のｎ拡散領域を接合する第１のｎ拡散フィルA first n diffusion fill that crosses the common edge and joins the first n diffusion region of the first logic cell and the second n diffusion region of the second logic cell.
のうちの少なくとも１つを形成するためのコードとを含む、非一時的コンピュータ可読記憶媒体。And a code for forming at least one of the non-transitory computer readable storage medium. プロセッサによって実行されると、ｆｉｎｆｅｔベースの論理セルを有する集積回路を設計するための動作を前記プロセッサに実行させるコードを含む非一時的コンピュータ可読記憶媒体であって、前記非一時的コンピュータ可読記憶媒体が、A non-transitory computer-readable storage medium comprising code that, when executed by a processor, causes the processor to perform an operation to design an integrated circuit having finfet-based logic cells But,
２つ以上のｐ拡散領域または２つ以上のｎ拡散領域のうちの少なくとも１つを含む、少なくとも第１の全行高さ論理セルを含む第１の全行を形成するためのコードと、Code for forming a first full row including at least a first full row height logic cell including at least one of two or more p diffusion regions or two or more n diffusion regions;
２つ以上のｐ拡散領域または２つ以上のｎ拡散領域のうちの少なくとも１つを含む、少なくとも第２の全行高さ論理セルを含む第２の全行を前記第１の全行に隣接して形成するためのコードであって、A second full row including at least a second full row height logic cell including at least one of two or more p diffusion regions or two or more n diffusion regions adjacent to the first full row A cord for forming
前記第１の全行および前記第２の全行の２つ以上のｐ拡散領域はｙ方向に積み重ねられ、前記２つ以上のｐ拡散領域の各々がｘ方向の２つ以上のフィンを含み、前記２つ以上のｐ拡散領域の各々がｎ型ウェル内にｐ型ドーピングを有するアイランドを含む、またはTwo or more p diffusion regions of the first full row and the second full row are stacked in the y direction, each of the two or more p diffusion regions including two or more fins in the x direction; Each of the two or more p-diffusion regions includes an island having p-type doping in the n-type well, or
前記第１の全行および前記第２の全行の２つ以上のｎ拡散領域は前記ｙ方向に積み重ねられ、前記２つ以上のｎ拡散領域の各々が前記ｘ方向の２つ以上のフィンを含み、前記２つ以上のｎ拡散領域の各々がｐ型ウェル内にｎ型ドーピングを有するアイランドを含む、コードと、Two or more n diffusion regions of the first full row and the second full row are stacked in the y direction, and each of the two or more n diffusion regions has two or more fins in the x direction. A cord, wherein each of the two or more n diffusion regions includes an island having n-type doping in a p-type well;
前記第１の全行と前記第２の全行との間に１つまたは複数の副行を散在させるためのコードであって、前記１つまたは複数の副行のうちの少なくとも第１の副行が、少なくとも１つのｐ拡散領域および少なくとも１つのｎ拡散領域を含む第１の半行高さ論理セルを含み、Code for interspersing one or more sub-rows between the first full row and the second full row, wherein at least a first sub-row of the one or more sub-rows A row includes a first half row height logic cell including at least one p diffusion region and at least one n diffusion region;
前記第１の半行高さ論理セルの前記少なくとも１つのｐ拡散領域が、前記第１の全行高さ論理セルもしくは前記第２の全行高さ論理セルの前記２つ以上のｐ拡散領域のうちの１つに隣接し、かつ／またはThe at least one p diffusion region of the first half row height logic cell is the two or more p diffusion regions of the first full row height logic cell or the second full row height logic cell. Adjacent to one of and / or
前記第１の半行高さ論理セルの前記少なくとも１つのｎ拡散領域が、前記第１の全行高さ論理セルもしくは前記第２の全行高さ論理セルの前記２つ以上のｎ拡散領域のうちの１つに隣接する、コードとを含む、非一時的コンピュータ可読記憶媒体。The at least one n diffusion region of the first half row height logic cell is the two or more n diffusion regions of the first full row height logic cell or the second full row height logic cell. A non-transitory computer readable storage medium comprising code adjacent to one of the two.
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