CN110690215A - Layout structure based on FinFET small-area standard unit - Google Patents

Layout structure based on FinFET small-area standard unit Download PDF

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Publication number
CN110690215A
CN110690215A CN201911106462.0A CN201911106462A CN110690215A CN 110690215 A CN110690215 A CN 110690215A CN 201911106462 A CN201911106462 A CN 201911106462A CN 110690215 A CN110690215 A CN 110690215A
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polysilicon
fin
layer
standard cell
layout
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虞蓓蕾
高唯欢
胡晓明
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention discloses a layout structure based on a FinFET small-area standard cell, wherein an intermediate polysilicon truncation layer is also formed between a first polysilicon truncation layer of which the central line forms the upper edge of the standard cell and a second polysilicon truncation layer of which the central line forms the lower edge of the standard cell, the intermediate polysilicon truncation layer divides polysilicon on the same track into two parts of polysilicon, and two polysilicon connection layers with different graphic specifications respectively introduce different input signals through the two parts of polysilicon. The invention adds two polysilicon interception layers, adopts the combination of two polysilicon connection layers with different graphic specifications and the added polysilicon interception layers, realizes that two different input signals can be simultaneously introduced into the same polysilicon track under the condition that the height of the polysilicon interception layer is the same as that of the traditional standard cell layout and the polysilicon interception layer conforms to the design rule, has more compact active area layout (4 independent AA areas), can be realized by using four polysilicon tracks, and reduces the layout area of the standard cell.

Description

Layout structure based on FinFET small-area standard unit
Technical Field
The invention belongs to the field of microelectronic and semiconductor integrated circuit design, relates to a standard cell library, and particularly belongs to a layout structure based on FinFET small-area standard cells.
Background
The Standard Cell library is the basis of the automatic design of a Very Large Scale Integration (VLSI), the layouts of various Standard Cell circuits are designed by adopting a full-customization method, and then the layout structures of the Standard cells (STD cells) which are subjected to optimized design and pass verification are stored in a database. During design, the required standard cells are called out from the cell library and are arranged into a plurality of rows, and wiring channels are reserved among the rows. And then connecting the standard units by using a connecting wire according to the circuit requirements, and simultaneously connecting the corresponding input/output unit and the bonding block to obtain the required chip layout. In the standard cell library, the height of each standard cell is equal, the width is not limited, and the positions of a power supply, a ground wire and an input/output port in each standard cell are specially specified, so that the standard cells can be simply and orderly connected, the layout is regular, great convenience is brought to the subsequent high-level system design, and the system design which is originally complex and has large workload is relatively simple and easy and has strong regularity. The optimized standard unit can be used for automatically carrying out logic synthesis and layout wiring, and the design efficiency is improved.
For clock signal input structures like in D flip-flops, the circuit shown in block area in fig. 1, where P1, P2 are PMOS transistors and N1, N2 are NMOS transistors. The input signals of the gate of the first PMOS transistor (P1) and the gate of the second NMOS transistor (N2) are both CK1 signals, and the input signals of the gate of the second PMOS transistor (P2) and the gate of the first NMOS transistor (N1) are both CKb signals.
A Fin-Field-Effect Transistor (FinFET) is a new type of cmos Transistor that can improve circuit control and reduce leakage current, shortening the gate length of the Transistor. On a 14nm FinFET process platform, the connection of clock signals of a similar D trigger shown in FIG. 1 is realized by using a traditional layout mode, as shown in FIG. 2, due to the design rule requirement and the design characteristics of a standard unit, the layout needs to be divided into six independent Active Areas (AA), and at least six polysilicon tracks are needed for realization.
Specifically, for the clock signal connection structure, the layout structure based on the FinFET standard cell includes a first layout region, a second layout region, a third layout region, a fourth layout region, a fifth layout region, and a sixth layout region, as shown in fig. 3. The first layout area is located in the upper left part of the whole layout and comprises a first PMOS transistor; the second layout region is positioned in the middle upper part of the whole layout and comprises a second PMOS transistor; the third layout area is positioned at the upper right part of the whole layout and comprises a third PMOS transistor and a fourth PMOS transistor; the fourth layout area is positioned at the lower left part of the whole layout and comprises a first NMOS transistor and a second NMOS transistor; the fifth layout area is positioned at the middle lower part of the whole layout and comprises a third NMOS transistor; the sixth layout area is located in the lower right portion of the entire layout and includes a fourth NMOS transistor.
As shown in fig. 3, the layout structure includes an N Well (NW), a boron implantation region (SDP), a phosphorous implantation region (SDN), first to fourth fins (Fin 1-Fin 4), first to sixth active regions (AA 1-AA 6), first to fourteenth Fin connection layers (M01_ 1-M01 _14), first to tenth polysilicon (PO 1-PO 10), first to fifth polysilicon connection layers (M02_ 1-M02 _5), and first to second polysilicon truncation layers (POC 1-POC 2).
The first PMOS transistor in the first layout area is composed of a first active area AA1, a second polysilicon PO2, a first Fin1, a second Fin2, a first Fin connection layer M01_1 and a second Fin connection layer M01_2, and the gate of the first PMOS transistor is connected to a signal a and is introduced from the first polysilicon connection layer M02_1 through the second polysilicon PO 2.
The second PMOS transistor in the second layout area is composed of the second active area AA2, the fifth polysilicon PO5, the first Fin1, the second Fin2, the third Fin connection layer M01_3 and the fourth Fin connection layer M01_4, and the gate of the second PMOS transistor is connected to the signal B and introduced from the third polysilicon connection layer M02_3 through the fifth polysilicon PO 5.
The third PMOS transistor in the third layout area is composed of the third active area AA3, the eighth polysilicon PO8, the first Fin1, the second Fin2, the fifth Fin connection layer M01_5 and the sixth Fin connection layer M01_6, and the gate of the third PMOS transistor is connected to the signal C and is introduced from the fourth polysilicon connection layer M02_4 through the eighth polysilicon PO 8.
The fourth PMOS transistor in the third layout area is composed of the third active area AA3, the ninth polysilicon PO9, the first Fin1, the second Fin2, the sixth Fin connection layer M01_6 and the seventh Fin connection layer M01_7, and the gate of the fourth PMOS transistor is connected to the signal D and introduced from the fifth polysilicon connection layer M02_5 through the ninth polysilicon PO 9.
The first NMOS transistor in the fourth layout area is composed of a fourth active region AA4, a second polysilicon PO2, a third Fin3, a fourth Fin4, an eighth Fin connection layer M01_8, and a ninth Fin connection layer M01_9, and a gate of the first NMOS transistor is connected to a gate of the first PMOS transistor.
The second NMOS transistor in the fourth layout area is composed of a fourth active area AA4, a third polysilicon PO3, a third Fin3, a fourth Fin4, a ninth Fin connection layer M01_9, and a tenth Fin connection layer M01_10, and the gate of the second NMOS transistor is connected to a signal C, which is introduced from the second polysilicon connection layer M02_2 through the third polysilicon PO 3.
The third NMOS transistor in the fifth layout area is composed of a fifth active region AA5, a sixth polysilicon PO6, a third Fin3, a fourth Fin4, an eleventh Fin connection layer M01_11, and a twelfth Fin connection layer M01_12, and the gate of the third NMOS transistor is connected to the gate of the second PMOS transistor through the third polysilicon connection layer M02_ 3.
The fourth NMOS transistor in the sixth layout area is composed of a sixth active area AA6, a ninth polysilicon PO9, a third Fin3, a fourth Fin4, a thirteenth Fin connection layer M01_13, and a fourteenth Fin connection layer M01_14, and a gate of the fourth NMOS transistor is connected to a gate of the fourth PMOS transistor.
In the layout structure, six independent active area AA areas are formed, ten polysilicon tracks are used, wherein CKb signals are input to the third polysilicon PO3 and the eighth polysilicon PO8, and CK1 signals are input to the fifth polysilicon PO5 and the sixth polysilicon PO6, and the standard cells use more polysilicon tracks, the layout of the active area is not compact, and the cell area is larger.
Disclosure of Invention
The invention aims to solve the technical problem of providing a layout structure based on a FinFET small-area standard unit, and can solve the problems of incompact layout and large area of an active region of the traditional layout structure.
In order to solve the technical problem, in the layout structure based on the FinFET small-area standard cell, an intermediate polysilicon truncation layer is further formed between a first polysilicon truncation layer of which the central line forms the upper edge of the standard cell and a second polysilicon truncation layer of which the central line forms the lower edge of the standard cell, the intermediate polysilicon truncation layer divides polysilicon on the same track into two parts of polysilicon, and two polysilicon connection layers with different graphic specifications respectively introduce different input signals through the two parts of polysilicon.
The layout structure of the standard unit is divided into a first layout area, a second layout area, a third layout area and a fourth layout area.
The layout structure of the standard unit comprises an upper edge layout structure, a lower edge layout structure, a Fin transistor layout structure, a polysilicon cut-off layout structure and a polysilicon connection layer layout structure, and comprises an N Well (NW), a boron injection region (SDP), a phosphorus injection region (SDN), first to fourth fins (Fin 1-Fin 4), first to fourth active regions (AA 1-AA 4), first to twelfth Fin connection layers (M01_ 1-M01 _12), first to tenth polysilicon (PO 1-PO 10), first to sixth polysilicon connection layers (M02_ 1-M02 _6) and first to fourth polysilicon cut-off layers (POC 1-POC 4).
The first layout area is located at the upper left part of the layout of the standard unit, the second layout area is located at the upper right part of the layout of the standard unit, the third layout area is located at the lower left part of the layout of the standard unit, and the fourth layout area is located at the lower right part of the layout of the standard unit.
The first layout area comprises a first PMOS transistor and a second PMOS transistor, the second layout area comprises a third PMOS transistor and a fourth PMOS transistor, the third layout area comprises a first NMOS transistor and a second NMOS transistor, and the fourth layout area comprises a third NMOS transistor and a fourth NMOS transistor.
The gate of the first PMOS transistor is connected with the same input signal as the gate of the first NMOS transistor, the input signal of the second PMOS transistor is connected with the same input signal as the third NMOS transistor, the input signal of the second NMOS transistor is connected with the same input signal as the third PMOS transistor, and the gate of the fourth PMOS transistor is connected with the same input signal as the gate of the fourth NMOS transistor.
In the upper and lower edge layout structures, the central line of the first polysilicon truncation layer is consistent with the upper edges of the first polysilicon to the eighth polysilicon and the upper edges of the first fin connecting layer to the sixth fin connecting layer and forms the upper edge of the layout structure of the standard cell, and the central line of the second polysilicon truncation layer is consistent with the lower edge of the first polysilicon, the lower edge of the second polysilicon, the lower edge of the ninth polysilicon, the lower edge of the fourth polysilicon, the lower edge of the fifth polysilicon, the lower edge of the tenth polysilicon, the lower edge of the seventh polysilicon, the lower edge of the eighth polysilicon and the lower edge of the seventh fin connecting layer to the twelfth fin connecting layer and forms the lower edge of the layout structure of the standard cell.
In the fin type transistor layout structure, the first polycrystalline silicon and the first active region form a left edge of the first active region, the fourth polycrystalline silicon and the first active region form a right edge of the first active region, the fifth polycrystalline silicon and the second active region form a left edge of the second active region, the eighth polycrystalline silicon and the second active region form a right edge of the second active region, the first polycrystalline silicon and the third active region form a left edge of the third active region, the fourth polycrystalline silicon and the third active region form a right edge of the third active region, the fifth polycrystalline silicon and the fourth active region form a left edge of the fourth active region, and the eighth polycrystalline silicon and the fourth active region form a right edge of the fourth active region.
In the polysilicon truncation layer layout structure, the third polysilicon truncation layer and the fourth polysilicon truncation layer have the same graphic specification, and the central line of the third polysilicon truncation layer and the central line of the fourth polysilicon truncation layer are consistent with the lower edge of the boron injection region, the lower edge of the N well and the upper edge of the phosphorus injection region.
The third polycrystalline silicon is located between the first polycrystalline silicon interception layer and the third polycrystalline silicon interception layer, the ninth polycrystalline silicon is located between the third polycrystalline silicon interception layer and the second polycrystalline silicon interception layer, the sixth polycrystalline silicon is located between the first polycrystalline silicon interception layer and the fourth polycrystalline silicon interception layer, and the tenth polycrystalline silicon is located between the fourth polycrystalline silicon interception layer and the second polycrystalline silicon interception layer.
The layout structure comprises eight polycrystalline silicon tracks, the third polycrystalline silicon and the ninth polycrystalline silicon are located on the same track, and the sixth polycrystalline silicon and the tenth polycrystalline silicon are located on the same track.
In the layout structure of the polycrystalline silicon connecting layer, the second polycrystalline silicon connecting layer and the third polycrystalline silicon connecting layer adopt a first graphic specification, and the side length ratio of the first graphic specification is L1: h1 is 2.55: 1, the first polysilicon connecting layer, the fourth polysilicon connecting layer, the fifth polysilicon connecting layer and the sixth polysilicon connecting layer adopt a second graphic specification, and the side length ratio L2 of the second graphic specification is as follows: h2 is 1: 1, and H1: h2 is 0.8: 1.
the first polycrystalline silicon connecting layer is connected with the second polycrystalline silicon, the second polycrystalline silicon connecting layer is connected with the third polycrystalline silicon, the third polycrystalline silicon connecting layer is connected with the sixth polycrystalline silicon, the fourth polycrystalline silicon connecting layer is connected with the ninth polycrystalline silicon, the fifth polycrystalline silicon connecting layer is connected with the tenth polycrystalline silicon, and the sixth polycrystalline silicon connecting layer is connected with the seventh polycrystalline silicon.
The first PMOS transistor consists of a first active region, second polysilicon, a first fin, a second fin, a first fin connecting layer and a second fin connecting layer, and is positioned in a region where the N well and the boron injection region are intersected; the grid electrode of the first PMOS transistor is connected with a first signal, and the first signal is introduced by the first polycrystalline silicon connecting layer connected with the second polycrystalline silicon.
The second PMOS transistor consists of a first active region, third polysilicon, a first fin, a second fin connecting layer and a third fin connecting layer, and is positioned in a region where the N well and the boron injection region are intersected; the grid electrode of the second PMOS transistor is connected with a second signal, the second signal is introduced by the second polycrystalline silicon connecting layer connected with the third polycrystalline silicon, and the source electrode of the second PMOS transistor and the drain electrode of the first PMOS transistor share a first active region.
The third PMOS transistor consists of a second active region, sixth polycrystalline silicon, a first fin, a second fin, a fourth fin connecting layer and a fifth fin connecting layer, and is positioned in a region where the N well and the boron injection region are intersected; and the grid electrode of the third PMOS transistor is connected with a third signal, and the third signal is introduced by the third polysilicon connecting layer connected with the sixth polysilicon.
The fourth PMOS transistor consists of a second active region, seventh polycrystalline silicon, a first fin, a second fin, a fifth fin connecting layer and a sixth fin connecting layer, and is positioned in a region where the N well and the boron injection region are intersected; the grid electrode of the fourth PMOS transistor is connected with a fourth signal, the fourth signal is introduced by the sixth polycrystalline silicon connecting layer connected with the seventh polycrystalline silicon, and the drain electrode of the fourth PMOS transistor and the source electrode of the third PMOS transistor share a second active region.
The first NMOS transistor consists of a third active region, second polysilicon, a third fin, a fourth fin, a seventh fin connecting layer and an eighth fin connecting layer, and is positioned in the phosphorus injection region; the grid electrode of the first NMOS transistor is connected with the grid electrode of the first PMOS transistor and is connected with a first signal.
The second NMOS transistor consists of a third active region, ninth polycrystalline silicon, a third fin, a fourth fin, an eighth fin connecting layer and a ninth fin connecting layer, and is positioned in the phosphorus injection region; the grid electrode of the second NMOS transistor is connected with a third signal, the third signal is introduced by the fourth polycrystalline silicon connecting layer connected with the ninth polycrystalline silicon, and the source electrode of the second NMOS transistor and the drain electrode of the first NMOS transistor share a third active region.
The third NMOS transistor consists of a fourth active region, tenth polycrystalline silicon, a third fin, a fourth fin, a tenth fin connecting layer and an eleventh fin connecting layer, and is positioned in the phosphorus injection region; and the grid electrode of the third NMOS transistor is connected with a second signal, and the second signal is introduced by the fifth polycrystalline silicon connecting layer connected with the tenth polycrystalline silicon.
The fourth NMOS transistor consists of a fourth active region, seventh polycrystalline silicon, a third fin, a fourth fin, an eleventh fin connecting layer and a twelfth fin connecting layer, and is positioned in the phosphorus injection region; the grid electrode of the fourth NMOS transistor is connected with the grid electrode of the fourth PMOS transistor and connected with a fourth signal, and the drain electrode of the fourth NMOS transistor and the source electrode of the third NMOS transistor share a fourth active region.
Compared with the prior layout structure based on FinFET standard cells, the invention adds a third polysilicon truncation layer and a fourth polysilicon truncation layer, utilizes the third polysilicon truncation layer to divide polysilicon on the same track into third polysilicon and ninth polysilicon, utilizes the fourth polysilicon truncation layer to divide polysilicon on the same track into sixth polysilicon and tenth polysilicon, adopts the combination of polysilicon connecting layers with two different graphic specifications and the added polysilicon truncation layers under the condition of the same height as the traditional standard cell layout according to the requirement of a design rule, realizes that two different input signals can be simultaneously introduced on the same polysilicon track, inputs CK1 signals into the third polysilicon and the tenth polysilicon and inputs CKb signals into the sixth polysilicon and the ninth polysilicon aiming at the clock signal input structure of a D trigger, the active area layout (4 independent AA areas) of the invention is more compact, and can be realized by using four polysilicon tracks, and the layout area of the standard cell is reduced by 22.2 percent.
Drawings
FIG. 1 is a circuit diagram of a clock signal input structure;
FIG. 2 is a schematic diagram of a standard cell layout structure based on clock signal connections of FinFETs;
FIG. 3 is a schematic diagram of a layout structure of a labeling unit according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein it is shown in the accompanying drawings, wherein the specific embodiments are by way of illustration. In the following description, specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced or applied in different embodiments, and the details may be based on different viewpoints and applications, and may be widely spread and replaced by those skilled in the art without departing from the spirit of the present invention.
According to the layout structure based on the FinFET small-area standard cell, an intermediate polycrystalline silicon truncation layer is further formed between a first polycrystalline silicon truncation layer of which the central line forms the upper edge of the standard cell and a second polycrystalline silicon truncation layer of which the central line forms the lower edge of the standard cell, polycrystalline silicon on the same track is divided into two parts of polycrystalline silicon through the intermediate polycrystalline silicon truncation layer, and different input signals are respectively introduced into the two parts of polycrystalline silicon through two polycrystalline silicon connection layers with different graphic specifications.
As shown in fig. 3, the layout structure of the standard cell is divided into a first layout region, a second layout region, a third layout region, and a fourth layout region. The layout structure of the standard unit comprises an upper edge layout structure, a lower edge layout structure, a Fin transistor layout structure, a polysilicon cut-off layout structure and a polysilicon connecting layer layout structure, and comprises an N Well (NW), a boron injection region (SDP), a phosphorus injection region (SDN), first to fourth fins (Fin 1-Fin 4), first to fourth active regions (AA 1-AA 4), first to twelfth Fin connecting layers (M01_ 1-M01 _12), first to tenth polysilicon (PO 1-PO 10), first to sixth polysilicon connecting layers (M02_ 1-M02 _6) and first to fourth polysilicon cut-off layers (POC 1-POC 4).
The first layout area is located in an upper left portion of a layout of the standard cell and includes a first PMOS transistor and a second PMOS transistor.
The second layout area is located at the upper right part of the layout of the standard cell and includes a third PMOS transistor and a fourth PMOS transistor.
The third layout area is positioned at the lower left part of the layout of the standard unit and comprises a first NMOS transistor and a second NMOS transistor.
And the fourth layout area is positioned at the lower right part of the layout of the standard unit and comprises a third NMOS transistor and a fourth NMOS transistor.
The gate of the first PMOS transistor is connected with the same input signal as the gate of the first NMOS transistor, the input signal of the second PMOS transistor is connected with the same input signal as the third NMOS transistor, the input signal of the second NMOS transistor is connected with the same input signal as the third PMOS transistor, and the gate of the fourth PMOS transistor is connected with the same input signal as the gate of the fourth NMOS transistor.
In the layout structure of the upper and lower edges, the central line of the first polysilicon truncation layer POC1 is consistent with the upper edges of the first polysilicon PO1 to the eighth polysilicon PO8 and the upper edges of the first fin connecting layer to the sixth fin connecting layers M01_1 to M01_6 and constitutes the upper edge of the layout structure of the standard cell, the central line of the second polysilicon truncation layer POC2 is consistent with the lower edge of the first polysilicon PO1, the lower edge of the second polysilicon PO2, the lower edge of the ninth polysilicon PO9, the lower edge of the fourth polysilicon PO4, the lower edge of the fifth polysilicon PO5, the lower edge of the tenth polysilicon PO10, the lower edge of the seventh polysilicon PO7, the lower edge of the eighth polysilicon PO8, and the lower edges of the seventh fin connecting layers M01_7 to M01_12 to form the lower edge of the layout structure of the standard cell.
In the fin transistor layout structure, the first polysilicon PO1 and the first active region AA1 form a left edge of a first active region AA1, the fourth polysilicon PO4 and the first active region AA1 form a right edge of a first active region AA1, the fifth polysilicon PO5 and the second active region AA2 form a left edge of a second active region AA2, the eighth polysilicon PO8 and the second active region AA2 form a right edge of a second active region AA2, the first polysilicon PO1 and the third active region AA3 form a left edge of a third active region AA3, the fourth polysilicon PO4 and the third active region AA3 form a right edge of a third active region AA3, the fifth polysilicon PO5 and the fourth active region AA4 form a left edge of a fourth active region AA4, and the eighth polysilicon PO8 and the fourth active region AA4 form a right edge of a fourth active region AA 4.
In the polysilicon truncation layer layout structure, the graphic specifications of the third polysilicon truncation layer POC3 and the fourth polysilicon truncation layer POC4 are the same, and the central line of the third polysilicon truncation layer POC3 and the central line of the fourth polysilicon truncation layer POC4 are consistent with the lower edge of the boron injection region SDP, the lower edge of the N well NW, and the upper edge of the phosphorus injection region SDN.
The third poly PO3 is located between the first poly truncation layer POC1 and the third poly truncation layer POC3, the ninth poly PO9 is located between the third poly truncation layer POC3 and the second poly truncation layer POC2, the sixth poly PO6 is located between the first poly truncation layer POC1 and the fourth poly truncation layer POC4, and the tenth poly PO10 is located between the fourth poly truncation layer POC4 and the second poly truncation layer POC 2.
As shown in fig. 3, the layout structure has eight polysilicon tracks, the third polysilicon PO3 and the ninth polysilicon PO9 are located on the same track, and the sixth polysilicon PO6 and the tenth polysilicon PO10 are located on the same track.
In the layout structure of the polysilicon connecting layer, the second polysilicon connecting layer M02_2 and the third polysilicon connecting layer M02_3 adopt a first pattern specification, and the side length ratio of the first pattern specification is L1: h1 is 2.55: 1, the first polysilicon connecting layer M02_1, the fourth polysilicon connecting layer M02_4, the fifth polysilicon connecting layer M02_5 and the sixth polysilicon connecting layer M02_6 adopt a second graphic specification, wherein the side length ratio of the second graphic specification is L2: h2 is 1: 1, and H1: h2 is 0.8: 1, as shown in fig. 3.
The first polysilicon connecting layer M02_1 is connected to the second polysilicon PO2, the second polysilicon connecting layer M02_2 is connected to the third polysilicon PO3, the third polysilicon connecting layer M02_3 is connected to the sixth polysilicon PO6, the fourth polysilicon connecting layer M02_4 is connected to the ninth polysilicon PO9, the fifth polysilicon connecting layer M02_5 is connected to the tenth polysilicon PO10, and the sixth polysilicon connecting layer M02_6 is connected to the seventh polysilicon PO 7.
The third polysilicon PO3 and the ninth polysilicon PO9 are on the same track, but the second polysilicon connecting layer M02_2 and the fourth polysilicon connecting layer M02_4 have different pattern specifications, so that two different input signals can be simultaneously introduced into the same polysilicon track.
The first PMOS transistor consists of a first active region AA1, a second polysilicon PO2, a first Fin Fin1, a second Fin Fin2, a first Fin connection layer M01_1 and a second Fin connection layer M01_2, and is positioned in a region where the N well and the boron injection region SDP intersect; the gate of the first PMOS transistor is connected to a first signal, and the first signal is introduced from the first poly connecting layer M02_1 connected to the second poly PO 2.
The second PMOS transistor is composed of a first active region AA1, a third polysilicon PO3, a first Fin1, a second Fin2, a second Fin connection layer M01_2 and a third Fin connection layer M01_3, and is located in a region where the N-well and the boron implantation region SDP intersect; the gate of the second PMOS transistor is connected to a second signal, the second signal is introduced from the second poly interconnect layer M02_2 connected to the third poly PO3, and the source of the second PMOS transistor and the drain of the first PMOS transistor share a first active region AA 1.
The third PMOS transistor is composed of a second active region AA2, a sixth polysilicon PO6, a first Fin1, a second Fin2, a fourth Fin connection layer M01_4 and a fifth Fin connection layer M01_5, and is located in a region where the N-well and the boron implantation region SDP intersect; the gate of the third PMOS transistor is connected to a third signal, and the third signal is introduced from the third poly connecting layer M02_3 connected to the sixth poly PO 6.
The fourth PMOS transistor is composed of a second active region AA2, a seventh polysilicon PO7, a first Fin1, a second Fin2, a fifth Fin connection layer M01_5 and a sixth Fin connection layer M01_6, and is located in a region where the N-well and the boron implantation region SDP intersect; the gate of the fourth PMOS transistor is connected to a fourth signal, the fourth signal is introduced from the sixth polysilicon connection layer M02_6 connected to the seventh polysilicon PO7, and the drain of the fourth PMOS transistor and the source of the third PMOS transistor share a second active region AA 2.
The first NMOS transistor is composed of a third active region AA3, a second polysilicon PO2, a third Fin3, a fourth Fin4, and seventh and eighth Fin connection layers M01_7 and M01_8, and is located in a phosphorus implantation region SDN; the grid electrode of the first NMOS transistor is connected with the grid electrode of the first PMOS transistor and is connected with a first signal.
The second NMOS transistor is composed of a third active region AA3, a ninth polysilicon PO9, a third Fin3, a fourth Fin4, and eighth and ninth Fin connection layers M01_8 and M01_9, and is located in the phosphorus implantation region SDN; the gate of the second NMOS transistor is connected to a third signal, the third signal is introduced from the fourth polysilicon connection layer M02_4 connected to the ninth polysilicon PO9, and the source of the second NMOS transistor and the drain of the first NMOS transistor share a third active region AA 3.
The third NMOS transistor is composed of a fourth active region AA4, a tenth polysilicon PO10, a third Fin3, a fourth Fin4, and tenth Fin connection layers M01_10 and eleventh Fin connection layers M01_11, and is located in the phosphorus implantation region SDN; the gate of the third NMOS transistor is connected to a second signal, which is introduced by the fifth poly connection layer M02_5 connected to the tenth poly PO 10.
The fourth NMOS transistor is composed of a fourth active region AA4, a seventh polysilicon PO7, a third Fin3, a fourth Fin4, an eleventh Fin connection layer M01_11 and a twelfth Fin connection layer M01_12, and is located in the phosphorus implantation region SDN; the gate of the fourth NMOS transistor is connected to the gate of the fourth PMOS transistor and receives a fourth signal, and the drain of the fourth NMOS transistor and the source of the third NMOS transistor share a fourth active region AA 4.
Compared with the prior layout structure based on FinFET standard cells, the invention adds a third polysilicon truncation layer and a fourth polysilicon truncation layer, utilizes the third polysilicon truncation layer to divide polysilicon on the same track into third polysilicon and ninth polysilicon, utilizes the fourth polysilicon truncation layer to divide polysilicon on the same track into sixth polysilicon and tenth polysilicon, adopts the combination of polysilicon connecting layers with two different graphic specifications and the added polysilicon truncation layers under the condition of the same height as the traditional standard cell layout according to the requirement of a design rule, realizes that two different input signals can be simultaneously introduced on the same polysilicon track, inputs CK1 signals into the third polysilicon and the tenth polysilicon and inputs CKb signals into the sixth polysilicon and the ninth polysilicon aiming at the clock signal input structure of a D trigger, the active area layout (4 independent AA areas) of the invention is more compact, and can be realized by using four polysilicon tracks, thereby reducing the layout area of the standard unit.
The present invention has been described in detail with reference to the specific embodiments, which are merely preferred embodiments of the present invention, and the present invention is not limited to the above embodiments. Equivalent alterations and modifications made by those skilled in the art without departing from the principle of the invention should be considered to be within the technical scope of the invention.

Claims (21)

1. A layout structure based on a FinFET small-area standard cell is characterized in that an intermediate polycrystalline silicon truncation layer is further formed between a first polycrystalline silicon truncation layer of which the central line forms the upper edge of the standard cell and a second polycrystalline silicon truncation layer of which the central line forms the lower edge of the standard cell, polycrystalline silicon on the same track is divided into two parts of polycrystalline silicon through the intermediate polycrystalline silicon truncation layer, and two polycrystalline silicon connection layers with different graphic specifications respectively introduce different input signals through the two parts of polycrystalline silicon.
2. The FinFET small-area standard cell-based layout structure of claim 1, wherein the standard cell layout structure is divided into a first layout region, a second layout region, a third layout region and a fourth layout region.
3. The FinFET small-area standard cell-based layout structure of claim 2, wherein the standard cell layout structure comprises an upper and lower edge layout structure, a Fin-type transistor layout structure, a polysilicon truncation layer layout structure, and a polysilicon connection layer layout structure, and comprises an N-well, a boron injection region SDP, a phosphorus injection region SDN, first to fourth fins Fin 1-Fin 4, first to fourth active regions AA 1-AA 4, first to twelfth Fin connection layers M01_ 1-M01 _12, first to tenth polysilicon PO 1-PO 10, first to sixth polysilicon connection layers M02_ 1-M02 _6, and first to fourth polysilicon truncation layers POC 1-POC 4.
4. The FinFET small-area standard cell-based layout structure according to claim 3, wherein the first layout area is located at the upper left part of the standard cell layout, the second layout area is located at the upper right part of the standard cell layout, the third layout area is located at the lower left part of the standard cell layout, and the fourth layout area is located at the lower right part of the standard cell layout.
5. The FinFET small-area standard cell-based layout structure of claim 4, wherein the first layout area comprises a first PMOS transistor and a second PMOS transistor, the second layout area comprises a third PMOS transistor and a fourth PMOS transistor, the third layout area comprises a first NMOS transistor and a second NMOS transistor, and the fourth layout area comprises a third NMOS transistor and a fourth NMOS transistor.
6. The FinFET small-area standard cell-based layout structure of claim 4, wherein a gate of the first PMOS transistor is connected to the same input signal as a gate of the first NMOS transistor, an input signal of the second PMOS transistor is connected to the same input signal as a gate of the third NMOS transistor, an input signal of the second NMOS transistor is connected to the same input signal as a gate of the third PMOS transistor, and an input signal of the fourth PMOS transistor is connected to the same input signal as a gate of the fourth NMOS transistor.
7. The FinFET small area standard cell-based layout structure of claim 3, characterized in that in the upper and lower edge layout structures, the central line of the first polysilicon truncation layer is consistent with the upper edges of the first polysilicon to the eighth polysilicon and the upper edges of the first fin connecting layer to the sixth fin connecting layer and forms the upper edge of the layout structure of the standard cell, the central line of the second polysilicon truncation layer is consistent with the lower edge of the first polysilicon, the lower edge of the second polysilicon, the lower edge of the ninth polysilicon, the lower edge of the fourth polysilicon, the lower edge of the fifth polysilicon, the lower edge of the tenth polysilicon, the lower edge of the seventh polysilicon, the lower edge of the eighth polysilicon, and the lower edges of the seventh fin connecting layer to the twelfth fin connecting layer, and forms the lower edge of the layout structure of the standard cell.
8. The FinFET small area standard cell-based layout structure of claim 3, wherein in the fin-type transistor layout structure, the first polysilicon and the first active region constitute a left edge of the first active region, the fourth polysilicon and the first active region constitute the right edge of the first active region, the fifth polysilicon and the second active region constitute the left edge of the second active region, the eighth polysilicon and the second active region constitute a right edge of a second active region, the first polysilicon and the third active region constitute a left edge of a third active region, the fourth polysilicon and the third active region form the right edge of the third active region, the fifth polysilicon and the fourth active region form the left edge of the fourth active region, and the eighth polysilicon and the fourth active region form the right edge of the fourth active region.
9. The FinFET small-area standard cell-based layout structure of claim 3, wherein in the polysilicon truncation layer layout structure, the pattern specifications of the third polysilicon truncation layer and the fourth polysilicon truncation layer are the same, and the central line of the third polysilicon truncation layer and the central line of the fourth polysilicon truncation layer are consistent with the lower edge of the boron injection region, the lower edge of the N well and the upper edge of the phosphorus injection region.
10. The FinFET small-area standard cell-based layout structure of claim 9, wherein the third polysilicon is located between the first polysilicon truncation layer and the third polysilicon truncation layer, the ninth polysilicon is located between the third polysilicon truncation layer and the second polysilicon truncation layer, the sixth polysilicon is located between the first polysilicon truncation layer and the fourth polysilicon truncation layer, and the tenth polysilicon is located between the fourth polysilicon truncation layer and the second polysilicon truncation layer.
11. The FinFET small-area standard cell-based layout structure of claim 10, wherein the layout structure has eight polysilicon tracks, the third polysilicon and the ninth polysilicon are located on a same track, and the sixth polysilicon and the tenth polysilicon are located on a same track.
12. The FinFET small-area standard cell-based layout structure of claim 3, wherein in the polysilicon connection layer layout structure, the second polysilicon connection layer and the third polysilicon connection layer adopt a first graphic specification, and the side length ratio of the first graphic specification is L1: h1 is 2.55: 1, the first polysilicon connecting layer, the fourth polysilicon connecting layer, the fifth polysilicon connecting layer and the sixth polysilicon connecting layer adopt a second graphic specification, and the side length ratio L2 of the second graphic specification is as follows: h2 is 1: 1, and H1: h2 is 0.8: 1.
13. the FinFET small-area standard cell-based layout structure of claim 12, wherein the first polysilicon connection layer connects to the second polysilicon, the second polysilicon connection layer connects to the third polysilicon, the third polysilicon connection layer connects to the sixth polysilicon, the fourth polysilicon connection layer connects to the ninth polysilicon, the fifth polysilicon connection layer connects to the tenth polysilicon, and the sixth polysilicon connection layer connects to the seventh polysilicon.
14. The FinFET small-area standard cell-based layout structure of claim 5, wherein the first PMOS transistor is composed of a first active region, a second polysilicon, a first fin, a second fin, and a first fin connection layer and a second fin connection layer, which are located in a region where an N-well and a boron-implanted region intersect; the grid electrode of the first PMOS transistor is connected with a first signal, and the first signal is introduced by the first polycrystalline silicon connecting layer connected with the second polycrystalline silicon.
15. The FinFET small-area standard cell-based layout structure of claim 5, wherein the second PMOS transistor is composed of a first active region, a third polysilicon, a first fin, a second fin, and a second fin connection layer and a third fin connection layer, which are located in a region where an N-well and a boron implantation region intersect; the grid electrode of the second PMOS transistor is connected with a second signal, the second signal is introduced by the second polycrystalline silicon connecting layer connected with the third polycrystalline silicon, and the source electrode of the second PMOS transistor and the drain electrode of the first PMOS transistor share a first active region.
16. The FinFET small-area standard cell-based layout structure of claim 5, wherein the third PMOS transistor is composed of a second active region, a sixth polysilicon, a first fin, a second fin, and fourth and fifth fin connection layers, which are located in a region where an N-well and a boron-implanted region intersect; and the grid electrode of the third PMOS transistor is connected with a third signal, and the third signal is introduced by the third polysilicon connecting layer connected with the sixth polysilicon.
17. The FinFET small-area standard cell-based layout structure of claim 5, wherein the fourth PMOS transistor is composed of a second active region, a seventh polysilicon, a first fin, a second fin, and fifth and sixth fin connection layers, which are located in a region where an N-well and a boron-implanted region intersect; the grid electrode of the fourth PMOS transistor is connected with a fourth signal, the fourth signal is introduced by the sixth polycrystalline silicon connecting layer connected with the seventh polycrystalline silicon, and the drain electrode of the fourth PMOS transistor and the source electrode of the third PMOS transistor share a second active region.
18. The FinFET small area standard cell-based layout structure of claim 5, wherein the first NMOS transistor is comprised of a third active region, a second polysilicon, a third fin, a fourth fin, and seventh and eighth fin connection layers, which are located in a phosphorus implanted region; the grid electrode of the first NMOS transistor is connected with the grid electrode of the first PMOS transistor and is connected with a first signal.
19. The FinFET small area standard cell-based layout structure of claim 5, wherein the second NMOS transistor is comprised of a third active region, a ninth polysilicon, a third fin, a fourth fin, and eighth and ninth fin connection layers, which are located in a phosphorus implanted region; the grid electrode of the second NMOS transistor is connected with a third signal, the third signal is introduced by the fourth polycrystalline silicon connecting layer connected with the ninth polycrystalline silicon, and the source electrode of the second NMOS transistor and the drain electrode of the first NMOS transistor share a third active region.
20. The FinFET small area standard cell-based layout structure of claim 5, wherein the third NMOS transistor is comprised of a fourth active region, a tenth polysilicon, a third fin, a fourth fin, and tenth and eleventh fin connection layers, which are located in a phosphorus implanted region; and the grid electrode of the third NMOS transistor is connected with a second signal, and the second signal is introduced by the fifth polycrystalline silicon connecting layer connected with the tenth polycrystalline silicon.
21. The FinFET small-area standard cell-based layout structure of claim 5, wherein the fourth NMOS transistor is composed of a fourth active region, a seventh poly-silicon, a third fin, a fourth fin, and eleventh and twelfth fin connection layers, which are located in a phosphorus-implanted region; the grid electrode of the fourth NMOS transistor is connected with the grid electrode of the fourth PMOS transistor and connected with a fourth signal, and the drain electrode of the fourth NMOS transistor and the source electrode of the third NMOS transistor share a fourth active region.
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