JP6652451B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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JP6652451B2
JP6652451B2 JP2016117617A JP2016117617A JP6652451B2 JP 6652451 B2 JP6652451 B2 JP 6652451B2 JP 2016117617 A JP2016117617 A JP 2016117617A JP 2016117617 A JP2016117617 A JP 2016117617A JP 6652451 B2 JP6652451 B2 JP 6652451B2
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film
gate electrode
region
semiconductor device
insulating film
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JP2017224666A (ja
JP2017224666A5 (enExample
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直 山口
直 山口
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority to JP2016117617A priority Critical patent/JP6652451B2/ja
Priority to US15/482,239 priority patent/US9899403B2/en
Priority to CN201710356508.9A priority patent/CN107507864B/zh
Priority to TW106118450A priority patent/TW201810677A/zh
Publication of JP2017224666A publication Critical patent/JP2017224666A/ja
Priority to US15/879,257 priority patent/US10229925B2/en
Publication of JP2017224666A5 publication Critical patent/JP2017224666A5/ja
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    • HELECTRICITY
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    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
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    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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    • H10D30/0212Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
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    • H10D30/024Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
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    • H10D30/0413Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
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    • H10D30/694IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/696IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having at least one additional gate, e.g. program gate, erase gate or select gate
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    • H10D62/113Isolations within a component, i.e. internal isolations
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    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
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    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213Channel regions of field-effect devices
    • H10D62/221Channel regions of field-effect devices of FETs
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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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  • Semiconductor Memories (AREA)
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  • Materials Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2016117617A 2016-06-14 2016-06-14 半導体装置およびその製造方法 Active JP6652451B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2016117617A JP6652451B2 (ja) 2016-06-14 2016-06-14 半導体装置およびその製造方法
US15/482,239 US9899403B2 (en) 2016-06-14 2017-04-07 Semiconductor device and method of manufacturing the same
CN201710356508.9A CN107507864B (zh) 2016-06-14 2017-05-19 半导体器件及其制造方法
TW106118450A TW201810677A (zh) 2016-06-14 2017-06-05 半導體裝置及其製造方法
US15/879,257 US10229925B2 (en) 2016-06-14 2018-01-24 Semiconductor device and method of manufacturing the same

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JP2016117617A JP6652451B2 (ja) 2016-06-14 2016-06-14 半導体装置およびその製造方法

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JP2017224666A JP2017224666A (ja) 2017-12-21
JP2017224666A5 JP2017224666A5 (enExample) 2018-12-27
JP6652451B2 true JP6652451B2 (ja) 2020-02-26

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JP2019117913A (ja) * 2017-12-27 2019-07-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6920192B2 (ja) * 2017-12-28 2021-08-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10515954B2 (en) * 2018-03-18 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having fin structures of varying dimensions
US10312247B1 (en) * 2018-03-22 2019-06-04 Silicon Storage Technology, Inc. Two transistor FinFET-based split gate non-volatile floating gate flash memory and method of fabrication
JP6998267B2 (ja) * 2018-05-08 2022-01-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP7053388B2 (ja) * 2018-06-28 2022-04-12 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN110828380B (zh) * 2018-08-14 2022-06-17 中芯国际集成电路制造(上海)有限公司 静态存储单元的形成方法及静态存储单元
CN110828460B (zh) * 2018-08-14 2022-07-19 中芯国际集成电路制造(北京)有限公司 半导体器件及其形成方法
US11195923B2 (en) * 2018-12-21 2021-12-07 Applied Materials, Inc. Method of fabricating a semiconductor device having reduced contact resistance
JP7232081B2 (ja) * 2019-03-01 2023-03-02 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP7200054B2 (ja) * 2019-06-24 2023-01-06 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2021027096A (ja) * 2019-08-01 2021-02-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
KR102624201B1 (ko) * 2019-09-06 2024-01-15 에스케이하이닉스 주식회사 저항 변화 메모리층을 구비하는 비휘발성 메모리 장치
CN112490128B (zh) * 2019-09-12 2024-11-19 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
US20220051905A1 (en) * 2020-08-12 2022-02-17 Tokyo Electron Limited Formation of low-temperature and high-temperature in-situ doped source and drain epitaxy using selective heating for wrap-around contact and vertically stacked device architectures
CN114334817A (zh) * 2020-09-30 2022-04-12 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

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