CN107507864B - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN107507864B CN107507864B CN201710356508.9A CN201710356508A CN107507864B CN 107507864 B CN107507864 B CN 107507864B CN 201710356508 A CN201710356508 A CN 201710356508A CN 107507864 B CN107507864 B CN 107507864B
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- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
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- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
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- H10D30/62—Fin field-effect transistors [FinFET]
- H10D30/6211—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
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- H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/696—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having at least one additional gate, e.g. program gate, erase gate or select gate
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- H10D62/113—Isolations within a component, i.e. internal isolations
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- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
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- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
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- H10D62/221—Channel regions of field-effect devices of FETs
- H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
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- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
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- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
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- H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
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- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Composite Materials (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Non-Volatile Memory (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016-117617 | 2016-06-14 | ||
| JP2016117617A JP6652451B2 (ja) | 2016-06-14 | 2016-06-14 | 半導体装置およびその製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107507864A CN107507864A (zh) | 2017-12-22 |
| CN107507864B true CN107507864B (zh) | 2022-09-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710356508.9A Active CN107507864B (zh) | 2016-06-14 | 2017-05-19 | 半导体器件及其制造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US9899403B2 (enExample) |
| JP (1) | JP6652451B2 (enExample) |
| CN (1) | CN107507864B (enExample) |
| TW (1) | TW201810677A (enExample) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10163901B1 (en) * | 2017-06-23 | 2018-12-25 | Globalfoundries Singapore Pte. Ltd. | Method and device for embedding flash memory and logic integration in FinFET technology |
| US10700207B2 (en) * | 2017-11-30 | 2020-06-30 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device integrating backside power grid and related integrated circuit and fabrication method |
| DE102018127448B4 (de) | 2017-11-30 | 2023-06-22 | Taiwan Semiconductor Manufacturing Co. Ltd. | Metallschienenleiter für nicht-planare Halbleiter-Bauelemente |
| JP2019117855A (ja) * | 2017-12-27 | 2019-07-18 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| JP2019117913A (ja) * | 2017-12-27 | 2019-07-18 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| JP6920192B2 (ja) * | 2017-12-28 | 2021-08-18 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| US10515954B2 (en) | 2018-03-18 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having fin structures of varying dimensions |
| US10312247B1 (en) * | 2018-03-22 | 2019-06-04 | Silicon Storage Technology, Inc. | Two transistor FinFET-based split gate non-volatile floating gate flash memory and method of fabrication |
| JP6998267B2 (ja) * | 2018-05-08 | 2022-01-18 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| JP7053388B2 (ja) * | 2018-06-28 | 2022-04-12 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| CN110828380B (zh) * | 2018-08-14 | 2022-06-17 | 中芯国际集成电路制造(上海)有限公司 | 静态存储单元的形成方法及静态存储单元 |
| CN110828460B (zh) * | 2018-08-14 | 2022-07-19 | 中芯国际集成电路制造(北京)有限公司 | 半导体器件及其形成方法 |
| US11195923B2 (en) * | 2018-12-21 | 2021-12-07 | Applied Materials, Inc. | Method of fabricating a semiconductor device having reduced contact resistance |
| JP7232081B2 (ja) * | 2019-03-01 | 2023-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| JP7200054B2 (ja) * | 2019-06-24 | 2023-01-06 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| JP2021027096A (ja) * | 2019-08-01 | 2021-02-22 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| KR102624201B1 (ko) * | 2019-09-06 | 2024-01-15 | 에스케이하이닉스 주식회사 | 저항 변화 메모리층을 구비하는 비휘발성 메모리 장치 |
| CN112490128B (zh) * | 2019-09-12 | 2024-11-19 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
| US20220051905A1 (en) * | 2020-08-12 | 2022-02-17 | Tokyo Electron Limited | Formation of low-temperature and high-temperature in-situ doped source and drain epitaxy using selective heating for wrap-around contact and vertically stacked device architectures |
| CN114334817A (zh) * | 2020-09-30 | 2022-04-12 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
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| JP4921755B2 (ja) * | 2005-09-16 | 2012-04-25 | 株式会社東芝 | 半導体装置 |
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| JP2017224666A (ja) | 2017-12-21 |
| CN107507864A (zh) | 2017-12-22 |
| TW201810677A (zh) | 2018-03-16 |
| US9899403B2 (en) | 2018-02-20 |
| JP6652451B2 (ja) | 2020-02-26 |
| US20180166459A1 (en) | 2018-06-14 |
| US20170358592A1 (en) | 2017-12-14 |
| US10229925B2 (en) | 2019-03-12 |
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