JP6649216B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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JP6649216B2
JP6649216B2 JP2016182023A JP2016182023A JP6649216B2 JP 6649216 B2 JP6649216 B2 JP 6649216B2 JP 2016182023 A JP2016182023 A JP 2016182023A JP 2016182023 A JP2016182023 A JP 2016182023A JP 6649216 B2 JP6649216 B2 JP 6649216B2
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semiconductor region
electrode
recess
insulating portion
insulating
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JP2018046253A5 (enExample
JP2018046253A (ja
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研也 小林
研也 小林
松田　哲朗
哲朗 松田
洋輔 檜森
洋輔 檜森
俊史 西口
俊史 西口
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Toshiba Corp
Toshiba Electronic Devices and Storage Corp
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Priority to JP2016182023A priority Critical patent/JP6649216B2/ja
Priority to US15/448,126 priority patent/US9947751B2/en
Priority to CN201710377247.9A priority patent/CN107833919B/zh
Publication of JP2018046253A publication Critical patent/JP2018046253A/ja
Priority to US15/943,147 priority patent/US11011609B2/en
Publication of JP2018046253A5 publication Critical patent/JP2018046253A5/ja
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    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
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    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
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    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
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    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
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    • H10D84/8314—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having gate insulating layers with different properties

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  • Electrodes Of Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
JP2016182023A 2016-09-16 2016-09-16 半導体装置およびその製造方法 Active JP6649216B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2016182023A JP6649216B2 (ja) 2016-09-16 2016-09-16 半導体装置およびその製造方法
US15/448,126 US9947751B2 (en) 2016-09-16 2017-03-02 Semiconductor device and method of manufacturing the same
CN201710377247.9A CN107833919B (zh) 2016-09-16 2017-05-25 半导体装置及其制造方法
US15/943,147 US11011609B2 (en) 2016-09-16 2018-04-02 Method of manufacturing a semiconductor device

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JP2016182023A JP6649216B2 (ja) 2016-09-16 2016-09-16 半導体装置およびその製造方法

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