JP6478943B2 - ファンアウト半導体パッケージ及びその製造方法 - Google Patents

ファンアウト半導体パッケージ及びその製造方法 Download PDF

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Publication number
JP6478943B2
JP6478943B2 JP2016093940A JP2016093940A JP6478943B2 JP 6478943 B2 JP6478943 B2 JP 6478943B2 JP 2016093940 A JP2016093940 A JP 2016093940A JP 2016093940 A JP2016093940 A JP 2016093940A JP 6478943 B2 JP6478943 B2 JP 6478943B2
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layer
connection member
disposed
insulating layer
redistribution
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JP2016213466A5 (https=
JP2016213466A (ja
Inventor
ヒュン パク、ダエ
ヒュン パク、ダエ
キム、ハン
ヘオン ファ、カン
ヘオン ファ、カン
グヮン コ、ヨウン
グヮン コ、ヨウン
ホ シム、ジュン
ホ シム、ジュン
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/13—Containers comprising a conductive base serving as an interconnection
    • H10W76/132—Containers comprising a conductive base serving as an interconnection having other interconnections through an insulated passage in the conductive base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2016093940A 2015-05-11 2016-05-09 ファンアウト半導体パッケージ及びその製造方法 Active JP6478943B2 (ja)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
KR10-2015-0065177 2015-05-11
KR20150065177 2015-05-11
KR10-2015-0139682 2015-10-05
KR1020150139682A KR20160132751A (ko) 2015-05-11 2015-10-05 전자부품 패키지 및 그 제조방법
KR10-2016-0047455 2016-04-19
KR1020160047455A KR102002071B1 (ko) 2015-05-11 2016-04-19 팬-아웃 반도체 패키지 및 그 제조방법

Related Child Applications (1)

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JP2018166145A Division JP6683780B2 (ja) 2015-05-11 2018-09-05 ファンアウト半導体パッケージ及びその製造方法

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JP2016213466A JP2016213466A (ja) 2016-12-15
JP2016213466A5 JP2016213466A5 (https=) 2017-06-29
JP6478943B2 true JP6478943B2 (ja) 2019-03-06

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JP2018166145A Active JP6683780B2 (ja) 2015-05-11 2018-09-05 ファンアウト半導体パッケージ及びその製造方法

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Families Citing this family (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018097410A1 (ko) 2016-11-28 2018-05-31 주식회사 네패스 신뢰성을 가지는 반도체 패키지 및 이의 제조방법
JP6815880B2 (ja) * 2017-01-25 2021-01-20 株式会社ディスコ 半導体パッケージの製造方法
KR102019353B1 (ko) * 2017-04-07 2019-09-09 삼성전자주식회사 팬-아웃 센서 패키지 및 이를 포함하는 광학방식 지문센서 모듈
US10644046B2 (en) 2017-04-07 2020-05-05 Samsung Electronics Co., Ltd. Fan-out sensor package and optical fingerprint sensor module including the same
US20180337454A1 (en) * 2017-05-16 2018-11-22 Samsung Electro-Mechanics Co., Ltd. Filter module and front end module including the same
CN108878380B (zh) 2017-05-16 2022-01-21 三星电机株式会社 扇出型电子器件封装件
US20190006305A1 (en) * 2017-06-29 2019-01-03 Powertech Technology Inc. Semiconductor package structure and manufacturing method thereof
KR102018616B1 (ko) * 2017-07-04 2019-09-06 삼성전자주식회사 반도체 장치
KR102077455B1 (ko) * 2017-07-04 2020-02-14 삼성전자주식회사 반도체 장치
KR102081086B1 (ko) * 2017-07-07 2020-02-25 삼성전자주식회사 팬-아웃 반도체 패키지 모듈
KR20190013051A (ko) 2017-07-31 2019-02-11 삼성전기주식회사 팬-아웃 반도체 패키지
US10453821B2 (en) * 2017-08-04 2019-10-22 Samsung Electronics Co., Ltd. Connection system of semiconductor packages
KR101982054B1 (ko) * 2017-08-10 2019-05-24 삼성전기주식회사 팬-아웃 반도체 패키지
KR102440119B1 (ko) * 2017-08-10 2022-09-05 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR102117463B1 (ko) * 2017-08-18 2020-06-02 삼성전기주식회사 팬-아웃 반도체 패키지
KR102008343B1 (ko) 2017-09-27 2019-08-07 삼성전자주식회사 팬-아웃 반도체 패키지
WO2019073801A1 (ja) * 2017-10-11 2019-04-18 ソニーセミコンダクタソリューションズ株式会社 半導体装置およびその製造方法
KR102019349B1 (ko) * 2017-10-19 2019-09-09 삼성전자주식회사 반도체 패키지
KR101922884B1 (ko) * 2017-10-26 2018-11-28 삼성전기 주식회사 팬-아웃 반도체 패키지
KR101901712B1 (ko) 2017-10-27 2018-09-27 삼성전기 주식회사 팬-아웃 반도체 패키지
KR101939046B1 (ko) 2017-10-31 2019-01-16 삼성전기 주식회사 팬-아웃 반도체 패키지
TWI736780B (zh) 2017-10-31 2021-08-21 台灣積體電路製造股份有限公司 晶片封裝及其形成方法
US11322449B2 (en) 2017-10-31 2022-05-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package with fan-out structures
KR101963292B1 (ko) 2017-10-31 2019-03-28 삼성전기주식회사 팬-아웃 반도체 패키지
KR101963293B1 (ko) * 2017-11-01 2019-03-28 삼성전기주식회사 팬-아웃 반도체 패키지
KR101942744B1 (ko) * 2017-11-03 2019-01-28 삼성전기 주식회사 팬-아웃 반도체 패키지
KR101933423B1 (ko) 2017-11-28 2018-12-28 삼성전기 주식회사 팬-아웃 센서 패키지
WO2019111874A1 (ja) * 2017-12-05 2019-06-13 株式会社村田製作所 モジュール
WO2019111873A1 (ja) 2017-12-05 2019-06-13 株式会社村田製作所 モジュール
KR102025906B1 (ko) 2017-12-06 2019-11-04 삼성전자주식회사 안테나 모듈
KR101912290B1 (ko) 2017-12-06 2018-10-29 삼성전기 주식회사 팬-아웃 반도체 패키지
KR101982058B1 (ko) 2017-12-06 2019-05-24 삼성전기주식회사 팬-아웃 반도체 패키지
KR102061852B1 (ko) 2017-12-18 2020-01-02 삼성전자주식회사 반도체 패키지
KR102099749B1 (ko) * 2018-01-19 2020-04-10 삼성전자주식회사 팬-아웃 반도체 패키지
KR102015910B1 (ko) * 2018-01-24 2019-10-23 삼성전자주식회사 팬-아웃 센서 패키지
KR102063470B1 (ko) 2018-05-03 2020-01-09 삼성전자주식회사 반도체 패키지
CN112189260A (zh) 2018-05-28 2021-01-05 索尼半导体解决方案公司 成像装置
KR102556703B1 (ko) * 2018-05-30 2023-07-18 삼성전기주식회사 패키지 기판 및 그 제조방법
DE102019117844A1 (de) 2018-09-27 2020-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Integrierte-schaltung-package und verfahren
US10790162B2 (en) 2018-09-27 2020-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
WO2020067732A1 (ko) * 2018-09-28 2020-04-02 주식회사 네패스 반도체 패키지
KR102226190B1 (ko) * 2018-09-28 2021-03-11 주식회사 네패스 반도체 패키지 및 그 제조 방법
US20210358883A1 (en) * 2018-10-11 2021-11-18 Shenzhen Xiuyi Investment Development Partnership (Limited Partnership) Fan-out packaging method employing combined process
JP6777136B2 (ja) * 2018-11-20 2020-10-28 Tdk株式会社 アンテナモジュール
WO2020166567A1 (ja) * 2019-02-15 2020-08-20 株式会社村田製作所 電子モジュール及び電子モジュールの製造方法
KR102620534B1 (ko) * 2019-02-15 2024-01-03 삼성전기주식회사 반도체 패키지
CN113261094B (zh) 2019-03-07 2024-04-16 爱玻索立克公司 封装基板及包括其的半导体装置
KR102564761B1 (ko) 2019-03-07 2023-08-07 앱솔릭스 인코포레이티드 패키징 기판 및 이를 포함하는 반도체 장치
US11967542B2 (en) 2019-03-12 2024-04-23 Absolics Inc. Packaging substrate, and semiconductor device comprising same
US11652039B2 (en) 2019-03-12 2023-05-16 Absolics Inc. Packaging substrate with core layer and cavity structure and semiconductor device comprising the same
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US11981501B2 (en) 2019-03-12 2024-05-14 Absolics Inc. Loading cassette for substrate including glass and substrate loading method to which same is applied
KR102715473B1 (ko) 2019-03-13 2024-10-10 삼성전자주식회사 패키지 온 패키지 및 이를 포함하는 패키지 연결 시스템
CN114678344B (zh) 2019-03-29 2025-08-15 爱玻索立克公司 半导体用封装玻璃基板、半导体封装基板及半导体装置
KR20200129671A (ko) 2019-05-09 2020-11-18 삼성전기주식회사 패키지 온 패키지 및 이를 포함하는 패키지 연결 시스템
KR20210020673A (ko) * 2019-08-16 2021-02-24 삼성전기주식회사 인쇄회로기판
JP7104245B2 (ja) * 2019-08-23 2022-07-20 アブソリックス インコーポレイテッド パッケージング基板及びこれを含む半導体装置
WO2021117191A1 (ja) * 2019-12-12 2021-06-17 太陽誘電株式会社 部品モジュールおよびその製造方法
CN115053344A (zh) 2020-03-13 2022-09-13 株式会社半导体能源研究所 半导体装置及电子设备
WO2021205926A1 (ja) * 2020-04-08 2021-10-14 ローム株式会社 半導体装置
US11183446B1 (en) * 2020-08-17 2021-11-23 Qualcomm Incorporated X.5 layer substrate
CN114388487A (zh) * 2020-10-16 2022-04-22 虹晶科技股份有限公司 封装结构及该封装结构的制备方法
CN220065432U (zh) * 2020-12-14 2023-11-21 株式会社村田制作所 电子部件封装
CN116093060A (zh) 2021-11-08 2023-05-09 群创光电股份有限公司 电子装置及其制备方法
CN117410247A (zh) 2022-07-08 2024-01-16 群创光电股份有限公司 电子装置
KR102886060B1 (ko) * 2022-11-22 2025-11-12 앱솔릭스 인코포레이티드 패키징 기판 및 이를 포함하는 반도체 패키지
JP2025020919A (ja) * 2023-07-31 2025-02-13 株式会社東芝 半導体装置、回路基板、および回路基板の製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4028749B2 (ja) * 2002-04-15 2007-12-26 日本特殊陶業株式会社 配線基板
JP4167001B2 (ja) * 2002-04-15 2008-10-15 日本特殊陶業株式会社 配線基板の製造方法
JP2006049457A (ja) * 2004-08-03 2006-02-16 Dt Circuit Technology Co Ltd 部品内蔵配線板、部品内蔵配線板の製造方法
JP2007123524A (ja) * 2005-10-27 2007-05-17 Shinko Electric Ind Co Ltd 電子部品内蔵基板
US7425758B2 (en) * 2006-08-28 2008-09-16 Micron Technology, Inc. Metal core foldover package structures
JP5326269B2 (ja) * 2006-12-18 2013-10-30 大日本印刷株式会社 電子部品内蔵配線板、及び電子部品内蔵配線板の放熱方法
TW200917446A (en) * 2007-10-01 2009-04-16 Phoenix Prec Technology Corp Packaging substrate structure having electronic component embedded therein and fabricating method thereof
JPWO2010101167A1 (ja) * 2009-03-05 2012-09-10 日本電気株式会社 半導体装置及びその製造方法
KR101077410B1 (ko) * 2009-05-15 2011-10-26 삼성전기주식회사 방열부재를 구비한 전자부품 내장형 인쇄회로기판 및 그 제조방법
US8901724B2 (en) * 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
WO2011114766A1 (ja) * 2010-03-16 2011-09-22 日本電気株式会社 機能素子内蔵基板
JP6152254B2 (ja) * 2012-09-12 2017-06-21 新光電気工業株式会社 半導体パッケージ、半導体装置及び半導体パッケージの製造方法
JP6200178B2 (ja) * 2013-03-28 2017-09-20 新光電気工業株式会社 電子部品内蔵基板及びその製造方法
US9066424B2 (en) * 2013-07-15 2015-06-23 Hong Kong Applied Science and Technology Research Institute Company Limited Partitioned hybrid substrate for radio frequency applications
KR101514539B1 (ko) * 2013-08-29 2015-04-22 삼성전기주식회사 전자부품 내장기판

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