JP6342981B2 - 半導体発光素子及びその製造方法 - Google Patents
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Description
10、210、510 成長基板
112、2112、5112 n型半導体層
114、2114、5114 活性層
116、2116、5116 p型半導体層
110、2110、5110 半導体エピタキシャル積層
120a、120b、2120a、2120b、5120b p型電極
20、220、520、60 第1搭載基板
135、2135、5135 第1接着層
130a、130b、2130a、2130b、130b’、5120a n型電極
140、2140 金属酸化物透明導電層
150、2150 反射層
201、2201、501 第1エピタキシャルユニット
202、2202、502、501’ 第2エピタキシャルユニット
230、2230、5230 第2接着層
5280 透明金属酸化物導電層
30、530 第2搭載基板
200、300、400、500、600 半導体発光素子
2123 パターン化犠牲層
130a’、5120b’ p型延伸電極
130a’’ n型延伸電極
134 導電孔
132、232 絶縁層
202’ 第3エピタキシャルユニット
125 金属導電接続構造
120b’、1310 p型電極パッド
120b’’、1320 n型電極パッド
40 第1透明構造
410 絶縁散乱層
411、412 開口
530’ 第2搭載基板ユニット
501’ 十字形エピタキシャルユニット
260、560 ハンダ
50’、20’ サブキャリア
5000、2000 発光装置
A’、B’ 対称面
D 方向
Claims (9)
- 半導体発光素子の製造方法であって、
第1表面を有する第1基板と前記第1表面に貼り付けられた複数のエピタキシャルユニットとを含む半導体装置であって、前記第1表面が複数の第1領域及び複数の第2領域を含み、前記複数の第2領域の間に少なくとも一つの前記第1領域が含まれ、前記複数のエピタキシャルユニットが複数の第1エピタキシャルユニット及び複数の第2エピタキシャルユニットを含み、前記複数の第1エピタキシャルユニットが前記複数の第1領域に位置し、前記複数の第2エピタキシャルユニットが前記複数の第2領域に位置する半導体装置を提供するステップと、
前記第1表面と前記複数のエピタキシャルユニットとの間に第1接着層を提供するステップと、
前記複数のエピタキシャルユニットと前記第1基板との間の接着力を低減させるステップと、
前記第1表面と前記第1接着層との間に、前記複数の第2エピタキシャルユニットに対応するパターン化犠牲層を形成するステップと、
前記第1接着層と前記パターン化犠牲層を分離させることにより、少なくとも前記複数の第2エピタキシャルユニットの一部と前記第1基板を同一ステップにおいて分離させるステップとを含み、
前記複数のエピタキシャルユニットのそれぞれがn型半導体層、活性層及びp型半導体層を含む、半導体発光素子の製造方法。 - ドライエッチング、ウェットエッチング、機械力、光照射又は加熱の方式により、前記複数の第2エピタキシャルユニットと前記第1表面との間の接着力を前記複数の第1エピタキシャルユニットと前記第1表面との間の接着力より小さくするステップをさらに含む、請求項1に記載の製造方法。
- 前記複数の第1エピタキシャルユニットと前記複数の第2エピタキシャルユニットとが交互に配列されている、請求項1に記載の製造方法。
- 前記パターン化犠牲層を除去するステップをさらに含む、請求項1に記載の製造方法。
- 前記複数の第2エピタキシャルユニットの上に第2接着層を提供するステップをさらに含む、請求項1に記載の製造方法。
- 前記複数の第1エピタキシャルユニットを前記第1表面上に残すステップをさらに含む、請求項1に記載の製造方法。
- 前記複数のエピタキシャルユニットそれぞれの側壁を被覆する透明絶縁層を形成するステップとさらに含む、請求項1に記載の製造方法。
- 前記複数のエピタキシャルユニットそれぞれと前記第1接着層との間に金属電極を形成するステップをさらに含み、かつ前記金属電極が複数のエピタキシャルユニットそれぞれと電気的に接続する、請求項1に記載の製造方法。
- 前記複数のエピタキシャルユニット上にパターン化金属層を形成するステップをさらに含み、前記パターン化金属層が前記第1表面の対向側に位置する、請求項1に記載の製造方法。
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