FR2864970B1 - Substrat a support a coefficient de dilatation thermique determine - Google Patents

Substrat a support a coefficient de dilatation thermique determine

Info

Publication number
FR2864970B1
FR2864970B1 FR0400175A FR0400175A FR2864970B1 FR 2864970 B1 FR2864970 B1 FR 2864970B1 FR 0400175 A FR0400175 A FR 0400175A FR 0400175 A FR0400175 A FR 0400175A FR 2864970 B1 FR2864970 B1 FR 2864970B1
Authority
FR
France
Prior art keywords
composite support
layer
epitaxy
temperature
thermal expansion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0400175A
Other languages
English (en)
Other versions
FR2864970A1 (fr
Inventor
Yves Mathieu Levaillant
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0400175A priority Critical patent/FR2864970B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to PCT/IB2004/003762 priority patent/WO2005076345A1/fr
Priority to EP04791788A priority patent/EP1702357B1/fr
Priority to CNB2004800402057A priority patent/CN100472749C/zh
Priority to JP2006548416A priority patent/JP4745249B2/ja
Priority to KR1020067013398A priority patent/KR100855793B1/ko
Priority to AT04791788T priority patent/ATE398833T1/de
Priority to DE602004014533T priority patent/DE602004014533D1/de
Publication of FR2864970A1 publication Critical patent/FR2864970A1/fr
Application granted granted Critical
Publication of FR2864970B1 publication Critical patent/FR2864970B1/fr
Priority to US11/472,663 priority patent/US7887936B2/en
Priority to US12/983,543 priority patent/US20110094668A1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Organic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Metallurgy (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
  • Laminated Bodies (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Photovoltaic Devices (AREA)
FR0400175A 2004-01-09 2004-01-09 Substrat a support a coefficient de dilatation thermique determine Expired - Fee Related FR2864970B1 (fr)

Priority Applications (10)

Application Number Priority Date Filing Date Title
FR0400175A FR2864970B1 (fr) 2004-01-09 2004-01-09 Substrat a support a coefficient de dilatation thermique determine
DE602004014533T DE602004014533D1 (de) 2004-01-09 2004-10-28 Substrat mit bestimmtem wärmeausdehnungskoeffizienten
CNB2004800402057A CN100472749C (zh) 2004-01-09 2004-10-28 具有确定热膨胀系数的衬底
JP2006548416A JP4745249B2 (ja) 2004-01-09 2004-10-28 決定可能な熱膨張係数を有する基板
KR1020067013398A KR100855793B1 (ko) 2004-01-09 2004-10-28 확정적인 열팽창계수를 가지는 기판
AT04791788T ATE398833T1 (de) 2004-01-09 2004-10-28 Substrat mit bestimmtem wärmeausdehnungskoeffizienten
PCT/IB2004/003762 WO2005076345A1 (fr) 2004-01-09 2004-10-28 Substrat a coefficient de dilatation thermique determine
EP04791788A EP1702357B1 (fr) 2004-01-09 2004-10-28 Substrat a coefficient de dilatation thermique determine
US11/472,663 US7887936B2 (en) 2004-01-09 2006-06-21 Substrate with determinate thermal expansion coefficient
US12/983,543 US20110094668A1 (en) 2004-01-09 2011-01-03 Substrate with determinate thermal expansion coefficient

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0400175A FR2864970B1 (fr) 2004-01-09 2004-01-09 Substrat a support a coefficient de dilatation thermique determine

Publications (2)

Publication Number Publication Date
FR2864970A1 FR2864970A1 (fr) 2005-07-15
FR2864970B1 true FR2864970B1 (fr) 2006-03-03

Family

ID=34684904

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0400175A Expired - Fee Related FR2864970B1 (fr) 2004-01-09 2004-01-09 Substrat a support a coefficient de dilatation thermique determine

Country Status (9)

Country Link
US (2) US7887936B2 (fr)
EP (1) EP1702357B1 (fr)
JP (1) JP4745249B2 (fr)
KR (1) KR100855793B1 (fr)
CN (1) CN100472749C (fr)
AT (1) ATE398833T1 (fr)
DE (1) DE602004014533D1 (fr)
FR (1) FR2864970B1 (fr)
WO (1) WO2005076345A1 (fr)

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US7687372B2 (en) * 2005-04-08 2010-03-30 Versatilis Llc System and method for manufacturing thick and thin film devices using a donee layer cleaved from a crystalline donor
US7575982B2 (en) * 2006-04-14 2009-08-18 Applied Materials, Inc. Stacked-substrate processes for production of nitride semiconductor structures
WO2009061353A2 (fr) * 2007-11-02 2009-05-14 President And Fellows Of Harvard College Fabrication de couches autonomes à semi-conducteurs par traitement thermique de substrats par un polymère
FR2926674B1 (fr) * 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable
DE102009007625A1 (de) * 2008-11-14 2010-05-20 Osram Opto Semiconductors Gmbh Verbundsubstrat für einen Halbleiterchip
DE102009000514A1 (de) * 2009-01-30 2010-08-26 Robert Bosch Gmbh Verbundbauteil sowie Verfahren zum Herstellen eines Verbundbauteil
FR2947098A1 (fr) * 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
US20110177638A1 (en) * 2010-01-15 2011-07-21 Koninklijke Philips Electronics N.V. Semiconductor light emitting device with curvature control layer
DE102010046215B4 (de) 2010-09-21 2019-01-03 Infineon Technologies Austria Ag Halbleiterkörper mit verspanntem Bereich, Elektronisches Bauelement und ein Verfahren zum Erzeugen des Halbleiterkörpers.
JP5938871B2 (ja) 2010-11-15 2016-06-22 住友電気工業株式会社 ＧａＮ系膜の製造方法
US8697564B2 (en) 2010-11-16 2014-04-15 Sumitomo Electric Industries, Ltd. Method of manufacturing GaN-based film
US9184228B2 (en) 2011-03-07 2015-11-10 Sumitomo Electric Industries, Ltd. Composite base including sintered base and base surface flattening layer, and composite substrate including that composite base and semiconductor crystalline layer
CN102304760A (zh) * 2011-08-12 2012-01-04 青岛铝镓光电半导体有限公司 复合衬底及其制造方法、异质外延制备单晶厚膜的方法
EP2765226A4 (fr) 2011-10-07 2015-06-17 Sumitomo Electric Industries Procédé de fabrication de film de gan et substrat composite utilisé dans ledit procédé
CN102560676B (zh) * 2012-01-18 2014-08-06 山东大学 一种使用减薄键合结构进行GaN单晶生长的方法
US9356070B2 (en) 2012-08-15 2016-05-31 Epistar Corporation Light-emitting device
US20140048824A1 (en) 2012-08-15 2014-02-20 Epistar Corporation Light-emitting device
CN108281378B (zh) * 2012-10-12 2022-06-24 住友电气工业株式会社 Iii族氮化物复合衬底、半导体器件及它们的制造方法
CN103811593B (zh) 2012-11-12 2018-06-19 晶元光电股份有限公司 半导体光电元件的制作方法
US9646911B2 (en) * 2014-04-10 2017-05-09 Sensor Electronic Technology, Inc. Composite substrate
CN105895672A (zh) * 2015-01-26 2016-08-24 东莞市中镓半导体科技有限公司 一种降低氮化镓基电子器件外延应力的离子注入改善型衬底
JP6735588B2 (ja) * 2016-03-30 2020-08-05 株式会社サイオクス 窒化物半導体テンプレート、窒化物半導体積層物、窒化物半導体テンプレートの製造方法、および窒化物半導体積層物の製造方法
US10790296B1 (en) 2019-05-21 2020-09-29 Sandisk Technologies Llc Distortion-compensated wafer bonding method and apparatus using a temperature-controlled backside thermal expansion layer
KR20230017249A (ko) * 2020-05-29 2023-02-03 더 거번먼트 오브 더 유나이티드 스테이츠 오브 아메리카, 에즈 레프리젠티드 바이 더 세크러테리 오브 더 네이비 임의 기판으로의 대면적 iii족 질화물 반도체 물질 및 디바이스의 전사

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FR2789518B1 (fr) * 1999-02-10 2003-06-20 Commissariat Energie Atomique Structure multicouche a contraintes internes controlees et procede de realisation d'une telle structure
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JP3809464B2 (ja) * 1999-12-14 2006-08-16 独立行政法人理化学研究所 半導体層の形成方法
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Also Published As

Publication number Publication date
US7887936B2 (en) 2011-02-15
US20110094668A1 (en) 2011-04-28
ATE398833T1 (de) 2008-07-15
EP1702357A1 (fr) 2006-09-20
EP1702357B1 (fr) 2008-06-18
JP2007523472A (ja) 2007-08-16
US20060240644A1 (en) 2006-10-26
WO2005076345A1 (fr) 2005-08-18
CN1902747A (zh) 2007-01-24
DE602004014533D1 (de) 2008-07-31
KR100855793B1 (ko) 2008-09-01
CN100472749C (zh) 2009-03-25
KR20060113983A (ko) 2006-11-03
FR2864970A1 (fr) 2005-07-15
JP4745249B2 (ja) 2011-08-10

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Effective date: 20100930