JP6245107B2 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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- JP6245107B2 JP6245107B2 JP2014160719A JP2014160719A JP6245107B2 JP 6245107 B2 JP6245107 B2 JP 6245107B2 JP 2014160719 A JP2014160719 A JP 2014160719A JP 2014160719 A JP2014160719 A JP 2014160719A JP 6245107 B2 JP6245107 B2 JP 6245107B2
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- 239000004065 semiconductor Substances 0.000 title claims description 189
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000010410 layer Substances 0.000 claims description 139
- 239000000758 substrate Substances 0.000 claims description 83
- 239000004020 conductor Substances 0.000 claims description 69
- 239000011229 interlayer Substances 0.000 claims description 48
- 238000005530 etching Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 238000007747 plating Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 210000000746 body region Anatomy 0.000 description 16
- 239000012535 impurity Substances 0.000 description 9
- 238000011084 recovery Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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Description
次に、半導体装置10の製造方法を説明する。半導体装置10は、ドリフト領域28と略同じn型不純物濃度を有するn型の半導体基板(シリコン基板)から製造される。まず、エミッタ領域20、ボディ領域21、ドリフト領域28、アノード領域50、トレンチ40、絶縁膜42、トレンチ電極44を形成する。次に、図4に示すように、半導体基板上に層間絶縁膜47を形成する。
20:エミッタ領域
21:ボディ領域
28:ドリフト領域
30:バッファ領域
32:コレクタ領域
40:トレンチ
42:絶縁膜
44:トレンチ電極
47:層間絶縁膜
50:アノード領域
52:カソード領域
60:上部電極
62:下部電極
70:コンタクトホール
74:導電体層
90:IGBT領域
92:ダイオード領域
Claims (7)
- 半導体基板を有する半導体装置であって、
前記半導体基板の上面に形成された平行に伸びる複数のトレンチと、
前記各トレンチの内面を覆うトレンチ絶縁膜と、
前記各トレンチの内部に配置されており、前記トレンチ絶縁膜によって前記半導体基板から絶縁されているトレンチ電極と、
前記複数のトレンチのうちの隣り合うトレンチに挟まれた第1範囲内の前記半導体基板に形成されており、前記半導体基板の前記上面に露出しており、前記トレンチ絶縁膜に接している第1導電型の第1半導体層と、
前記第1範囲内の前記半導体基板に形成されており、一部が前記半導体基板の前記上面に露出しており、前記第1半導体層の下側で前記トレンチ絶縁膜に接している第2導電型の第2半導体層と、
前記半導体基板に形成されており、前記第2半導体層の下側に配置されており、前記第2半導体層によって前記第1半導体層から分離されており、前記第2半導体層の下側で前記トレンチ絶縁膜に接している第1導電型の第3半導体層と、
前記半導体基板の前記上面及び前記トレンチ電極上に配置されており、前記第1範囲内に配置された複数のコンタクトホールを有する層間絶縁膜と、
前記各コンタクトホール内に配置されており、前記第1半導体層と前記第2半導体層の少なくとも一方に接続されている第1導電体層と、
前記第1導電体層上及び前記層間絶縁膜上に配置されており、前記各第1導電体層に接続されている表面電極、
を有し、
前記各コンタクトホールが、前記各トレンチと平行な方向に沿って長く伸びており、
前記第1範囲に隣接する2つのトレンチのうちの一方から他方に向かう方向に、前記複数のコンタクトホールが間隔を開けて配列されている、
半導体装置。 - 前記第1範囲とは異なる前記複数のトレンチのうちの隣り合うトレンチに挟まれた範囲である第2範囲内の前記半導体基板に形成されており、前記半導体基板の前記上面に露出している第2導電型の第4半導体層と、
第2導電体層、
をさらに有しており、
前記第3半導体層の一部が、前記第4半導体層の下側に配置されており、前記第4半導体層に接しており、
前記層間絶縁膜が、前記第2範囲内に配置されたコンタクトホールを有しており、
前記第2導電体層が、前記第2範囲内の前記コンタクトホール内に配置されており、前記第4半導体層に接続されており、
前記表面電極の一部が、前記第2導電体層上に配置されており、前記第2導電体層に接続されており、
前記複数の第1導電体層の前記半導体基板に対するコンタクト面積を前記第1範囲の面積で除算した値が、前記第2導電体層の前記半導体基板に対するコンタクト面積を前記第2範囲の面積で除算した値よりも大きい、
請求項1の半導体装置。 - 前記第1導電体層のヤング率は、前記表面電極のヤング率よりも高い請求項1または2の半導体装置。
- 前記第1導電体層は、CVD、メッキ、スパッタによって形成可能な材料によって構成されている請求項1〜3のいずれか一項の半導体装置。
- 前記第1導電体層は、W、Al、Cuのいずれかを含む金属によって構成されている請求項1〜4のいずれか一項の半導体装置。
- 前記各トレンチ電極上の前記層間絶縁膜の幅が、前記第1範囲内の複数のコンタクトホールに挟まれた前記層間絶縁膜の幅よりも広い請求項1〜5のいずれか一項の半導体装置。
- 加工用ウエハから半導体装置を製造する方法であって、
前記加工用ウエハが、
平行に伸びる複数のトレンチが上面に形成された半導体基板と、
前記各トレンチの内面を覆うトレンチ絶縁膜と、
前記各トレンチの内部に配置されており、前記トレンチ絶縁膜によって前記半導体基板から絶縁されているトレンチ電極、
を有しており、
前記半導体基板が、
前記複数のトレンチのうちの隣り合うトレンチに挟まれた範囲内に形成されており、前記半導体基板の前記上面に露出しており、前記トレンチ絶縁膜に接している第1導電型の第1半導体層と、
前記範囲内に形成されており、一部が前記半導体基板の前記上面に露出しており、前記第1半導体層の下側で前記トレンチ絶縁膜に接している第2導電型の第2半導体層と、
前記第2半導体層の下側に配置されており、前記第2半導体層によって前記第1半導体層から分離されており、前記第2半導体層の下側で前記トレンチ絶縁膜に接している第1導電型の第3半導体層、
を有しており、
前記方法が、
前記加工用ウエハの上面に、層間絶縁膜を形成する工程と、
前記範囲内の前記層間絶縁膜に、複数のコンタクトホールを形成する工程と、
前記複数のコンタクトホール内及び前記層間絶縁膜上に、導電体層を成長させる工程と、
前記複数のコンタクトホール内に前記導電体層が残存するように前記層間絶縁膜上の前記導電体層をエッチングする工程と、
前記エッチングの後に、前記導電体層上及び前記層間絶縁膜上に、表面電極を形成する工程、
を有し、
前記各コンタクトホールが、前記各トレンチと平行な方向に沿って長く伸びるように形成され、
前記範囲に隣接する2つのトレンチのうちの一方から他方に向かう方向に、前記複数のコンタクトホールが間隔を開けて配列されるように前記各コンタクトホールが形成される、
製造方法。
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