JP2019106430A - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
- 210000000746 body region Anatomy 0.000 claims abstract description 142
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 239000012535 impurity Substances 0.000 claims abstract description 51
- 238000013459 approach Methods 0.000 claims description 5
- 238000011084 recovery Methods 0.000 description 19
- 239000011229 interlayer Substances 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Abstract
Description
12 :半導体基板
14 :上部電極
16 :下部電極
20 :IGBT領域
22 :エミッタ領域
23 :ボディコンタクト領域
24 :ボディ領域
24a :第1ボディ領域
24b :第2ボディ領域
26 :ドリフト領域
28 :バッファ領域
30 :コレクタ領域
32 :ゲート絶縁膜
34 :ゲート電極
36 :層間絶縁膜
38 :境界
40 :ダイオード領域
41 :アノードコンタクト領域
42 :アノード領域
48 :カソード領域
50 :トレンチ
52 :絶縁膜
54 :制御電極
56 :層間絶縁膜
Claims (4)
- 半導体装置であって、
半導体基板と、
前記半導体基板の上面に設けられたトレンチと、
前記トレンチ内に配置されたゲート絶縁膜と、
前記トレンチ内に配置されており、前記ゲート絶縁膜によって前記半導体基板から絶縁されているゲート電極と、
前記上面に接している上部電極と、
前記半導体基板の下面に接している下部電極、
を有しており、
前記半導体基板が、前記下部電極に接する範囲に、p型のコレクタ領域と、n型のカソード領域を備えており、
前記半導体基板をその厚み方向に沿って平面視したときに、前記コレクタ領域と重複する半導体領域がIGBT領域であり、前記カソード領域と重複する半導体領域がダイオード領域であり、
前記トレンチが、前記IGBT領域内に設けられており、
前記半導体基板が、
前記IGBT領域から前記ダイオード領域に跨って分布しており、前記コレクタ領域の上部及び前記カソード領域の上部に配置されており、前記ゲート絶縁膜に接しているドリフト領域と、
前記IGBT領域内の前記ドリフト領域の上部に配置されており、前記ゲート絶縁膜に接しているp型のボディ領域と、
前記ボディ領域の上部に配置されており、前記ボディ領域よりもp型不純物濃度が高く、前記上部電極に接しているp型のボディコンタクト領域と、
前記ボディ領域の上部に配置されており、前記上部電極に接しており、前記ゲート絶縁膜に接しており、前記ボディ領域によって前記ドリフト領域から分離されているn型のエミッタ領域と、
前記ダイオード領域内の前記ドリフト領域の上部に配置されているp型のアノード領域と、
前記アノード領域の上部に配置されており、前記アノード領域よりもp型不純物濃度が高く、前記上部電極に接しているp型のアノードコンタクト領域、
を有しており、
前記ボディ領域が、第1ボディ領域と、前記第1ボディ領域及び前記アノード領域よりもp型不純物濃度が低い第2ボディ領域を有しており、
前記第2ボディ領域が、前記アノード領域に隣接しており、
前記第1ボディ領域が、前記アノード領域と反対側で前記第2ボディ領域に隣接している、
半導体装置。 - 前記第2ボディ領域内のp型不純物濃度が、前記アノード領域に近づくにしたがって低下するように分布している請求項1の半導体装置。
- 前記第2ボディ領域内のp型不純物濃度が、前記アノード領域に近づくにしたがって連続的に低下するように分布している請求項2の半導体装置。
- 前記第2ボディ領域内のp型不純物濃度が、前記アノード領域に近づくにしたがってステップ状に低下するように分布している請求項2の半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017237121A JP7067041B2 (ja) | 2017-12-11 | 2017-12-11 | 半導体装置 |
CN201811474807.3A CN110034184B (zh) | 2017-12-11 | 2018-12-04 | 半导体装置 |
US16/213,123 US11404411B2 (en) | 2017-12-11 | 2018-12-07 | Semiconductor device having alternately arranged IGBT regions and diode regions |
DE102018131705.0A DE102018131705A1 (de) | 2017-12-11 | 2018-12-11 | Halbleitervorrichtung |
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JP2017237121A JP7067041B2 (ja) | 2017-12-11 | 2017-12-11 | 半導体装置 |
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JP2019106430A true JP2019106430A (ja) | 2019-06-27 |
JP7067041B2 JP7067041B2 (ja) | 2022-05-16 |
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JP (1) | JP7067041B2 (ja) |
CN (1) | CN110034184B (ja) |
DE (1) | DE102018131705A1 (ja) |
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JP2021158198A (ja) * | 2020-03-26 | 2021-10-07 | 三菱電機株式会社 | 半導体装置 |
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JP7279356B2 (ja) * | 2018-12-19 | 2023-05-23 | 富士電機株式会社 | 半導体装置 |
DE102019133030B4 (de) * | 2019-12-04 | 2023-05-04 | Infineon Technologies Austria Ag | Bipolartransistor mit isoliertem gate enthaltende halbleitervorrichtung und herstellungsverfahren |
CN113764511B (zh) * | 2021-07-30 | 2023-10-27 | 广州华浦电子科技有限公司 | 具有动态载流子通道的低损耗超结igbt器件及其制造方法 |
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JP5937413B2 (ja) | 2011-06-15 | 2016-06-22 | 株式会社デンソー | 半導体装置 |
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JP6078961B2 (ja) | 2012-03-19 | 2017-02-15 | 富士電機株式会社 | 半導体装置の製造方法 |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2014038937A (ja) * | 2012-08-16 | 2014-02-27 | Mitsubishi Electric Corp | 半導体装置 |
JP2014075582A (ja) * | 2012-09-12 | 2014-04-24 | Fuji Electric Co Ltd | 半導体装置および半導体装置の製造方法 |
JP2016032105A (ja) * | 2014-07-29 | 2016-03-07 | インフィネオン テクノロジーズ アーゲーInfineon Technologies Ag | 逆導通型igbt |
WO2016030966A1 (ja) * | 2014-08-26 | 2016-03-03 | 三菱電機株式会社 | 半導体素子 |
WO2016080269A1 (ja) * | 2014-11-17 | 2016-05-26 | 富士電機株式会社 | 半導体装置および半導体装置の製造方法 |
Cited By (2)
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JP2021158198A (ja) * | 2020-03-26 | 2021-10-07 | 三菱電機株式会社 | 半導体装置 |
JP7354897B2 (ja) | 2020-03-26 | 2023-10-03 | 三菱電機株式会社 | 半導体装置 |
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CN110034184A (zh) | 2019-07-19 |
JP7067041B2 (ja) | 2022-05-16 |
US11404411B2 (en) | 2022-08-02 |
US20190181136A1 (en) | 2019-06-13 |
CN110034184B (zh) | 2022-10-04 |
DE102018131705A1 (de) | 2019-06-13 |
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