JP6228462B2 - ハンドルウエハ内に高抵抗率領域を有するシリコン・オン・インシュレータ構造体およびそのような構造体の製法 - Google Patents

ハンドルウエハ内に高抵抗率領域を有するシリコン・オン・インシュレータ構造体およびそのような構造体の製法 Download PDF

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JP6228462B2
JP6228462B2 JP2013558114A JP2013558114A JP6228462B2 JP 6228462 B2 JP6228462 B2 JP 6228462B2 JP 2013558114 A JP2013558114 A JP 2013558114A JP 2013558114 A JP2013558114 A JP 2013558114A JP 6228462 B2 JP6228462 B2 JP 6228462B2
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wafer
handle
handle wafer
resistivity
layer
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JP2014512091A5 (https=
JP2014512091A (ja
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ジェフリー・エル・リバート
ル・フェイ
ロバート・ダブリュー・スタンドリー
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SunEdison Inc
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SunEdison Inc
MEMC Electronic Materials Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H10P36/07—Gettering within semiconductor bodies within silicon bodies of silicon-on-insulator structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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JP2013558114A 2011-03-16 2012-03-13 ハンドルウエハ内に高抵抗率領域を有するシリコン・オン・インシュレータ構造体およびそのような構造体の製法 Active JP6228462B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161453409P 2011-03-16 2011-03-16
US61/453,409 2011-03-16
US201161545891P 2011-10-11 2011-10-11
US61/545,891 2011-10-11
PCT/US2012/028920 WO2012125632A1 (en) 2011-03-16 2012-03-13 Silicon on insulator structures having high resistivity regions in the handle wafer and methods for producing such structures

Publications (3)

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JP2014512091A JP2014512091A (ja) 2014-05-19
JP2014512091A5 JP2014512091A5 (https=) 2017-05-18
JP6228462B2 true JP6228462B2 (ja) 2017-11-08

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US (2) US8846493B2 (https=)
EP (1) EP2686878B1 (https=)
JP (1) JP6228462B2 (https=)
KR (1) KR101870476B1 (https=)
CN (1) CN103430298B (https=)
TW (1) TWI550834B (https=)
WO (1) WO2012125632A1 (https=)

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Publication number Publication date
KR20140019350A (ko) 2014-02-14
CN103430298A (zh) 2013-12-04
US20120235283A1 (en) 2012-09-20
TW201241994A (en) 2012-10-16
EP2686878B1 (en) 2016-05-18
KR101870476B1 (ko) 2018-06-22
US20120238070A1 (en) 2012-09-20
EP2686878A1 (en) 2014-01-22
TWI550834B (zh) 2016-09-21
US8846493B2 (en) 2014-09-30
WO2012125632A1 (en) 2012-09-20
CN103430298B (zh) 2016-03-16
JP2014512091A (ja) 2014-05-19

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