JP6129671B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP6129671B2 JP6129671B2 JP2013150391A JP2013150391A JP6129671B2 JP 6129671 B2 JP6129671 B2 JP 6129671B2 JP 2013150391 A JP2013150391 A JP 2013150391A JP 2013150391 A JP2013150391 A JP 2013150391A JP 6129671 B2 JP6129671 B2 JP 6129671B2
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- semiconductor chip
- semiconductor device
- wiring board
- main surface
- wire
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- 239000004065 semiconductor Substances 0.000 title claims description 195
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000002184 metal Substances 0.000 claims description 73
- 229910052751 metal Inorganic materials 0.000 claims description 73
- 239000011347 resin Substances 0.000 claims description 38
- 229920005989 resin Polymers 0.000 claims description 38
- 238000007789 sealing Methods 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 12
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- 230000002093 peripheral effect Effects 0.000 description 11
- 238000002347 injection Methods 0.000 description 10
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- 239000000463 material Substances 0.000 description 9
- 238000000465 moulding Methods 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 4
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- 239000012466 permeate Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 230000001174 ascending effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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- 238000012360 testing method Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
図1は実施の形態の半導体装置の構造の一例を示す平面図、図2は図1に示す半導体装置の長手方向の構造を示す側面図、図3は図1に示す半導体装置の裏面側の構造を示す裏面図、図4は図1に示す半導体装置の幅方向の構造を示す側面図である。また、図5は図1に示す半導体装置の封止体を透過して内部構造を示す平面図、図6は図5に示すA−A線に沿って切断した構造を示す断面図、図7は図5に示すB−B線に沿って切断した構造を示す断面図である。さらに、図8は図1に示す半導体装置に搭載される半導体チップのパッドレイアウトの一例を示す平面図、図9は図1に示す半導体装置に搭載される半導体チップの内部の回路ブロックのレイアウトの一例を示す平面図である。
1a 上面(第1面、表面)
1aa 第1辺(長辺)
1ab 第2辺(短辺)
1ac 第3辺(長辺)
1ad 第4辺(短辺)
1b 下面(第2面、裏面)
1c,1ca,1cb,1cc,1cd,1ce,1cf ボンディングリード(端子、電極、リード、ボンディングステッチ)
1d ランド(端子、電極、ボンディングリード)
1e 配線部(配線パターン)
1f 開口部
1g スルーホール配線
1h チップ搭載領域
2 半導体チップ
2a 主面(表面)
2aa 第1辺(長辺)
2ab 第2辺(短辺)
2ac 第3辺(長辺)
2ad 第4辺(短辺)
2b 裏面
2c 電極パッド(電極、端子)
2ca 電極パッド(第1電極パッド、電極、端子)
2cb,2cc,2cd 電極パッド(電極、端子)
2e DRAM(メモリ回路)
2f,2g,2h,2i,2j 特定の機能を有する(マクロ化された)ロジック回路
2k 他の(マクロ化されていない)ロジック回路
3 半田ボール(外部接続用端子、外部電極端子)
4 金属ワイヤ(導電性ワイヤ、導電性部材)
4a 第1ワイヤ(金属ワイヤ)
4b 第2ワイヤ(金属ワイヤ)
4c 第3ワイヤ(金属ワイヤ)
4d 第4ワイヤ(金属ワイヤ)
4e 第5ワイヤ(金属ワイヤ)
4f 第6ワイヤ(金属ワイヤ)
5 BGA(Ball Grid Array 、半導体装置)
6 ダイボンド材(マウント材、接着材)
7 封止体(樹脂体、樹脂部)
7a インデックスマーク
8 多数個取り基板(配線基板)
8a デバイス領域(パッケージ領域、半導体装置領域)
9 封止用樹脂(樹脂)
10 ポット
11 ランナ
Claims (4)
- (a)第1面とその反対側の第2面とを有し、前記第1面に複数のリードが設けられ、かつ前記第1面が長方形に形成された配線基板を準備する工程、
(b)前記(a)工程の後、四角形の主面、前記主面に形成された複数の電極パッド、および前記主面とは反対側の裏面を有する半導体チップを、前記半導体チップの前記裏面が前記配線基板の前記第1面と対向するように、前記配線基板の前記第1面上に配置する工程、
(c)前記(b)工程の後、前記半導体チップの前記主面の4辺のうちの3辺のそれぞれに沿って形成された前記複数の電極パッドと、前記配線基板の前記第1面の前記複数のリードとを複数の金属ワイヤで電気的に接続する工程、
(d)前記(c)工程の後、前記半導体チップおよび前記複数の金属ワイヤを樹脂封止して前記配線基板の前記第1面上に封止体を形成する工程、
を有し、
前記(d)工程において、前記半導体チップの前記主面の4辺のうちの前記複数の金属ワイヤが配置されていない辺に対向する辺側から封止用樹脂を流し込んで前記封止体を形成する、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記半導体チップは、メモリ回路とロジック回路とを有する、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記配線基板の前記第1面の短辺に沿うように並んで配置された前記複数の金属ワイヤが、前記半導体チップの前記主面の対向する2辺のそれぞれに配置され、
前記対向する2辺のそれぞれの外側の位置に、前記第1面の短辺に沿って、かつ複数列に亘って前記複数のリードが設けられ、
前記複数のリードに前記複数の金属ワイヤが電気的に接続されている、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記半導体チップの前記主面の前記対向する2辺と交差する1辺に前記複数の金属ワイヤが配置され、
前記配線基板の前記第1面において、前記交差する1辺の外側の位置に前記複数のリードが1列に設けられ、
前記複数のリードに前記複数の金属ワイヤが電気的に接続されている、半導体装置の製造方法。
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JP2013150391A JP6129671B2 (ja) | 2013-07-19 | 2013-07-19 | 半導体装置の製造方法 |
US14/328,527 US9275940B2 (en) | 2013-07-19 | 2014-07-10 | Semiconductor device and manufacturing method thereof |
CN201410345262.1A CN104299947B (zh) | 2013-07-19 | 2014-07-18 | 制造半导体器件的方法 |
HK15102570.7A HK1202184A1 (en) | 2013-07-19 | 2015-03-13 | Semiconductor device and manufacturing method thereor |
US15/003,518 US20160148895A1 (en) | 2013-07-19 | 2016-01-21 | Semiconductor device and manufacturing method thereof |
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JP3048496B2 (ja) * | 1993-04-16 | 2000-06-05 | 株式会社東芝 | 半導体装置 |
JPH07122703A (ja) * | 1993-10-22 | 1995-05-12 | Kawasaki Steel Corp | 樹脂封止型半導体装置及びその製造方法 |
JP3421747B2 (ja) * | 1995-02-15 | 2003-06-30 | セイコーエプソン株式会社 | 圧電発振器及び電圧制御発振器 |
JPH09260418A (ja) * | 1996-03-27 | 1997-10-03 | Oki Micro Design Miyazaki:Kk | ワイヤーボンディングを考慮したtcp用半導体装置 |
US5955777A (en) * | 1997-07-02 | 1999-09-21 | Micron Technology, Inc. | Lead frame assemblies with voltage reference plane and IC packages including same |
JP2000100854A (ja) * | 1998-09-17 | 2000-04-07 | Toshiba Corp | 半導体装置 |
JP2000294684A (ja) * | 1999-04-09 | 2000-10-20 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP4820683B2 (ja) * | 2006-04-28 | 2011-11-24 | 川崎マイクロエレクトロニクス株式会社 | 半導体装置と半導体装置の絶縁破壊防止方法 |
JP4942020B2 (ja) * | 2006-05-12 | 2012-05-30 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4362784B2 (ja) * | 2006-07-06 | 2009-11-11 | エルピーダメモリ株式会社 | 半導体装置 |
WO2008146426A1 (ja) * | 2007-06-01 | 2008-12-04 | Panasonic Corporation | 半導体装置 |
JP5113509B2 (ja) * | 2007-12-25 | 2013-01-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5191915B2 (ja) * | 2009-01-30 | 2013-05-08 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US8547709B2 (en) * | 2010-02-12 | 2013-10-01 | Cyntec Co. Ltd. | Electronic system with a composite substrate |
JP5750937B2 (ja) * | 2011-02-25 | 2015-07-22 | 富士通株式会社 | 半導体装置及びその製造方法 |
WO2012117960A1 (ja) * | 2011-03-02 | 2012-09-07 | シャープ株式会社 | 半導体素子および表示パネル |
JP5848517B2 (ja) * | 2011-04-26 | 2016-01-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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CN104299947A (zh) | 2015-01-21 |
US20160148895A1 (en) | 2016-05-26 |
US9275940B2 (en) | 2016-03-01 |
US20150021749A1 (en) | 2015-01-22 |
JP2015023159A (ja) | 2015-02-02 |
HK1202184A1 (en) | 2015-09-18 |
CN104299947B (zh) | 2018-04-06 |
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