JP5750937B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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JP5750937B2
JP5750937B2 JP2011040674A JP2011040674A JP5750937B2 JP 5750937 B2 JP5750937 B2 JP 5750937B2 JP 2011040674 A JP2011040674 A JP 2011040674A JP 2011040674 A JP2011040674 A JP 2011040674A JP 5750937 B2 JP5750937 B2 JP 5750937B2
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semiconductor element
electrode
recess
compound semiconductor
periphery
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JP2011040674A
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JP2012178468A (ja
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谷 元昭
元昭 谷
岡本 圭史郎
圭史郎 岡本
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Fujitsu Ltd
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Fujitsu Ltd
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Priority to JP2011040674A priority Critical patent/JP5750937B2/ja
Priority to US13/358,840 priority patent/US8866312B2/en
Priority to TW101103353A priority patent/TWI496251B/zh
Priority to CN201210034475.3A priority patent/CN102651352B/zh
Publication of JP2012178468A publication Critical patent/JP2012178468A/ja
Priority to US14/453,922 priority patent/US9177938B2/en
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Description

本発明は、半導体装置及びその製造方法に関する。
窒化物半導体は、高い飽和電子速度及びワイドバンドギャップ等の特徴を利用し、高耐圧及び高出力の半導体デバイスへの適用が検討されている。例えば、窒化物半導体であるGaNのバンドギャップは3.4eVであり、Siのバンドギャップ(1.1eV)及びGaAsのバンドギャップ(1.4eV)よりも大きく、高い破壊電界強度を有する。そのためGaNは、高電圧動作且つ高出力を得る電源用のパワーデバイスの材料として極めて有望である。
特開昭62−71301号公報 特開平5−121589号公報 特許第3127895号公報
上記のパワーデバイスは、大電流が流れるために低抵抗伝送を考慮する必要がある。その一方で、パワーデバイスは放熱量が極めて大きいため、高放熱性を十分に考慮する必要がある。
低抵抗伝送を実現するパッケージ技術として、例えば平坦な回路基板に半導体素子をフェイスアップで配置し、低コストであるワイヤボンディング法で実装する場合には、ワイヤを短くする、或いはワイヤを太くすることが有効である。
しかしながら、半導体素子の低抵抗伝送及び半導体素子の高放熱性の双方について、特に複雑な構成とすることなく、実効的な効果を確実に得ることのできるパッケージ技術は、現在のところ確立されていない。
本発明は、上記の課題に鑑みてなされたものであり、比較的簡易な構成で、半導体素子の低抵抗伝送を達成すると共に、半導体素子の十分な高放熱性を低コストで確実に実現する半導体装置及びその製造方法を提供することを目的とする。
半導体装置の一態様は、表面に第1の電極が形成された半導体素子と、表面に第2の電極及び凹部が形成された基板と、前記凹部内で前記半導体素子を固定する放熱性接着材料とを含み、前記半導体素子は、前記凹部内において、前記第1の電極と前記第2の電極とが近接するように偏倚した位置に固定されており、前記第1の電極と前記第2の電極とが接続されており、前記凹部内において、前記半導体素子の周縁のうちで前記第1の電極が位置する部位と、前記基板の前記凹部の周縁のうちで前記第2の電極が位置する部位とが第1の距離で対向しており、前記半導体素子の周縁のうちで前記第1の電極が非形成の部位と、前記基板の前記凹部の周縁のうちで前記第2の電極が非形成の部位とが前記第1の距離よりも大きい第2の距離で対向しており、前記放熱性接着材料は、前記半導体素子の底面から前記半導体素子の前記第2の距離の部位における側面の少なくとも一部を被覆する
半導体装置の製造方法の一態様は、表面に第1の電極が形成された半導体素子と、表面に第2の電極及び凹部が形成された基板とを備えた半導体装置の製造方法であって、前記基板の表面に凹部を形成する工程と、前記半導体素子を、前記凹部内において、前記第1の電極と前記第2の電極とが近接するように偏倚した位置に配置し、放熱性接着材料を前記半導体素子の底面から側面の少なくとも一部まで被覆させて前記半導体素子を固定する工程と、前記第1の電極と前記第2の電極とを接続する工程とを含み、前記凹部内に前記半導体素子を固定する際に、前記凹部内において、前記半導体素子の周縁のうちで前記第1の電極が位置する部位と、前記基板の前記凹部の周縁のうちで前記第2の電極が位置する部位とを第1の距離で対向させ、前記半導体素子の周縁のうちで前記第1の電極が非形成の部位と、前記基板の前記凹部の周縁のうちで前記第2の電極が非形成の部位とを前記第1の距離よりも大きい第2の距離で対向させ、前記放熱性接着材料を、前記半導体素子の前記第2の距離の部位における側面の少なくとも一部まで被覆させる
上記の各態様によれば、比較的簡易な構成で、半導体素子の低抵抗伝送を達成すると共に、半導体素子の十分な高放熱性を低コストで確実に実現する半導体装置を得ることができる。
第1の実施形態による半導体パッケージの製造工程を示すフロー図である。 第1の実施形態で作製するAlGaN/GaN・HEMTの製造方法を工程順に示す概略断面図である。 図2に引き続き、第1の実施形態で作製するAlGaN/GaN・HEMTの製造方法を工程順に示す概略断面図である。 第1の実施形態で作製された化合物半導体素子の概略構成を示す平面図である。 第1の実施形態で作製する半導体パッケージについて、製造工程順に示す概略断面図である。 図5に引き続き、第1の実施形態で作製する半導体パッケージについて、製造工程順に示す概略断面図である。 図6に引き続き、第1の実施形態で作製する半導体パッケージについて、製造工程順に示す概略断面図である。 図7に引き続き、第1の実施形態で作製する半導体パッケージについて、製造工程順に示す概略断面図である。 図8に引き続き、第1の実施形態で作製する半導体パッケージについて、製造工程順に示す概略断面図である。 第1の実施形態で作製する半導体パッケージについて、製造工程順に示す概略平面図である。 図10に引き続き、第1の実施形態で作製する半導体パッケージについて、製造工程順に示す概略平面図である。 図11に引き続き、第1の実施形態で作製する半導体パッケージについて、製造工程順に示す概略平面図である。 図12に引き続き、第1の実施形態で作製する半導体パッケージについて、製造工程順に示す概略平面図である。 図13に引き続き、第1の実施形態で作製する半導体パッケージについて、製造工程順に示す概略平面図である。 第1の実施形態の変形例1による半導体パッケージの概略構成を示す平面図である。 第1の実施形態の変形例2による半導体パッケージの概略構成を示す平面図である。 第2の実施形態による半導体パッケージの製造工程を示すフロー図である。 第2の実施形態による半導体パッケージの作製において、チップダイシングの工程を示す概略断面図である。 第2の実施形態で作製する半導体パッケージについて、製造工程順に示す概略断面図である。 図19に引き続き、第2の実施形態で作製する半導体パッケージについて、製造工程順に示す概略断面図である。 第2の実施形態で作製する半導体パッケージについて、製造工程順に示す概略平面図である。 図21に引き続き、第2の実施形態で作製する半導体パッケージについて、製造工程順に示す概略平面図である。 第3の実施形態による電源装置の概略構成を示す結線図である。 第4の実施形態による高周波増幅器の概略構成を示す結線図である。
以下、諸実施形態について図面を参照して詳細に説明する。以下の諸実施形態では、半導体素子を備えた半導体パッケージの構成について、その製造方法と共に説明する。
なお、以下の図面において、図示の便宜上、相対的に正確な大きさ及び厚みに示していない構成部材がある。
(第1の実施形態)
図1は、第1の実施形態による半導体パッケージの製造工程を示すフロー図である。
図2〜図3は、第1の実施形態で作製するAlGaN/GaN・HEMTの製造方法を工程順に示す概略断面図である。
図5〜図9は、第1の実施形態で作製する半導体パッケージについて、製造工程順に示す概略断面図である。
図10〜図14は、第1の実施形態で作製する半導体パッケージについて、製造工程順に示す概略平面図である。
本実施形態では、ステップS1〜S2で化合物半導体素子を作製した後、ステップS3〜ステップS7を経て半導体パッケージを作製する。以下、各ステップについて詳述する。
ステップS1:
ステップS1では、樹脂回路基板に搭載される半導体素子、ここではいわゆるHEMT(High Electron Mobility Transistor)構造の化合物半導体素子を作製する。具体的には、窒化物半導体であるAlGaN/GaN・HEMTを例示する。なお、本実施形態に適用可能な半導体素子は、AlGaN/GaN・HEMT以外にも、InAlN/GaN・HEMT、InAlGaN/GaN・HEMT等がある。更に、HEMT以外の窒化物半導体素子、窒化物半導体以外の化合物半導体素子、更には半導体メモリその他のあらゆる半導体素子に適用可能である。
先ず、図2(a)に示すように、成長用基板として例えばSi基板1上に、化合物半導体積層構造2を形成する。成長用基板としては、Si基板の代わりに、SiC基板、サファイア基板、GaAs基板、GaN基板等を用いても良い。また、基板の導電性としては、半絶縁性、導電性を問わない。
化合物半導体積層構造2は、バッファ層2a、電子走行層2b、中間層2c、電子供給層2d、及びキャップ層2eを有して構成される。
完成したAlGaN/GaN・HEMTでは、その動作時において、電子走行層2bの電子供給層2d(正確には中間層2c)との界面近傍に2次元電子ガス(2DEG)が発生する。この2DEGは、電子走行層2bの化合物半導体(ここではGaN)と電子供給層2dの化合物半導体(ここではAlGaN)との格子定数の相違に基づいて生成される。
詳細には、Si基板1上に、例えば有機金属気相成長(MOVPE:Metal Organic Vapor Phase Epitaxy)法により、以下の各化合物半導体を成長する。MOVPE法の代わりに、分子線エピタキシー(MBE:Molecular Beam Epitaxy)法等を用いても良い。
Si基板1上に、AlNを0.1μm程度の厚みに、i(インテンショナリ・アンドープ)−GaNを3μm程度の厚みに、i−AlGaNを5nm程度の厚みに、n−AlGaNを30nm程度の厚みに、n−GaNを10nm程度の厚みに順次成長する。これにより、バッファ層2a、電子走行層2b、中間層2c、電子供給層2d、及びキャップ層2eが形成される。
AlN、GaN、AlGaN、及びGaNの成長条件としては、原料ガスとしてトリメチルアルミニウムガス、トリメチルガリウムガス、及びアンモニアガスの混合ガスを用いる。成長する化合物半導体層に応じて、Al源であるトリメチルアルミニウムガス、Ga源であるトリメチルガリウムガスの供給の有無及び流量を適宜設定する。共通原料であるアンモニアガスの流量は、100ccm〜10LM程度とする。また、成長圧力は50Torr〜300Torr程度、成長温度は1000℃〜1200℃程度とする。
GaN、AlGaNをn型として成長する際には、n型不純物として例えばSiを含む例えばSiH4ガスを所定の流量で原料ガスに添加し、GaN及びAlGaNにSiをドーピングする。Siのドーピング濃度は、1×1018/cm3程度〜1×1020/cm3程度、例えば5×1018/cm3程度とする。
続いて、図2(b)に示すように、素子分離構造3を形成する。図2(a)以降では、素子分離構造3の図示を省略する。
詳細には、化合物半導体積層構造2の素子分離領域に、例えばアルゴン(Ar)を注入する。これにより、化合物半導体積層構造2及びSi基板1の表層部分に素子分離構造3が形成される。素子分離構造3により、化合物半導体積層構造2上で活性領域が画定される。
なお、素子分離は、上記の注入法の代わりに、例えばSTI(Shallow Trench Isolation)法を用いて行っても良い。このとき、化合物半導体積層構造2のドライエッチングには、例えば塩素系のエッチングガスを用いる。
続いて、図2(c)に示すように、ソース電極4及びドレイン電極5を形成する。
詳細には、先ず、化合物半導体積層構造2の表面におけるソース電極及びドレイン電極の形成予定位置(電極形成予定位置)に電極用リセス2A,2Bを形成する。
化合物半導体積層構造2の表面にレジストを塗布する。レジストをリソグラフィーにより加工し、レジストに、電極形成予定位置に相当する化合物半導体積層構造2の表面を露出する開口を形成する。以上により、当該開口を有するレジストマスクが形成される。
このレジストマスクを用いて、電子供給層2dの表面が露出するまで、キャップ層2eの電極形成予定位置をドライエッチングして除去する。これにより、電子供給層2dの表面の電極形成予定位置を露出する電極用リセス2A,2Bが形成される。エッチング条件としては、Ar等の不活性ガス及びCl2等の塩素系ガスをエッチングガスとして用い、例えばCl2を流量30sccm、圧力を2Pa、RF投入電力を20Wとする。なお、電極用リセス2A,2Bは、キャップ層2eの途中までエッチングして形成しても、また電子供給層2d以降までエッチングして形成しても良い。
レジストマスクは、灰化処理等により除去される。
ソース電極及びドレイン電極を形成するためのレジストマスクを形成する。ここでは、蒸着法及びリフトオフ法に適した例えば庇構造2層レジストを用いる。このレジストを化合物半導体積層構造2上に塗布し、電極用リセス2A,2Bを露出させる開口を形成する。以上により、当該開口を有するレジストマスクが形成される。
このレジストマスクを用いて、電極材料として、例えばTa/Alを、例えば蒸着法により、電極用リセス2A,2Bを露出させる開口内を含むレジストマスク上に堆積する。Taの厚みは20nm程度、Alの厚みは200nm程度とする。リフトオフ法により、レジストマスク及びその上に堆積したTa/Alを除去する。その後、Si基板1を、例えば窒素雰囲気中において400℃〜1000℃程度の温度、例えば600℃程度で熱処理し、残存したTa/Alを電子供給層2dとオーミックコンタクトさせる。Ta/Alの電子供給層2dとのオーミックコンタクトが得られるのであれば、熱処理が不要な場合もある。以上により、電極用リセス2A,2Bを電極材料の一部で埋め込むソース電極4及びドレイン電極5が形成される。
続いて、図3(a)に示すように、化合物半導体積層構造2にゲート電極の電極用リセス2Cを形成する。
詳細には、先ず、化合物半導体積層構造2の表面にレジストを塗布する。レジストをリソグラフィーにより加工し、レジストに、ゲート電極の形成予定位置(電極形成予定位置)に相当する化合物半導体積層構造2の表面を露出する開口を形成する。以上により、当該開口を有するレジストマスクが形成される。
このレジストマスクを用いて、電極形成予定位置における、キャップ層2e及び電子供給層2dの一部をドライエッチングして除去する。これにより、キャップ層2e及び電子供給層2dの一部まで掘り込まれた電極用リセス2Cが形成される。エッチング条件としては、Ar等の不活性ガス及びCl2等の塩素系ガスをエッチングガスとして用い、例えばCl2を流量30sccm、圧力を2Pa、RF投入電力を20Wとする。なお、電極用リセス2Cは、キャップ層2eの途中までエッチングして形成しても、また電子供給層2dのより深い箇所までエッチングして形成しても良い。
レジストマスクは、灰化処理等により除去される。
続いて、図3(b)に示すように、ゲート絶縁膜6を形成する。
詳細には、電極用リセス2Cの内壁面を覆うように、化合物半導体積層構造2上に絶縁材料として例えばAl23を堆積する。Al23は、例えば原子層堆積法(Atomic Layer Deposition:ALD法)により膜厚2nm〜200nm程度、ここでは10nm程度に堆積する。これにより、ゲート絶縁膜6が形成される。
なお、Al23の堆積は、ALD法の代わりに、例えばプラズマCVD法又はスパッタ法等で行うようにしても良い。また、Al23を堆積する代わりに、Alの窒化物又は酸窒化物を用いても良い。それ以外にも、Si,Hf,Zr,Ti,Ta,Wの酸化物、窒化物又は酸窒化物、或いはこれらから適宜に選択して多層に堆積して、ゲート絶縁膜を形成しても良い。
続いて、図3(c)に示すように、ゲート電極7を形成する。
詳細には、先ず、ゲート電極及びフィールドプレート電極を形成するためのレジストマスクを形成する。ここでは、蒸着法及びリフトオフ法に適した例えば庇構造2層レジストを用いる。このレジストをゲート絶縁膜6上に塗布し、ゲート絶縁膜6の電極用リセス2Cの部分を露出させる各開口を形成する。以上により、当該各開口を有するレジストマスクが形成される。
このレジストマスクを用いて、電極材料として、例えばNi/Auを、例えば蒸着法により、ゲート絶縁膜6の電極用リセス2Cの部分を露出させる開口内を含むレジストマスク上に堆積する。Niの厚みは30nm程度、Auの厚みは400nm程度とする。リフトオフ法により、レジストマスク及びその上に堆積したNi/Auを除去する。以上により、電極用リセス2C内をゲート絶縁膜6を介して電極材料の一部で埋め込むゲート電極7が形成される。
しかる後、層間絶縁膜の形成、ソース電極4、ドレイン電極5、ゲート電極7と接続される配線の形成、上層の保護膜の形成、最表面に露出する接続電極の形成等の諸工程を経て、本実施形態によるAlGaN/GaN・HEMTが形成される。
本実施形態では、ゲート絶縁膜6を有するMIS型のAlGaN/GaN・HEMTを例示したが、ゲート絶縁膜6を有さずゲート電極7が化合物半導体積層構造2と直接的に接触する、ショットキー型のAlGaN/GaN・HEMTを作製するようにしても良い。
また、電極用リセス2C内にゲート電極7を形成するゲートリセス構造を採用することなく、リセスのない化合物半導体積層構造2上に、ゲート絶縁膜を介して、或いは直接的に、ゲート電極を形成しても良い。
ステップS2:
ステップS2では、ステップS1でAlGaN/GaN・HEMTが作製されたSi基板から、各化合物半導体素子(化合物半導体チップ)を切り出す。
Si基板に設けられたダイシングラインに沿って、例えば所定のブレードを用いてダイシング、又は、レーザを用いてダイシング(レーザダイシング)して、各化合物半導体素子を切り出す(個片化する)。
作製された化合物半導体素子10を図4に示す。この化合物半導体素子10では、その表面に外部接続用の接続電極11が、矩形状の周縁における4辺のうち、ここでは3辺に沿って並列形成されている。各接続電極11は、下層で配線等を介してソース電極、ドレイン電極、ゲート電極等と接続されている。
ステップS3:
ステップS3では、図5及び図10に示すように、樹脂回路基板20の表面に凹部(ざぐり、キャビティ)21を形成する。
樹脂回路基板20は、樹脂22内、表面及び裏面に各種の銅(Cu)配線23が形成されており、各Cu配線23間はビア24により適宜接続されている。樹脂22内には、放熱用金属、ここではCuからなる金属コア25が設けられている。金属コア25は、Cu以外にも、金(Au)、ニッケル(Ni)、アルミニウム(Al)、チタン(Ti)、パラジウム(Pd)から選ばれた少なくとも1種類を含む金属を用いたものとしても良い。樹脂22の表面及び裏面はソルダーレジスト26,27で覆われている。樹脂22の表面に形成されたソルダーレジスト26には、樹脂22の表面の一部を露出する開口26a,26bが形成されている。開口26a内の所定位置には、化合物半導体素子10の接続電極11と接続される接続電極28aが、開口26b内には外部との接続電極28bが形成されている。樹脂22の裏面に形成されたソルダーレジスト27には、樹脂22の裏面の一部を露出する開口27a,27bが形成されており、開口27a,27b内には外部との接続電極29a,29bが形成されている。
なお、図10〜図14では、樹脂回路基板20の表面の接続電極28bの図示は省略する。
ここで、図5(a)ではスルーホールを有する樹脂回路基板20を、図5(b)ではスルーホールを有しない樹脂回路基板20を例示する。
図5(a)の樹脂回路基板20では、樹脂22を貫通するスルーホールが形成されている。ここではスルーホール31a,31bを例示する。スルーホール31a,31bの内壁面にはCuが形成されている。スルーホール31aを介して、樹脂22の表面の接続電極28aと裏面の接続電極29aとが接続される。スルーホール31bを介して、樹脂22の表面の接続電極28b、金属コア25、裏面の接続電極29bが接続される。
図5(b)の樹脂回路基板20では、樹脂22の表面の接続電極28b、金属コア25、裏面の接続電極29bがCu配線23及びビア24を介して接続される。
レーザ加工又はルータ加工により、樹脂22及びソルダーレジスト26の表面の所定部位に、金属コア25の表面の一部を露出する凹部21を形成する。凹部21は、化合物半導体素子10よりもサイズが大きい横長の矩形状に形成され、その周縁における4辺のうちの3辺が、並列する接続電極28aに沿っている。
樹脂22の加工で飛散した樹脂を洗浄して洗い流した後、表面に露出している接続電極28a,29a及び凹部21の底面に露出する金属コア25の表面を、例えばNiメッキ、続けてAuメッキ処理する。ここで、凹部21の底面に露出する金属コア25は、樹脂回路基板の表面で面積占有率が高いほど放熱性に優れるが、必要に応じて適宜にパターニングされていても良い。
以下の図6〜図14では、スルーホールを有する樹脂回路基板20について例示する。
ステップS4:
ステップS4では、図6及び図11に示すように、凹部21内にダミー素子30を配置し、この状態で凹部21内に放熱性に優れた接着材料(放熱性接着材料)、ここでは金属材料32を供給する。
詳細には、凹部21内における化合物半導体素子10の固定予定位置に、化合物半導体素子10と同型で同一サイズのダミー素子30を配置する。ダミー素子30は、例えばシリコン、ガラス、又はセラミックスを材料とするものである。固定予定位置は、凹部21の底面上で偏倚した位置であって、具体的には以下のようにする。ダミー素子30の3辺(化合物半導体素子10の接続電極11が形成された3辺に対応する)を、凹部21の周縁から0.01mm〜0.1mm程度、例えば0.05mm程度離れた箇所とする。ダミー素子30の他の1辺(化合物半導体素子10の接続電極11が形成されていない1辺に対応する)を、凹部21の周縁から4mm程度以上、例えば10.05mm程度離れた箇所とする。
化合物半導体素子10の固定予定位置にダミー素子30を配置した状態で、凹部21内に金属材料32、ここでは銀(Ag)の焼結用ペーストを、ダミー素子30の側面の少なくとも一部を被覆する厚みに供給する。この厚み(焼結用ペーストの厚み)は、ダミー素子30の側面高さの半分(中央位置)以上、換言すれば、化合物半導体素子10の厚みの半分(中央位置)以上とすることが好ましい。
金属材料32としては、Agの焼結用ペースト以外にも、例えばAu及びCuの焼結用ペーストから選ばれた少なくとも1種類を用いても良い。
また、放熱性接着材料としては、金属材料以外にも、絶縁性の材料である例えばBN、AlN等をペースト状にしたものを用いることができる。導電性の材料であるダイヤモンド(C)も、これを含有するペースト状のものを用いることが可能である。
ステップS5:
ステップS5では、図7及び図12に示すように、ダミー素子30を除去する。
ダミー素子30を除去すると、凹部21内において、化合物半導体素子10の固定予定位置を除く部位の全面に、上記の厚みの金属材料32が残存する。ここで、凹部21内に属材料32で画定された固定予定位置を32aとする。
ステップS6:
ステップS6では、図8及び図13に示すように、裏面に金属材料33が配された化合物半導体素子10を樹脂回路基板20の凹部21内に固着する。
詳細には、先ず、半導体素子10の裏面に所定の厚み(金属材料32よりも薄い)に金属材料33を塗布する。金属材料33には、金属材料32と同じAgの焼結用ペーストを用いるが、異なる金属として例えばAu及びCuの焼結用ぺーストから選ばれた少なくとも1種類を用いても良い。
裏面に金属材料33が配された化合物半導体素子10を、凹部21内の固定予定位置32aにフェイスアップで仮固定する。この仮固定は、例えば2kgf程度の加重で行う。その後、150℃〜250℃程度、例えば大気圧下で200℃程度として1時間程度、金属材料32,33を本硬化する。以上により、化合物半導体素子10が凹部21内の固定予定位置32aに固着される。
本実施形態では、化合物半導体素子10の裏面に金属材料33を塗布したが、凹部21内の固定予定位置32aにおける金属コア25の表面に、同様の厚みの金属材料を配し、化合物半導体素子10を当該金属材料上に配置するようにしても良い。この場合も、上記の同様の条件で仮固定及び本硬化を行う。
本実施形態では、ダミー素子30を用いて金属材料32,33を形成することにより、金属材料32を化合物半導体素子10の側面を覆う所期の厚みに正確に形成することができる。図示の例では、化合物半導体素子10の接続電極11の形成された辺と凹部21の周縁との間でも、化合物半導体素子10の側面が金属材料32で覆われる様子を示すが、この構成に限定されるものではない。例えば、次の工程における金属ワイヤを可及的に短くすべく、化合物半導体素子10の接続電極11の形成された辺と凹部21の周縁とを殆ど接触させることも考えられる。この場合には、その微小な隙間には金属材料32は殆ど存しないと考えられる。金属材料32の放熱効果は、その広さ(表面積)に比例するため、この狭い部位に金属材料32が無くとも、特に問題はない。
なお、ダミー素子30を用いることなく、化合物半導体素子10を金属材料で固着することも考えられる。
ステップS7:
ステップS7では、図9及び図14に示すように、化合物半導体素子10の接続電極11と樹脂回路基板20の接続電極28aとをワイヤボンディングして接続する。
詳細には、化合物半導体素子10の3辺と樹脂回路基板20の3辺とにおいて、互いに対向する接続電極11と接続電極28aとを金属ワイヤ34で接続する。金属ワイヤ34としては、例えば直径100μm〜2500μm程度、例えば100μm程度で、長さが例えば0.1mm程度のAlワイヤを用いる。金属ワイヤ34としては、Al以外に、Au,Cu,Pdから選択された1種類を用いても良い。
以上により、本実施形態による半導体パッケージが作製される。
本実施形態では、樹脂回路基板20に形成された凹部21内に、化合物半導体素子10が金属材料32,33で固定配置される。化合物半導体素子10は、凹部21の底面上において、偏倚した位置に配置される。具体的に、化合物半導体素子10は、その周縁のうちで接続電極11が設けられた3辺については凹部21の周縁との距離が小さく、接続電極11が設けられていない1辺については凹部21の周縁との距離が大きい位置に配置される。そして、後者の位置に相当する化合物半導体素子10の周縁と凹部21の周縁との間の広い領域では、金属材料32が化合物半導体素子10の側面を所定位置まで覆う厚みに形成されている。この構成では、金属材料32,33を通じて、化合物半導体素子10の底面のみならず側面(金属材料32が覆う部分)からも効率良く放熱することができ、しかも金属材料32の占有面積が広いことから更に放熱が助長される。その一方で、前者の位置に相当する化合物半導体素子10の周縁と凹部21の周縁との間の狭い領域で、互いに対向する接続電極11と接続電極28aとが金属ワイヤ34で接続される。この構成では、金属ワイヤ34を可及的に短く形成することができるため、低抵抗伝送が可能となる。
以上説明したように、本実施形態によれば、比較的簡易な構成で、化合物半導体素子10の低抵抗伝送を達成すると共に、化合物半導体素子10の十分な高放熱性を低コストで確実に実現する半導体パッケージを得ることができる。
−変形例−
以下、第1の実施形態の諸変形例について説明する。これらの変形例では、第1の実施形態と同様に、化合物半導体素子を備えた半導体パッケージを開示し、同様の製造方法により作製するが、化合物半導体素子の配置・接続状態が異なる点で相違する。なお、第1の実施形態による半導体パッケージと同様の構成部材等については同一の符号を用い、当該構成部材についての詳しい説明は省略する。
(変形例1)
図15は、第1の実施形態の変形例1による半導体パッケージの概略構成を示す平面図であり、第1の実施形態の図14に対応している。
本例では、第1の実施形態の図1のステップS1〜S7と同様に、半導体パッケージを作製する。図15に示すように、化合物半導体素子40では、その表面に外部接続用の接続電極11が、矩形状の周縁における4辺のうち、ここでは対向する2辺に沿って並列形成されている。
樹脂回路基板20に形成される凹部41は、金属コアの表面の一部を露出し、化合物半導体素子40よりもサイズが大きい横長の矩形状に形成され、その周縁のうちの対向する2辺が、並列する接続電極28aに沿っている。
化合物半導体素子40は、凹部41内に、その側面が金属材料32で、裏面が金属材料33で固定配置される。化合物半導体素子40は、その接続電極11が形成された対向する2辺が、凹部41の周縁から0.01mm〜0.1mm程度、例えば0.05mm程度離れた箇所に位置する。接続電極11が形成されていない対向する2辺が、凹部21の周縁から4mm程度以上、例えば6.5mm程度離れた箇所に位置する。
本例では、樹脂回路基板20に形成された凹部41内に、化合物半導体素子40が金属材料32,33で固定配置される。化合物半導体素子40は、凹部41の底面上において、偏倚した位置に配置される。具体的に、化合物半導体素子40は、その周縁のうちで接続電極11が設けられた対向する2辺については凹部41の周縁との距離が小さく、接続電極11が設けられていない対向する2辺については凹部41の周縁との距離が大きい位置に配置される。そして、後者の位置に相当する化合物半導体素子40の周縁と凹部41の周縁との間の広い領域では、金属材料32が化合物半導体素子40の側面を所定位置まで覆う厚みに形成されている。この構成では、金属材料32,33を通じて、化合物半導体素子40の底面のみならず側面(金属材料32が覆う部分)からも効率良く放熱することができ、しかも金属材料32の占有面積が広いことから更に放熱が助長される。その一方で、前者の位置に相当する化合物半導体素子40の周縁と凹部41の周縁との間の狭い領域で、互いに対向する接続電極11と接続電極28aとが金属ワイヤ34で接続される。この構成では、金属ワイヤ34を可及的に短く形成することができるため、低抵抗伝送が可能となる。
以上説明したように、本例によれば、比較的簡易な構成で、化合物半導体素子40の低抵抗伝送を達成すると共に、化合物半導体素子40の十分な高放熱性を低コストで確実に実現する半導体パッケージを得ることができる。
(変形例2)
図16は、第1の実施形態の変形例2による半導体パッケージの概略構成を示す平面図であり、第1の実施形態の図14に対応している。
本例では、第1の実施形態の図1のステップS1〜S7と同様に、半導体パッケージを作製する。図16に示すように、化合物半導体素子50では、その表面に外部接続用の接続電極11が、矩形状の周縁における4辺のうち、ここでは1辺に沿って並列形成されている。
樹脂回路基板20に形成される凹部51は、金属コアの表面の一部を露出し、化合物半導体素子50よりもサイズが大きい横長の矩形状に形成され、その周縁のうちの1辺が、並列する接続電極28aに沿っている。
化合物半導体素子50は、凹部51内に、その側面が金属材料32で、裏面が金属材料33で固定配置される。化合物半導体素子50は、その接続電極11が形成された1辺が、凹部51の周縁から0.01mm〜0.1mm程度、例えば0.05mm程度離れた箇所に位置する。接続電極11が形成されていない3辺が、凹部51の周縁から4mm程度以上、例えば10.05mm程度離れた箇所に位置する。
本例では、樹脂回路基板50に形成された凹部51内に、化合物半導体素子50が金属材料32,33で固定配置される。化合物半導体素子50は、凹部51の底面上において、偏倚した位置に配置される。具体的に、化合物半導体素子50は、その周縁のうちで接続電極11が設けられた1辺については凹部51の周縁との距離が小さく、接続電極11が設けられていない3辺については凹部51の周縁との距離が大きい位置に配置される。そして、後者の位置に相当する化合物半導体素子50の周縁と凹部51の周縁との間の広い領域では、金属材料32が化合物半導体素子50の側面を所定位置まで覆う厚みに形成されている。この構成では、金属材料32,33を通じて、化合物半導体素子50の底面のみならず側面(金属材料32が覆う部分)からも効率良く放熱することができ、しかも金属材料32の占有面積が広いことから更に放熱が助長される。その一方で、前者の位置に相当する化合物半導体素子50の周縁と凹部51の周縁との間の狭い領域で、互いに対向する接続電極11と接続電極28aとが金属ワイヤ34で接続される。この構成では、金属ワイヤ34を可及的に短く形成することができるため、低抵抗伝送が可能となる。
以上説明したように、本例によれば、比較的簡易な構成で、化合物半導体素子50の低抵抗伝送を達成すると共に、化合物半導体素子50の十分な高放熱性を低コストで確実に実現する半導体パッケージを得ることができる。
(第2の実施形態)
続いて、第2の実施形態について説明する。本実施形態では、第1の実施形態と同様に、化合物半導体素子を備えた半導体パッケージを開示し、同様の製造方法により作製するが、化合物半導体素子の側面を固定する金属材料が異なる点で相違する。なお、第1の実施形態による半導体パッケージと同様の構成部材等については同一の符号を用い、当該構成部材についての詳しい説明は省略する。
図17は、第2の実施形態による半導体パッケージの製造工程を示すフロー図である。
図19〜図20は、第2の実施形態で作製する半導体パッケージについて、製造工程順に示す概略断面図である。
図21〜図22は、第2の実施形態で作製する半導体パッケージについて、製造工程順に示す概略平面図である。
本実施形態では、ステップS11において、第1の実施形態のステップS1と同様に、AlGaN/GaN・HEMTを作製する。
ステップS12:
ステップS12では、図18(a)に示すように、ステップS11でAlGaN/GaN・HEMTが作製されたSi基板1について、途中までダイシングする。
詳細には、Si基板1に設けられたダイシングラインDLに沿って、例えば所定のブレードを用いてダイシング、又は、レーザを用いてSi基板1の裏面1b(表面を1aとする)からダイシング(レーザダイシング)する。本実施形態では、レーザダイシングを途中で停止させる。具体的には、ダイシングにより露出する溝1Aの深さが、化合物半導体素子の側面について、後述する溶融金属材料で化合物半導体素子の側面を覆いたいと考える高さに相当する位置でレーザダイシングを停止する。溝1Aの深さは、化合物半導体素子の厚みの半分(中央位置)以上とすることが好ましい。
ステップS13:
ステップS13では、図18(b)に示すように、Si基板1の裏面に後述する溶融金属材料の濡れ性を改善する金属薄膜61を形成する。
詳細には、溝1Aの内壁面を覆うようにSi基板1の裏面に、後述する溶融金属材料の濡れ性を改善する性質を有する金属、ここではTi/Ni/Auの積層膜を例えばスパッタ法、真空蒸着法、又はプラズマCVD法で形成する。これにより、金属薄膜61が形成される。金属薄膜61としては、Ti/Ni/Au以外に、Au,Cu,Ni,Al,Ti,Pdから選ばれた1種類、或いは数種類を適宜に組み合わせた積層膜としても良い。
ステップS14:
ステップS14では、図18(c)に示すように、Si基板1の裏面でダイシングラインDLに沿ってレーザダイシングし、Si基板1から、各化合物半導体素子60を切り出す。化合物半導体素子60には、その裏面の全体から側面の所定高さまで覆うように、金属薄膜61が形成されている。化合物半導体素子60は、第1の実施形態の図4で示した化合物半導体素子10と同様に、複数の接続電極11が、矩形状の周縁における4辺のうちの3辺に沿って並列形成されている。
ステップS15:
ステップS15では、第1の実施形態のステップS3と同様に、樹脂回路基板の表面に凹部を形成する。
ステップS16:
ステップS16では、図19及び図21に示すように、化合物半導体素子60を樹脂回路基板20の凹部21内に固着する。
詳細には、樹脂回路基板20の凹部21内に、溶融金属材料62、ここでは錫(Sn)/銀(Ag)を用いて、化合物半導体素子60を樹脂回路基板20の凹部21の底面上で偏倚した位置に固着する。溶融金属材料としては、Sn/Ag以外に、例えばSn/Ag/ビスマス(Bi)を用いても良い。その他、Sn、鉛(Pb)、Ag、インジウム(In)、Bi、亜鉛(Zn)、アンチモン(Sb)、Cuのうちから、適宜に数種類を選択したものを用いることができる。具体的に、化合物半導体素子60は、その接続電極11が形成された3辺が、凹部21の周縁から0.01mm〜0.1mm程度、例えば0.05mm程度離れた箇所に位置する。接続電極11が形成されていない1辺が、凹部21の周縁から4mm程度以上、例えば10.05mm程度離れた箇所に位置する。
化合物半導体素子60には、その裏面の全体から側面の所定高さまで覆うように、溶融金属材料62の濡れ性を改善する金属薄膜61が形成されている。そのため、溶融金属材料62は、化合物半導体素子60の金属薄膜61が形成された部位、即ち化合物半導体素子60の裏面の全体から側面の所定高さまで接触する。更に、溶融金属材料62の化合物半導体素子60の側面に接触する部分では、溶融金属の表面張力により、当該側面から、凹部21の側壁面に向かって高さが漸減するなだらかな凸面62aが形成される。この凸面は、均一高さの平坦面に比べて表面積が大きい。溶融金属材料62は冷却により固化するが、固化した状態でも、同一の形状が保たれる。
図示の例では、化合物半導体素子60の接続電極11の形成された辺と凹部21の周縁との間でも、化合物半導体素子10の側面が金属材料62で覆われる様子を示すが、この構成に限定されるものではない。例えば、次の工程における金属ワイヤを可及的に短くすべく、化合物半導体素子60の接続電極11の形成された辺と凹部21の周縁とを殆ど接触させることも考えられる。この場合には、その微小な隙間には金属材料62は殆ど存しないと考えられる。金属材料62の放熱効果は、その広さ(表面積)に比例するため、この狭い部位に金属材料32が無くとも、特に問題はない。
ステップS17:
ステップS17では、第1の実施形態のステップ7と同様に、図20及び図22に示すように、化合物半導体素子10の接続電極11と樹脂回路基板20の接続電極28aとをワイヤボンディングして接続する。
以上により、本実施形態による半導体パッケージが作製される。
本実施形態では、樹脂回路基板20に形成された凹部21内に、化合物半導体素子60が固化した溶融金属材料62で固定配置される。化合物半導体素子60は、凹部21の底面上において、偏倚した位置に配置される。具体的に、化合物半導体素子60は、その周縁のうちで接続電極11が設けられた3辺については凹部21の周縁との距離が小さく、接続電極11が設けられていない1辺については凹部21の周縁との距離が大きい位置に配置される。そして、後者の位置に相当する化合物半導体素子60の周縁と凹部21の周縁との間の広い領域では、溶融金属材料62が化合物半導体素子60の側面を所定位置まで覆うように形成されている。この構成では、溶融金属材料62を通じて、化合物半導体素子60の底面のみならず側面(溶融金属材料62が覆う部分)からも効率良く放熱することができ、しかも金属材料32の占有面積が広いことから更に放熱が助長される。更に溶融金属材料62は、上記のように、当該側面から、凹部21の側壁面に向かって高さが漸減するなだらかな凸面62aを有するように形成される。この凸面62aは、均一高さの平坦面に比べて表面積が大きいため、放熱量が増大する。その一方で、前者の位置に相当する化合物半導体素子10の周縁と凹部21の周縁との間の狭い領域で、互いに対向する接続電極11と接続電極28aとが金属ワイヤ34で接続される。この構成では、金属ワイヤ34を可及的に短く形成することができるため、低抵抗伝送が可能となる。
以上説明したように、本実施形態によれば、比較的簡易な構成で、化合物半導体素子10の低抵抗伝送を達成すると共に、化合物半導体素子10の十分な高放熱性を低コストで確実に実現する半導体パッケージを得ることができる。
なお、本実施形態でも、第1の実施形態の変形例1,2のように、2辺、又は1辺に沿って接続電極11が形成された化合物半導体素子を樹脂回路基板の凹部内に溶融金属材料を用いて固定しても良い。この化合物半導体素子には、上記のステップS12〜S14で溶融金属材料の濡れ性を改善する金属薄膜が形成される。
(第3の実施形態)
本実施形態では、第1及び第2の実施形態及び諸変形例から選ばれた1種の半導体パッケージを適用した電源装置を開示する。
図23は、第3の実施形態による電源装置の概略構成を示す結線図である。
本実施形態による電源装置は、高圧の一次側回路41及び低圧の二次側回路72と、一次側回路71と二次側回路72との間に配設されるトランス73とを備えて構成される。
一次側回路71は、交流電源74と、いわゆるブリッジ整流回路75と、複数(ここでは4つ)のスイッチング素子76a,76b,76c,76dとを備えて構成される。また、ブリッジ整流回路75は、スイッチング素子76eを有している。
二次側回路72は、複数(ここでは3つ)のスイッチング素子77a,77b,77cを備えて構成される。
本実施形態では、一次側回路71のスイッチング素子76a,76b,76c,76d,76eが、上記の化合物半導体素子のAlGaN/GaN・HEMTとされている。一方、二次側回路72のスイッチング素子77a,77b,77cは、シリコンを用いた通常のMIS・FETとされている。
本実施形態では、比較的簡易な構成で、化合物半導体素子の低抵抗伝送を達成すると共に、化合物半導体素子の十分な高放熱性を低コストで確実に実現する半導体パッケージを、高圧回路に適用する。これにより、信頼性の高い大電力の電源回路が実現する。
(第4の実施形態)
本実施形態では、第1及び第2の実施形態及び諸変形例から選ばれた1種の半導体パッケージを適用した高周波増幅器を開示する。
図24は、第4の実施形態による高周波増幅器の概略構成を示す結線図である。
本実施形態による高周波増幅器は、ディジタル・プレディストーション回路81と、ミキサー82a,82bと、パワーアンプ83とを備えて構成される。
ディジタル・プレディストーション回路81は、入力信号の非線形歪みを補償するものである。ミキサー82aは、非線形歪みが補償された入力信号と交流信号をミキシングするものである。パワーアンプ83は、交流信号とミキシングされた入力信号を増幅するものであり、上記の化合物半導体素子のAlGaN/GaN・HEMTを有している。なお図24では、例えばスイッチの切り替えにより、出力側の信号をミキサー82bで交流信号とミキシングしてディジタル・プレディストーション回路81に送出できる構成とされている。
本実施形態では、比較的簡易な構成で、化合物半導体素子の低抵抗伝送を達成すると共に、化合物半導体素子の十分な高放熱性を低コストで確実に実現する半導体パッケージを、高周波増幅器に適用する。これにより、信頼性の高い高耐圧の高周波増幅器が実現する。
以下、半導体装置及びその製造方法の諸態様を、付記としてまとめて記載する。
(付記1)表面に第1の電極が形成された半導体素子と、
表面に第2の電極及び凹部が形成された基板と、
前記凹部内で前記半導体素子を固定する放熱性接着材料と
を含み、
前記半導体素子は、前記凹部内において、前記第1の電極と前記第2の電極とが近接するように偏倚した位置に固定されており、
前記第1の電極と前記第2の電極とが接続されており、
前記放熱性接着材料は、前記半導体素子の底面から側面の少なくとも一部まで被覆することを特徴とする半導体装置。
(付記2)前記凹部内において、
前記半導体素子の周縁のうちで前記第1の電極が位置する部位と、前記基板の前記凹部の周縁のうちで前記第2の電極が位置する部位とが第1の距離で対向しており、
前記半導体素子の周縁のうちで前記第1の電極が非形成の部位と、前記基板の前記凹部の周縁のうちで前記第2の電極が非形成の部位とが前記第1の距離よりも大きい第2の距離で対向しており、
前記放熱性接着材料は、前記半導体素子の前記第2の距離の部位における側面の少なくとも一部を被覆することを特徴とする付記1に記載の半導体装置。
(付記3)前記放熱性接着材料は、金属材料であることを特徴とする付記1又は2に記載の半導体装置。
(付記4)前記金属材料は、前記半導体素子の側面の少なくとも一部を被覆する部位が凸面状とされていることを特徴とする付記3に記載の半導体装置。
(付記5)前記半導体素子は、底面から、側面の前記金属材料が被覆する高さまで、前記金属材料の濡れ性を改善する金属膜が形成されていることを特徴とする付記3に記載の半導体装置。
(付記6)前記金属材料は、錫、鉛、銀、インジウム、ビスマス、亜鉛、アンチモン、銅のうちから選択された少なくとも1種を含むことを特徴とする付記3〜5のいずれか1項に記載の半導体装置。
(付記7)前記基板は、前記凹部の底面に放熱用金属が設けられていることを特徴とする付記1〜6のいずれか1項に記載の半導体装置。
(付記8)前記半導体素子は、化合物半導体素子であることを特徴とする付記1〜7のいずれか1項に記載の半導体装置。
(付記9)表面に第1の電極が形成された半導体素子と、表面に第2の電極及び凹部が形成された基板とを備えた半導体装置の製造方法であって、
前記基板の表面に凹部を形成する工程と、
前記半導体素子を、前記凹部内において、前記第1の電極と前記第2の電極とが近接するように偏倚した位置に配置し、放熱性接着材料を前記半導体素子の底面から側面の少なくとも一部まで被覆させて前記半導体素子を固定する工程と、
前記第1の電極と前記第2の電極とを接続する工程と
を含むことを特徴とする半導体装置の製造方法。
(付記10)前記凹部内に前記半導体素子を固定する際に、
前記凹部内において、
前記半導体素子の周縁のうちで前記第1の電極が位置する部位と、前記基板の前記凹部の周縁のうちで前記第2の電極が位置する部位とを第1の距離で対向させ、
前記半導体素子の周縁のうちで前記第1の電極が非形成の部位と、前記基板の前記凹部の周縁のうちで前記第2の電極が非形成の部位とを前記第1の距離よりも大きい第2の距離で対向させて、
前記放熱性接着材料を、前記半導体素子の底面から前記半導体素子の前記第2の距離の部位における側面の少なくとも一部まで被覆させることを特徴とする付記9に記載の半導体装置の製造方法。
(付記11)前記凹部内に前記半導体素子を固定する際に、
前記凹部内の記半導体素子の固定予定位置に、前記半導体素子のダミー素子を配置して、前記放熱性接着材料を供給し、
前記ダミー素子を除去して前記放熱性接着材料に前記固定予定位置を画定し、
前記半導体素子を、前記固定予定位置に固着することを特徴とする付記9又は10に記載の半導体装置の製造方法。
(付記12)前記放熱性接着材料は、金属材料であることを特徴とする付記10又は11に記載の半導体装置の製造方法。
(付記13)前記金属材料は、前記半導体素子の側面の少なくとも一部を被覆する部位が凸面状とされることを特徴とする付記12に記載の半導体装置の製造方法。
(付記14)前記凹部内に前記半導体素子を固定する際に、
前記半導体素子に、底面から、側面の前記金属材料が被覆する高さまで、溶融した前記金属材料の濡れ性を改善する金属膜を形成し、
前記凹部内に前記金属材料で前記半導体素子を固定することを特徴とする付記13に記載の半導体装置の製造方法。
(付記15)前記金属材料は、錫、鉛、銀、インジウム、ビスマス、亜鉛、アンチモン、銅のうちから選択された少なくとも1種を含むことを特徴とする付記12〜14のいずれか1項に記載の半導体装置の製造方法。
(付記16)前記半導体素子は、化合物半導体素子であることを特徴とする付記9〜15のいずれか1項に記載の半導体装置の製造方法。
(付記17)変圧器と、前記変圧器を挟んで高圧回路及び低圧回路とを備えた電源回路であって、
表面に第1の電極が形成された化合物半導体素子と、
表面に第2の電極及び凹部が形成された基板と、
前記凹部内で前記化合物半導体素子を固定する放熱性接着材料と
を含み、
前記化合物半導体素子は、前記凹部内において、前記第1の電極と前記第2の電極とが近接するように偏倚した位置に固定されており、
前記第1の電極と前記第2の電極とが接続されており、
前記放熱性接着材料は、前記化合物半導体素子の底面から側面の少なくとも一部まで被覆することを特徴とする電源回路。
(付記18)入力した高周波電圧を増幅して出力する高周波増幅器であって、
表面に第1の電極が形成された化合物半導体素子と、
表面に第2の電極及び凹部が形成された基板と、
前記凹部内で前記化合物半導体素子を固定する放熱性接着材料と
を含み、
前記化合物半導体素子は、前記凹部内において、前記第1の電極と前記第2の電極とが近接するように偏倚した位置に固定されており、
前記第1の電極と前記第2の電極とが接続されており、
前記放熱性接着材料は、前記化合物半導体素子の底面から側面の少なくとも一部まで被覆することを特徴とする高周波増幅器。
(付記19)半導体素子を、濡れ性を有する溶融金属材料を固化させて固定するに際して、
前記半導体素子に、底面から、側面の前記溶融金属材料が被覆する高さまで、前記溶融金属材料の濡れ性を改善する金属膜を形成し、
前記溶融金属材料を供給して前記半導体素子を固定することを特徴とする半導体装置の製造方法。
(付記20)前記半導体素子を半導体基板から切り出す際に、
前記半導体基板を、その裏面から所定の深さまでダイシングして溝を形成し、
前記半導体基板の裏面に前記溝内を覆うように前記金属膜を形成し、
前記半導体基板をダイシングして前記半導体素子を切り出すことを特徴とする付記19に記載の半導体装置の製造方法。
1 Si基板
1a 表面
1b 裏面
1A 溝
2 化合物半導体積層構造
2a バッファ層
2b 電子走行層
2c 中間層
2d 電子供給層
2e キャップ層
2A,2B,2C 電極用リセス
3 素子分離構造
4 ソース電極
5 ドレイン電極
6 ゲート絶縁膜
7 ゲート電極
10,40,50,60 化合物半導体素子
11,28a,28b,29a,29b 接続電極
20 樹脂回路基板
21,41,51 凹部
22 樹脂
23 Cu配線
24 ビア
25 金属コア
26,27 ソルダーレジスト
26a,26b,27a,27b 開口
30 ダミー素子
31a,31b スルーホール
32,33 金属材料
32a 固定予定位置
34 金属ワイヤ
61 金属薄膜
62 溶融金属材料
62a 凸面
71 一次側回路
72 二次側回路
73 トランス
74 交流電源
75 ブリッジ整流回路
76a,76b,76c,76d,76e,77a,77b,77c スイッチング素子
81 ディジタル・プレディストーション回路
82a,82b ミキサー
83 パワーアンプ

Claims (8)

  1. 表面に第1の電極が形成された半導体素子と、
    表面に第2の電極及び凹部が形成された基板と、
    前記凹部内で前記半導体素子を固定する放熱性接着材料と
    を含み、
    前記半導体素子は、前記凹部内において、前記第1の電極と前記第2の電極とが近接するように偏倚した位置に固定されており、
    前記第1の電極と前記第2の電極とが接続されており、
    前記凹部内において、前記半導体素子の周縁のうちで前記第1の電極が位置する部位と、前記基板の前記凹部の周縁のうちで前記第2の電極が位置する部位とが第1の距離で対向しており、前記半導体素子の周縁のうちで前記第1の電極が非形成の部位と、前記基板の前記凹部の周縁のうちで前記第2の電極が非形成の部位とが前記第1の距離よりも大きい第2の距離で対向しており、
    前記放熱性接着材料は、前記半導体素子の底面から前記半導体素子の前記第2の距離の部位における側面の少なくとも一部を被覆することを特徴とする半導体装置。
  2. 前記放熱性接着材料は、金属材料であることを特徴とする請求項1に記載の半導体装置。
  3. 前記金属材料は、前記半導体素子の側面の少なくとも一部を被覆する部位が凸面状とされていることを特徴とする請求項に記載の半導体装置。
  4. 前記半導体素子は、底面から、側面の前記金属材料が被覆する高さまで、前記金属材料の濡れ性を改善する金属膜が形成されていることを特徴とする請求項に記載の半導体装置。
  5. 表面に第1の電極が形成された半導体素子と、表面に第2の電極及び凹部が形成された基板とを備えた半導体装置の製造方法であって、
    前記基板の表面に凹部を形成する工程と、
    前記半導体素子を、前記凹部内において、前記第1の電極と前記第2の電極とが近接するように偏倚した位置に配置し、放熱性接着材料を前記半導体素子の底面から側面の少なくとも一部まで被覆させて前記半導体素子を固定する工程と、
    前記第1の電極と前記第2の電極とを接続する工程と
    を含み、
    前記凹部内に前記半導体素子を固定する際に、前記凹部内において、前記半導体素子の周縁のうちで前記第1の電極が位置する部位と、前記基板の前記凹部の周縁のうちで前記第2の電極が位置する部位とを第1の距離で対向させ、前記半導体素子の周縁のうちで前記第1の電極が非形成の部位と、前記基板の前記凹部の周縁のうちで前記第2の電極が非形成の部位とを前記第1の距離よりも大きい第2の距離で対向させ、前記放熱性接着材料を、前記半導体素子の前記第2の距離の部位における側面の少なくとも一部まで被覆させることを特徴とする半導体装置の製造方法。
  6. 前記凹部内に前記半導体素子を固定する際に、
    前記凹部内の記半導体素子の固定予定位置に、前記半導体素子のダミー素子を配置して、前記放熱性接着材料を供給し、
    前記ダミー素子を除去して前記放熱性接着材料に前記固定予定位置を画定し、
    前記半導体素子を、前記固定予定位置に固着することを特徴とする請求項5に記載の半導体装置の製造方法。
  7. 前記金属材料は、前記半導体素子の側面の少なくとも一部を被覆する部位が凸面状とされることを特徴とする請求項に記載の半導体装置の製造方法。
  8. 前記凹部内に前記半導体素子を固定する際に、
    前記半導体素子に、底面から、側面の前記金属材料が被覆する高さまで、溶融した前記金属材料の濡れ性を改善する金属膜を形成し、
    前記凹部内に前記金属材料で前記半導体素子を固定することを特徴とする請求項に記載の半導体装置の製造方法。
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