JP5923712B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP5923712B2 JP5923712B2 JP2013520419A JP2013520419A JP5923712B2 JP 5923712 B2 JP5923712 B2 JP 5923712B2 JP 2013520419 A JP2013520419 A JP 2013520419A JP 2013520419 A JP2013520419 A JP 2013520419A JP 5923712 B2 JP5923712 B2 JP 5923712B2
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- layer
- semiconductor device
- barrier layer
- group iii
- iii nitride
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- 229910052758 niobium Inorganic materials 0.000 description 1
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- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
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- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
Description
本発明の第1の実施形態に係る半導体装置について図面を参照しながら説明する。
図1は第1の実施形態に係るIII族窒化物半導体を用いた半導体装置の断面構成を模式的に示している。図1に示すように、本実施形態の半導体装置であるFETは、面方位が(111)面であるシリコン(Si)からなる基板101の主面の上に、厚さが200nm〜3500nm程度の窒化アルミニウムガリウム(AlyGa1−yN(但し、0≦y≦1))からなる単層又はAlの組成が互いに異なる積層体からなるバッファ層102と、それぞれIII族窒化物半導体からなるキャリア走行層103及びバリア層104とが順次形成されている。
以下、前記のように構成された、第1の実施形態に係る半導体装置の製造方法の一例を図2を参照しながら説明する。
以下に、キャップ層105を構成する単結晶と多結晶とが混在したAlNについて説明する。
図7に、GaNからなるキャリア走行層103と、その上に形成された厚さが10nmのAl0.2Ga0.8Nからなるバリア層104と、単結晶と多結晶とが混在したAlNからなり、厚さが20nmのキャップ層105とから構成された場合のキャップ層105と、キャリア走行層103に生じる2DEG層のキャリア濃度との関係を示す。比較用として、バリア層104の上にキャップ層105を設けない場合と、キャップ層105として、通常パッシベーション膜に用いられるSiN膜(厚さ100nm)を設けた場合と、AlNからなるキャップ層の形成方法を変えた場合とのキャリア濃度を共に表している。なお、ここでの検討においては、FETにパッシベーション膜109は形成されていない。
以下に、本発明に係る図1に示すFETと、SiNをパッシベーション膜として用いた従来のFETとの電気的特性を比較した結果を説明する。なお、従来のFETは、バリア層104の上にSiNよりなるパッシベーション膜109が直接に形成される構成、すなわちキャップ層105が設けられていない構成である。なお、基板101からバリア層104に至る層構造は、本発明に係るFETと同一である。
本発明に係るFETについて、バリア層104の厚さを変化させた場合に、バリア層104とキャリア走行層103との界面に生じるキャリアの濃度が、いかに変化するかを検討した。その結果を図9(a)及び図9(b)に示す。
本実施形態に係るFETにおいては、キャップ層105を構成するAlNの表面をSiNからなるパッシベーション膜によって保護することにより、AlNの表面を不活性化することができる。これにより、デバイス特性の向上を図ることができ、例えば、電流量を増大し、且つ電流コラプス現象を抑制することができる。
図10は第1の実施形態の一変形例に係るFETにおけるゲート電極の近傍領域の断面構成を拡大して示している。
以下、本発明の第2の実施形態に係るFETについて図11を参照しながら説明する。
以下、本発明の第3の実施形態に係るFETについて図13を参照しながら説明する。
以下に、第3の実施形態に係るFETの製造方法の一変形例を図15に示す。
以下、本発明の第4の実施形態に係るFETについて図16を参照しながら説明する。
図16に示すように、第4の実施形態に係るFETは、面方位の(111)面を主面とするSiからなる基板101の主面上に、それぞれIII族窒化物半導体からなるバッファ層102、キャリア走行層103及びバリア層104が順次形成されている。
以下、前記のように構成された、第4の実施形態に係るFETの製造方法の一例を図17及び図18を参照しながら説明する。
第4の実施形態に係るFETの動作特性について説明する。
図19及び図20は、第4の実施形態に係るFETの製造方法の第1変形例を示している。
次に、第4の実施形態に係る製造方法の第2変形例について図21及び図22を参照しながら説明する。第2変形例においては、キャップ層105をゲート制御層111よりも先に形成する。
次に、第4の実施形態の第3変形例に係るFETについて図23を参照しながら説明する。
第4の実施形態及び各変形例に係るFETを構成する、AlNからなるキャップ層105の表面を、例えばSiNからなるパッシベーション膜によって覆うことにより、キャップ層105の表面を不活性化することができる。その結果、デバイス特性の向上、例えば電流量の増大及び電流コラプス現象の抑制等を向上することができる。
第1〜第4の各実施形態に係るFETにおいて、図24(a)に示すように、キャップ層105に設ける第2の開口部105bを、バリア層104の上部を掘り込むにように形成し、ソース電極が第2の開口部105bを埋めるように設けてもよい。
以下、本発明の第5の実施形態に係るIII族窒化物半導体を用いた半導体装置について図25を参照しながら説明する。
第1〜第5の実施形態に係るIII族窒化物半導体を用いた半導体装置において、基板101には、シリコン(Si)に代えて、サファイア(単結晶Al2O3)、炭化シリコン(SiC)、窒化ガリウム(GaN)又は窒化アルミニウム(AlN)等を用いることができる。
102 バッファ層
103 キャリア走行層
104 バリア層
105 キャップ層
105a 第1の開口部
105b 第2の開口部
105c 第3の開口部
105d 第1の開口部
105e 第2の開口部
106 ゲート電極
107 ソース電極
108 ドレイン電極
109 パッシベーション膜
110 絶縁層
111 ゲート制御層
112 マスク層
113 2次元電子(2DEG)層
114 ショットキー電極
115 オーミック電極
116 保護膜
116a 第1の開口部
116b 第2の開口部
116c 第3の開口部
120 スペーサ層
301 GaN層
302 スペーサ層
303 低温AlN層
303a 単結晶のAlN
Claims (18)
- 基板と、
前記基板の上に形成された第1のIII族窒化物半導体よりなり、且つ前記基板の主面に沿う方向にキャリアが走行するキャリア走行層と、
前記キャリア走行層の上に形成され、前記第1のIII族窒化物半導体よりもバンドギャップが大きい第2のIII族窒化物半導体よりなるバリア層と、
前記バリア層の上に形成された電極と、
前記バリア層の上で且つ前記電極の側方の領域に形成され、単結晶と多結晶とが混在した第3のIII族窒化物半導体よりなるキャップ層とを備えている半導体装置。 - 請求項1において、
前記キャップ層は、前記バリア層との界面に沿う方向に部分的に単結晶領域が形成されている半導体装置。 - 請求項2において、
前記単結晶領域は、前記バリア層との界面の全面に又は島状に、且つ厚さ方向に対して不均一に形成されている半導体装置。 - 請求項2又は3において、
前記単結晶領域は、前記バリア層と接している半導体装置。 - 請求項1において、
前記キャップ層は、前記バリア層側から、単結晶層と多結晶層とに積層された2層構造よりなる半導体装置。 - 請求項1において、
前記キャップ層は、アルミニウム(Al)を含むIII族窒化物半導体よりなる半導体装置。 - 請求項6において、
前記キャップ層は、前記基板とは反対側の面が酸化されている半導体装置。 - 請求項1〜7のいずれか1項において、
前記キャップ層は、窒化アルミニウム(AlN)よりなり、
前記バリア層は、AlxGa1−xN(但し、0<x≦1)よりなり、
前記キャリア走行層は、GaNよりなる半導体装置。 - 請求項1において、
前記キャリア走行層と前記バリア層との間に設けられ、単結晶の窒化アルミニウム(AlN)よりなるスペーサ層をさらに備えている半導体装置。 - 請求項1において、
前記バリア層と前記電極との間に設けられたp型のIII族窒化物半導体層をさらに備えている半導体装置。 - 請求項10において、
前記p型のIII族窒化物半導体層は、AlxGa1−xN(但し、0≦x≦1)よりなる半導体装置。 - 請求項1において、
前記バリア層と前記電極との間に設けられた絶縁層をさらに備えている半導体装置。 - 請求項12において、
前記絶縁層は、酸化アルミニウム(Al2O3)よりなる半導体装置。 - 請求項1〜13のいずれか1項において、
前記バリア層は、前記電極の下側部分の厚さが前記電極の側方部分の厚さよりも小さい半導体装置。 - 基板の上に第1のIII族窒化物半導体よりなるキャリア走行層を形成する工程と、
前記キャリア走行層の上に第2のIII族窒化物半導体よりなるバリア層を形成する工程と、
前記バリア層を覆うように第3のIII族窒化物半導体よりなるキャップ層を形成する工程と、
前記キャップ層の一部を選択的に除去する工程と、
前記キャップ層の一部を除去する工程よりも後に、p型のIII族窒化物半導体よりなる制御層を形成する工程と、
前記制御層を形成する工程の後に、前記バリア層の上に電極を形成する工程とを備え、
前記キャップ層は、有機金属化学気相堆積法により形成され、
前記キャップ層の形成温度は、前記キャリア走行層の形成温度及び前記バリア層の形成温度よりも低い半導体装置の製造方法。 - 請求項15において、
前記キャップ層の形成温度は、600℃以上且つ900℃以下であり、
前記キャリア走行層の形成温度及び前記バリア層の形成温度は、いずれも1000℃以上である半導体装置の製造方法。 - 請求項15において、
前記キャップ層の一部を除去する工程において、前記キャップ層は、アルカリ性のエッチャントにより除去する半導体装置の製造方法。 - 請求項15〜17のいずれか1項において、
前記制御層を形成する工程は、
前記p型のIII族窒化物半導体層を形成した後に、前記p型のIII族窒化物半導体層における前記電極の形成領域を残して除去する工程と、
残された前記p型のIII族窒化物半導体層をアニールする工程とを含む半導体装置の製造方法。
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