JP5487066B2 - 半導体装置の検査方法 - Google Patents
半導体装置の検査方法 Download PDFInfo
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- JP5487066B2 JP5487066B2 JP2010224927A JP2010224927A JP5487066B2 JP 5487066 B2 JP5487066 B2 JP 5487066B2 JP 2010224927 A JP2010224927 A JP 2010224927A JP 2010224927 A JP2010224927 A JP 2010224927A JP 5487066 B2 JP5487066 B2 JP 5487066B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/956—Inspecting patterns on the surface of objects
- G01N21/95684—Patterns showing highly reflecting parts, e.g. metallic elements
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
- G01B11/00—Measuring arrangements characterised by the use of optical techniques
- G01B11/30—Measuring arrangements characterised by the use of optical techniques for measuring roughness or irregularity of surfaces
- G01B11/306—Measuring arrangements characterised by the use of optical techniques for measuring roughness or irregularity of surfaces for measuring evenness
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/93—Detection standards; Calibrating baseline adjustment, drift correction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Length Measuring Devices By Optical Means (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
Description
図1は本発明の実施の形態の半導体装置の検査方法によって検査される半導体装置の構造の一例を示す断面図、図2は図1に示す半導体装置の実装構造の一例を示す部分断面図、図3は図1に示す半導体装置の裏面側の構造の一例を示す裏面図、図4は図1に示す半導体装置の反り状態(上に凸)の一例を示す側面図、図5は図1に示す半導体装置の反り状態(下に凸)の一例を示す側面図である。
2 配線基板
2a 上面
2b 下面
2c ボンディングリード
2d 第1エリア(外周部)
2e 第2エリア(中央部)
3 封止体
4 半導体チップ
4a 主面
4b 裏面
4c 電極パッド
5 ワイヤ
6 半田ボール(外部端子)
7 実装基板
7a 端子
8 半田
9 吸着ブロック
10 レーザー発振部
10a レーザー
11 レーザー受光部
Claims (11)
- 配線基板上に半導体チップが搭載されて成る半導体装置の検査方法であって、
(a)前記配線基板の前記半導体チップが搭載された上面と反対側の下面に複数の外部端子が設けられた前記半導体装置を準備する工程と、
(b)前記複数の外部端子の平坦度を測定して前記半導体装置の良品/不良品を判定する検査を行う工程と、
を有し、
前記(b)工程では、前記配線基板の前記下面を下に向けて上に凸となるように前記配線基板が反る場合の凸側への方向を(+)方向とし、前記配線基板の前記下面を下に向けて下に凸となるように前記配線基板が反る場合の凸側への方向を(−)方向とした際に、前記平坦度の前記(+)方向の許容範囲が前記平坦度の前記(−)方向の許容範囲に比べて小さい平坦度規格を形成し、前記平坦度規格を用いて前記半導体装置の検査を行うことを特徴とする半導体装置の検査方法。 - 請求項1記載の半導体装置の検査方法において、前記(b)工程では、前記複数の外部端子のそれぞれにレーザーを照射して前記平坦度を測定することを特徴とする半導体装置の検査方法。
- 請求項2記載の半導体装置の検査方法において、前記外部端子は、半田ボールであることを特徴とする半導体装置の検査方法。
- 請求項3記載の半導体装置の検査方法において、前記(+)方向と前記(−)方向の判定は、MAX高さの前記半田ボールの位置とMIN高さの前記半田ボールの位置によって判定することを特徴とする半導体装置の検査方法。
- 請求項4記載の半導体装置の検査方法において、前記配線基板の前記下面を中央部と前記中央部の外側の外周部とに分けて、それぞれの箇所で前記MAX高さの前記半田ボールと前記MIN高さの前記半田ボールのどちらが存在しているかを検知し、この検知結果によって前記配線基板の反り方向が前記上に凸か前記下に凸かを判定することを特徴とする半導体装置の検査方法。
- 請求項4記載の半導体装置の検査方法において、前記配線基板は、樹脂基板であることを特徴とする半導体装置の検査方法。
- 請求項6記載の半導体装置の検査方法において、前記配線基板は、前記下面を下に向けて前記上に凸となるように反っていることを特徴とする半導体装置の検査方法。
- 請求項7記載の半導体装置の検査方法において、前記(+)方向の前記平坦度の前記許容範囲の上限値は、前記半導体装置の常温での前記平坦度の測定値をBとし、前記半導体装置のピーク温度での前記平坦度の測定値をDとし、前記半導体装置の加熱ピークにおける規格値をAとすると、B+(A−D)で表されることを特徴とする半導体装置の検査方法。
- 請求項8記載の半導体装置の検査方法において、前記配線基板の前記上面に樹脂製の封止体が形成されていることを特徴とする半導体装置の検査方法。
- 請求項9記載の半導体装置の検査方法において、前記封止体は、エポキシ系樹脂から成ることを特徴とする半導体装置の検査方法。
- 請求項10記載の半導体装置の検査方法において、前記配線基板の熱膨張係数と前記封止体の熱膨張係数は異なっていることを特徴とする半導体装置の検査方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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JP2010224927A JP5487066B2 (ja) | 2010-10-04 | 2010-10-04 | 半導体装置の検査方法 |
TW100133834A TWI464815B (zh) | 2010-10-04 | 2011-09-20 | Inspection method of semiconductor device |
US13/244,434 US8605277B2 (en) | 2010-10-04 | 2011-09-24 | Method of inspecting semiconductor device |
KR1020110099418A KR101774592B1 (ko) | 2010-10-04 | 2011-09-29 | 반도체 장치의 검사 방법 |
CN201110305644.8A CN102446785B (zh) | 2010-10-04 | 2011-09-30 | 检查半导体器件的方法 |
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JP2010224927A JP5487066B2 (ja) | 2010-10-04 | 2010-10-04 | 半導体装置の検査方法 |
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JP2012078248A JP2012078248A (ja) | 2012-04-19 |
JP5487066B2 true JP5487066B2 (ja) | 2014-05-07 |
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US (1) | US8605277B2 (ja) |
JP (1) | JP5487066B2 (ja) |
KR (1) | KR101774592B1 (ja) |
CN (1) | CN102446785B (ja) |
TW (1) | TWI464815B (ja) |
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US9279673B2 (en) | 2013-03-18 | 2016-03-08 | Stats Chippac, Ltd. | Semiconductor device and method of calibrating warpage testing system to accurately measure semiconductor package warpage |
JP5576543B1 (ja) * | 2013-09-12 | 2014-08-20 | 太陽誘電株式会社 | 回路モジュール |
CN103575721B (zh) * | 2013-11-07 | 2016-04-13 | 无锡英普林纳米科技有限公司 | 一种多层结构表面增强拉曼散射基底及其制备方法 |
CN105719981B (zh) * | 2014-12-04 | 2018-09-07 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
CN107263984B (zh) * | 2016-03-31 | 2021-01-12 | 日铁化学材料株式会社 | 聚酰亚胺树脂层叠体与其制造方法以及带有功能层的聚酰亚胺膜 |
JP6719113B2 (ja) * | 2016-06-27 | 2020-07-08 | 株式会社 コアーズ | 平坦基準面の測定方法及び平坦度測定装置 |
JP6306230B1 (ja) * | 2017-02-09 | 2018-04-04 | Ckd株式会社 | 半田印刷検査装置、半田印刷検査方法、及び、基板の製造方法 |
CN106839956A (zh) * | 2017-03-21 | 2017-06-13 | 杭州市特种设备检测研究院 | 起重机主梁腹板局部翘曲度检测装置 |
US11127612B2 (en) * | 2018-04-25 | 2021-09-21 | Micron Technology, Inc. | Testing semiconductor devices based on warpage and associated methods |
CN109300809B (zh) * | 2018-09-28 | 2021-10-26 | 上海微松工业自动化有限公司 | 一种晶圆植球封装系统 |
CN109285807B (zh) * | 2018-09-28 | 2023-01-20 | 上海微松工业自动化有限公司 | 一种晶圆平整固定设备 |
KR102620864B1 (ko) * | 2018-11-23 | 2024-01-04 | 에스케이하이닉스 주식회사 | 반도체 패키지 및 제조 방법 |
US10971409B2 (en) * | 2018-12-27 | 2021-04-06 | Micron Technology, Inc. | Methods and systems for measuring semiconductor devices |
JP6781969B1 (ja) * | 2019-08-18 | 2020-11-11 | 進 中谷 | 測定装置及び測定方法 |
JP6781963B1 (ja) * | 2019-11-14 | 2020-11-11 | 進 中谷 | 測定装置及び測定方法 |
KR102228802B1 (ko) * | 2019-11-22 | 2021-03-17 | (주)제이스텍 | 디스플레이 패널 pcb 본딩 공정 시 간섭무늬를 이용한 본딩불량 검사 방법 |
JP6903243B2 (ja) * | 2020-09-07 | 2021-07-14 | 進 中谷 | 測定装置及び測定方法 |
CN214407428U (zh) * | 2021-01-27 | 2021-10-15 | 京东方科技集团股份有限公司 | 平面度检测设备及系统 |
CN112964183B (zh) * | 2021-03-12 | 2022-04-12 | 四川涪盛科技有限公司 | 弧高测量方法 |
CN113945188B (zh) * | 2021-09-18 | 2023-08-08 | 番禺得意精密电子工业有限公司 | 分析连接器焊接面在回流焊过程中翘曲的方法及系统 |
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JP2010141010A (ja) * | 2008-12-10 | 2010-06-24 | Renesas Technology Corp | 半導体装置の製造方法 |
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- 2011-09-20 TW TW100133834A patent/TWI464815B/zh active
- 2011-09-24 US US13/244,434 patent/US8605277B2/en active Active
- 2011-09-29 KR KR1020110099418A patent/KR101774592B1/ko active IP Right Grant
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Also Published As
Publication number | Publication date |
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TWI464815B (zh) | 2014-12-11 |
US8605277B2 (en) | 2013-12-10 |
CN102446785A (zh) | 2012-05-09 |
TW201225195A (en) | 2012-06-16 |
JP2012078248A (ja) | 2012-04-19 |
US20120081702A1 (en) | 2012-04-05 |
KR20120035115A (ko) | 2012-04-13 |
KR101774592B1 (ko) | 2017-09-04 |
CN102446785B (zh) | 2015-06-17 |
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