JP5389672B2 - 表示装置 - Google Patents
表示装置 Download PDFInfo
- Publication number
- JP5389672B2 JP5389672B2 JP2009550530A JP2009550530A JP5389672B2 JP 5389672 B2 JP5389672 B2 JP 5389672B2 JP 2009550530 A JP2009550530 A JP 2009550530A JP 2009550530 A JP2009550530 A JP 2009550530A JP 5389672 B2 JP5389672 B2 JP 5389672B2
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- JP
- Japan
- Prior art keywords
- film
- metal film
- insulating film
- interlayer connection
- display device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Description
本願は、先の日本特許出願2008−010927号(2008年1月21日出願)の優先権を主張するものであり、前記先の出願の全記載内容は、本書に引用をもって繰込み記載されているものとみなされる。
本発明は、表示装置に関し、特に、上層金属膜と下層金属膜との間に開口部を有する絶縁膜を挟んだ、上層金属膜と下層金属膜との電気的な接続構造に関する。
特許文献1乃至4及び非特許文献1乃至2には、透明電極層や半導体層と直接接続ができるAl合金系材料が開示されている。
2 第1の金属膜(下層金属膜)
3 ゲート電極
4 ゲート端子
5 ゲート配線
6 第1の絶縁膜
7 半導体膜
8 接触膜
9 第2の金属膜(上層金属膜)
10 データ配線
11 ソース電極
12 ドレイン電極
13 データ端子
14 第2の絶縁膜
15 ゲート端子孔
16 画素接続孔
17 データ端子孔
20 画素電極
21 端子保護パターン
22 層間接続膜
23 第1の金属膜露出面
24 第1の絶縁膜エッジ部
25 露出面/エッジ部交点
26 第2の絶縁膜露出面
27 空間
28 ボイド
29 第2の絶縁膜エッジ部
50 アイランドパターン
201 絶縁膜
202 上層導電膜
203 下層導電膜
204 接続孔
205 内側領域
206 外側領域
207 介する導電部
208 層間接続材料
209 層間接続材料滴下位置
第1の金属膜2が露出する剥離工程は第1の金属膜をパターンニングした後の剥離工程、
第2の金属膜9が露出する剥離工程は第2の金属膜をパターンニングした後の剥離工程があることは[背景技術]と同じであるが、本実施例においては、カバー膜を配置しない特徴があるため、本工程、すなわち開口部をパターンニングした後の剥離工程が新たに追加となる。なお、この剥離工程では第1の金属膜2と第2の金属膜9とが共に露出することとなる。
[サンプル]
サンプル1:実施例1で説明した第1の絶縁膜エッジ部まで層間接続層22を形成したサンプル。
・第1の金属膜:[非特許文献1]、[非特許文献2]の合金膜及びNi5%含有Al-Ni膜、膜厚300nm
・第1の絶縁膜:膜厚SiNx膜、400nm、エッジ部下面端角度75°
・第2の絶縁膜:膜厚SiNx膜、250nm、エッジ部下面端角度50°
・層間接続膜(サンプル1〜3):平均粒径5nm程度のAuナノ粒子を溶媒中に分散させた導電性を有する液体材料を加熱し固化、膜厚60nm
・端子保護パターン:ITO膜、膜厚40nm
(1)上記サンプルについてACFを介してTCPバンプと接続し抵抗を測定(初期接続抵抗)、
(2)初期抵抗を測定したサンプルを、高温・高湿(85℃、湿度60%)の環境下で、TCP配線とゲート端子間にDC35V印加して、抵抗測定及び端子の腐食進行度合いチェック(顕微鏡観察)を経時的に実施。
初期抵抗:
(大) 比較サンプル≒サンプル1≒サンプル2≧サンプル3 (小)
高温・高湿試験後抵抗:
(大) 比較サンプル≫サンプル1≧サンプル2>サンプル3 (小)
高温・高湿試験後腐食の進行度合い:
(大) 比較サンプル≫サンプル1≧サンプル2>サンプル3 (小)
[サンプル]
サンプル3:実施例2で説明した第2の絶縁膜露出面26まで延在して層間接続層22を形成したサンプル。
・第1の金属膜(ゲート端子):[非特許文献1]、[非特許文献2]の合金膜及びNi5%含有Al-Ni膜、膜厚300nm
・第1の絶縁膜:SiNx膜、膜厚400nm、エッジ部下面端角度75°
・第2の絶縁膜:SiNx膜、膜厚250nm、エッジ部下面端角度50°
・層間絶縁膜形成前洗浄剤
サンプル3及び比較サンプル:ノニオン系界面活性剤
サンプル4:0.6%TMAHにて第1の金属膜を30nmエッチング、第1の絶縁膜下面端飛び出し量0.05μm以下
・層間接続膜(サンプル3、4):平均粒径5nm程度のAuナノ粒子を溶媒中に分散させた導電性を有する液体材料を加熱し固化、膜厚:60nm
・端子保護パターン:ITO膜、膜厚:40nm
(1)上記サンプルについてACFを介してTCPのバンプと接続し抵抗を測定(初期接続抵抗)、
(2)初期抵抗を測定したサンプルを、高温・高湿(85℃、湿度60%)の環境下で、TCP配線とゲート端子間にDC35V印加して、抵抗測定及び端子の腐食進行度合いチェック(顕微鏡観察)を経時的に実施。
初期抵抗:
(大) 比較サンプル≧サンプル3>サンプル4 (小)
高温・高湿試験後抵抗:
(大) 比較サンプル≫サンプル3>サンプル4 (小)
高温・高湿試験後腐食の進行度合い:
(大) 比較サンプル≫サンプル3≧サンプル4 (小)
Claims (16)
- 基板の上に配置された下層金属膜と、
前記下層金属膜の上に配置された開口部を有する絶縁膜と、
少なくとも前記開口部で露出した前記下層金属膜と、前記絶縁膜の開口壁を延在して被覆するように配置された導電性を有する液体材料を固化した層間接続層と、
前記層間接続層の上に前記層間接続層の被覆境界領域を越えて前記絶縁膜と接するように配置された上層金属膜と、
を含むコンタクトホールを有し、前記開口部で露出した前記下層金属膜の膜厚が、前記開口部で露出していない部分の膜厚よりも薄い、ことを特徴とする表示装置。 - 前記層間接続層が、前記絶縁膜の前記開口壁上端を超え前記開口部周縁の絶縁膜露出面まで延在していることを特徴とする、請求項1に記載の表示装置。
- 前記層間接続層の膜厚が、前記開口部で露出した前記下層金属膜の膜厚と、前記開口部で露出していない部分の前記下層金属膜の膜厚との差よりも厚いことを特徴とする、請求項1又は2に記載の表示装置。
- 前記下層金属膜が、少なくともゲート配線またはデータ配線と電気的に接続されているゲート端子孔部またはデータ端子孔部のコンタクトホールであることを特徴とする、請求項1乃至3のいずれか一つに記載の表示装置。
- 前記開口部で露出した前記下層金属膜が、少なくともドレイン電極と電気的に接続されている画素接続孔部のコンタクトホールであることを特徴とする、請求項1乃至4のいずれか一つに記載の表示装置。
- 前記下層金属膜の最上面に位置する金属膜がAlを主成分とする合金膜であることを特徴とする、請求項1乃至5のいずれか一つに記載の表示装置。
- 前記上層金属膜が、ITO、IZO、SnOのいずれかの材料から選択されることを特徴とする、請求項1乃至6のいずれか一つに記載の表示装置。
- 前記絶縁膜の最上面に位置する絶縁膜が有機膜であることを特徴とする、請求項1乃至7のいずれか一つに記載の表示装置。
- 前記最上面に位置する有機絶縁膜が、ノボラック樹脂、アクリル樹脂、スチレン樹脂のいずれかの材料を含む樹脂から選択されることを特徴とする、請求項8に記載の表示装置。
- 前記表示装置が、液晶表示装置であることを特徴とする、請求項1乃至9のいずれか一つに記載の表示装置。
- 基板上又は前記基板上層に設けられた第1の金属膜と、
前記第1の金属膜を被覆する絶縁膜と、
前記絶縁膜に設けられ、底部が前記第1の金属膜表面に少なくとも達して露出させる開口部に、導電性の液体材料を配置し、固化して形成され、開口底部の露出した前記第1の金属膜表面を被覆するとともに開口壁を少なくとも一部の高さまで被覆し、前記開口部での表面形状が凹状又は凸状の曲面とされる層間接続膜と、
前記層間接続膜の上に少なくとも前記層間接続膜の被覆領域を覆うように形成され、前記開口部での表面形状が、前記層間接続膜に対応して凹状又は凸状の曲面とされる第2の金属層と、
を含む接続構造を有する、ことを特徴とする表示装置。 - 前記導電性を有する液体材料を固化した前記層間接続層は、Au、Ag、Cu、Ni、Pt、Pd、ITOの少なくとも一つを含有することを特徴とする、請求項1乃至11のいずれか一つに記載の表示装置。
- 前記第1の金属膜は、前記開口部によって露出する領域に、所定の深さの凹部を有し、
前記第1の金属膜の前記凹部は、前記層間接続膜で埋められ、
前記層間接続膜の膜厚は、前記第1の金属膜の前記凹部の深さよりも厚い、ことを特徴とする請求項11又は12に記載の表示装置。 - 前記開口部において、前記開口壁をなす前記絶縁膜のエッジ部の下面端が、前記第1の金属膜の前記凹部の上端から前記開口部内側に突出し、
前記第1の金属膜の前記凹部と、前記絶縁膜のエッジ部の下面端の突出部で囲まれた空間が前記層間接続膜で埋められている、ことを特徴とする請求項13に記載の表示装置。 - 前記層間接続膜は、前記開口壁の被覆領域の境界に近づくにしたがって膜厚が薄くなる、ことを特徴とする請求項11乃至14のいずれか一つに記載の表示装置。
- 前記絶縁膜が、積層された複数の絶縁膜を含み、
前記層間接続膜は、積層された複数の絶縁膜のうち少なくとも最下層の絶縁膜の開口壁を被覆する、ことを特徴とする請求項11乃至15のいずれか一つに記載の表示装置。
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